Level 2 Advanced Transfer Cache - HP ML530 - ProLiant - 128 MB RAM Brief Manual

ProLiant ML530 High-Performance Technologies
Level 2 Advanced
Transfer Cache
allows Windows .NET to resolve logical processors to their associated physical
processors.
In summary, OSs that support Hyper-Threading include:
Microsoft Windows 2000 Server (counts logical processors)
•
Microsoft .NET Server (uses all logical processors, regardless of physical count)
•
Sun Solaris 8
•
These OSs will support Hyper-Threading, but they will need drivers:
NetWare v 5.0
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NetWare v 5.1
•
NetWare v 6.0
•
OSs that will not support Hyper-Threading include any Linux distribution.
OSs aware of Hyper-Threading schedule application threads to run on logical
processors in the same way they manage physical processors. With Hyper-Threading
technology, OSs schedule threads not only to separate processors, but also to separate
logical processors on a single physical processor.
Because of the way the processors are counted, and subsequently identified by the OS,
threads are always scheduled to logical processors on different physical processors
before multiple threads are scheduled to the same physical processor. This optimization
allows software threads to use different physical execution resources when possible.
The second logical processor can also be turned off when it is not needed. A HALT
instruction is issued to the inactive logical processor. Without this instruction, an OS may
execute on the idle logical processor a sequence of instructions that repeatedly checks
for work to perform. This so-called "idle loop" can consume significant execution
resources that could otherwise be used by the active logical processor.
Note: Hyper-Threading can be turned off in the ROM-Based Setup Utility (RBSU). This
may be necessary for testing or verifying performance gains for enterprise applications.
Also, it is possible that some applications not designed for Hyper-Threading may not
perform as well with Hyper-Threading turned on.
The principle behind caching is based on the probability that a processor will need
information it has recently accessed in system memory more often than a random piece
of information it has not accessed. Just as a carpenter uses a tool belt, the processor uses
the cache to hold the most recently used information closer for faster and more efficient
operation.
Typically, there are two levels of cache memory: primary Level 1 (L1) cache and
secondary Level 2 (L2) cache. The L1 cache resides within the processor core and holds
8 kB of recently accessed data. The L2 cache stores recently accessed data that is not
held in the L1 cache. When the processor needs data, it first looks in the L1 cache. If the
information is found in the L1 cache (known as a cache hit), the processor uses it without
a performance delay. If the information is not in the L1 cache, the processor searches the
512-kB data store in the L2 cache. The data store is organized in columns and rows.
Each row, or cache line, contains 64 bytes (512 bits) of data. To optimize performance,
data is written to or read from the L2 cache as a complete 512-kB cache line. The
512-bit cache line size in the Intel Xeon Processor is twice the size of the cache line in
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