SPECIFICATIONS General Frequency Range 136~174MHz 136~174MHz Number of channels Channel Stepping 5, 6.25, 10, 12.5, 20, 25, 30, 50KHz Antenna Impedance 50Ω Working temperature –20°C~+60°C Power Supply 13.8V DC± 15% (11.7~15.8V) Grounding Method Negative ground Current Transmitter: about 9.5A Receiver: about 600mA(max.) Frequency Stability ±...
CIRCUITDESCRIPTION Frequency configuration The receiver utilizes double conversion. The first IF is 38.850 MHz and the second IF is 450kHz. The first local oscillator signal is supplied from the PLL circuit. The PLL circuit in the transmitter generates the necessary frequencies. Fig. 1 shows the frequencies. 450KHz ANT SW IF SYSTEM...
First Mixer The signal from the RF amplifier is heterodyned with the first local oscillator signal from the PLL frequency synthesizer circuit at the first mixer (Q204) to create a 38.850MHz first intermediate frequency (1st IF) signal. The first IF signal is then fed through one pair of monolithic crystal filter (MCF : XF200 XF201) to further remove spurious signals.
Squelch Circuit The detection output from the FM IF IC (U200) passes through a noise amplifier (U201 2/2) to detect noise. A voltage is applied to the CPU (U2). The CPU controls squelch according to the voltage (SQIN) level. The signal from the RSSI pin of U200 is used for S-meter. The electric field strength of the receive signal can be known before the SQIN voltage is input to the CPU, and the scan stop speed is improved.
high and Q104 turns on. Q102 turns on and a voltage is applied to (8T). The CPU in the control unit monitors the PLL (U205) LD signal directly. When the PLL is unlocked during transmission, the PLL LD signal goes low. The CPU detects this signal and makes the TXC signal low.
at the antenna end and to stabilize transmission output at voltage and temperature variations. (See Fig. Q220 Q212 Q214 Q216 D210,D211 RF AMP DRIVE STAGE D203 DRIVE AMP FINAL AMP ANT SW POWER D230,D231 U204 VR200 U505 CONTROL 14pin Fig. 9 APC Circuit Control Circuit The CPU carries out the following tasks (See Fig.
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P14~P17 P85~P86 Q6,Q7 KEYBACKLIGHT Fig. 12 Display circuit Encode DCS and CTCSS data is output through 42 PIN of CPU. The signal passes through low-pass CR filter, and the signal attained goes into the D/A converter (U505). The high speed data of DTMF/2T/5T Tone is output through 58 PIN of CPU, The signal passes through low-pass CR filter, providing TX and SP output audio frequency, and has processed IDC after amplified by a U504(B/4).
D/A Converter The D/A converter (U505) is used to adjust MO modulation, AF volume, TV voltage, FC reference voltage, and PC POWER CONTROL voltage level. Adjustment values are sent from the CPU as serial data. The D/A converter has a resolution of 256 and the following relationship is valid.
ADJUSTMENT PCB Section Measurement Adjustment Specifications Item Condition /Remarks Test equipment Terminal Parts Method 1. Setting 1) Power supply voltage DC Power supply terminal : 13.8V 1) CH: TX high CV201 ±0.2V 2. VCO lock Digital voltmeter 2) CH: RX high CV200 ±0.2V voltage...
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Transmitter section Measurement Adjustment Specifications Item Condition Test equipment Terminal Parts Method /Remarks 9. 2-Tone CH : TX center (Wide/Narrow) 3kHz (Wide) ±150Hz Modulation Encoder deviation LPF:15kHz 1.5kHz (Narrow) ±100Hz analyzer or linear Knob HPF:OFF detector 4) Transmit (LPF15kHz) Oscilloscope 10.
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