Bios Post Code - TYAN TIGER I7322DP Manual

5.3 BIOS Post Code

POST (hex) Description
Test CMOS R/W functionality.
CFh:
Early chipset initialization:
C0h
-Disable shadow RAM
-Disable L2 cache (socket 7 or below)
-Program basic chipset registers
Detect memory
C1h:
-Auto-detection of DRAM size, type and ECC.
-Auto-detection of L2 cache (socket 7 or below
Expand compressed BIOS code to DRAM
C3h:
Call chipset hook to copy BIOS back to E000 & F000
C5h:
shadow RAM.
Expand the Xgroup codes locating in physical address
01h:
1000:0
Initial Superio_Early_Init switch
03h:
1.Blank out screen
05h:
2.Clear CMOS error flag
1. Clear 8042 interface
07h:
2. Initialize 8042 self-test
1. Test special keyboard controller for Winbond 977 series
08h:
Super I/O chips.
2. Enable keyboard interface.
1. Disable PS/2 mouse interface (optional).
0Ah:
2. Autodetect ports for keyboard & mouse followed by a
port & interface swap (optional).
3. Reset keyboard for Winbond 977 series Super I/O chips.
Test F000h segment shadow to see whether it is R/W-able
0Eh:
or not. If test fails, keep beeping the speaker.
Auto detect flash type to load appropriate flash R/W codes
10h:
into the run time area in F000 for ESCD & DMI support.
Use walking 1's algorithm to check out interface in CMOS
12h:
circuitry. Also set real-time clock power status, and then
check for override.
Program chipset default values into chipset. Chipset default
14h:
values are MODBINable by OEM customers.
Initial onboard clock generator if
16h:
Early_Init_Onboard_Generator is defined.
See also POST 26h.
Detect CPU information including brand, SMI type (Cyrix or
18h:
Intel) and CPU level (586 or 686).
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