Appendix Ii: Bios Post Code - TYAN Thunder K8QW Manual

Appendix II: BIOS POST Code

Code Beeps / Description
02h Verify Real Mode
03h Disable Non-Maskable Interrupt (NMI) 3Ch
04h Get CPU type
06h Initialize system hardware
08h Initialize chipset with initial POST
values
09h Set IN POST flag
0Ah Initialize CPU registers
0Bh Enable CPU cache
0Ch Initialize caches to initial POST values 4Ah
0Eh Initialize I/O component
0Fh Initialize the local bus IDE
10h Initialize Power Management
11h Load alternate registers with initial
POST values
12h Restore CPU control word during
warm boot
13h Initialize PCI Bus Mastering devices
14h Initialize keyboard controller
16h 1-2-2-3. BIOS ROM checksum
17h Initialize cache before memory
autosize
18h 8254 timer initialization
1Ah 8237 DMA controller initialization
1Ch Reset Programmable Interrupt
Controller
20h 1-3-1-1. Test DRAM refresh
22h 1-3-1-3. Test 8742 KBD Controller
24h Set ES segment register to 4 GB
26h Enable A20 line
28h Autosize DRAM
29h Initialize POST Memory Manager
2Ah Clear 512 KB base RAM
2Ch 1-3-4-1. RAM failure on address
2Eh 1-3-4-3. RAM failure on data bits of
low byte of memory bus
2Fh Enable cache before system BIOS
shadow
30h 1-4-1-1. RAM failure on data bits of
high byte of memory bus
32h Test CPU bus-clock frequency
33h Initialize Phoenix Dispatch Manager
36h Warm start shut down
38h Shadow system BIOS ROM
Code
3Ah Autosize cache
Advanced configuration of chipset registers
3Dh Load alternate registers with CMOS values
42h Initialize interrupt vectors
45h POST device initialization
46h 2-1-2-3. Check ROM copyright notice
48h Check video configuration against CMOS
49h Initialize PCI bus and devices
Initialize all video adapters in system
4Bh QuietBoot start (optional)
4Ch Shadow video BIOS ROM
4Eh Display BIOS copyright notice
50h Display CPU type and speed
51h Initialize EISA board
52h Test keyboard
54h Set key click if enabled
58h 2-2-3-1. Test for unexpected interrupts
59h Initialize POST display service
5Ah Display prompt "Press F2 to enter SETUP"
5Bh Disable CPU cache
5Ch Test RAM between 512 and 640 KB
60h Test extended memory
62h Test extended memory address lines
64h Jump to UserPatch1
66h Configure advanced cache registers
67h Initialize Multi Processor APIC
68h Enable external and CPU caches
69h Setup System Management Mode (SMM)
area
6Ah Display external L2 cache size
6Bh Load custom defaults (optional)
6Ch Display shadow-area message
6Eh Display possible high address for UMB
recovery
70h Display error messages
72h Check for configuration errors
76h Check for keyboard errors
7Ch Set up hardware interrupt vectors
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Beeps / Description