TYAN THUNDER K8HM Manual page 72

3.9.1 – North Bridge Chipset Configuration Sub-Menu
This menu gives options for customizing memory & Hypertransport settings.
Select a menu by highlighting it using the Arrow (á/â) keys and pressing Enter.
The settings are described on the following pages.
Main Advanced
NorthBridge Chipset Configuration
4 Memory Configuration
4 ECC Configuration
4 IOMMU Option Configuration
CAS latency (Tcl)
RAS/CAS Delay (Trcd)
Min Active RAS (Tras)
Row Precharge Time (Trp) :X CLK
RAS/RAS Delay (Trrd)
Row Cycle (Trc)
Row Refresh Cycle (Trfc)
Read Write Delay (Trwt)
Read Preamble
Asynchronous Latency
Feature
NorthBridge Chipset Configuration
CAS Latency (Tcl)
RAS/CAS Delay (Trcd)
Min Active RAS (Tras)
BIOS Setup Utility
PCI/PnP Boot
:XX
:X CLK
:X CLK
:X CLK
:X CLK
:X CLK
:X CLK
:X ns
:X ns
Option
This controls the timing delay (in clock
Read only cycles) before SDRAM starts a read
command after receiving it.
When DRAM is refreshed, both rows
and columns are addressed
separately. This setup item allows you
to determine the timing of the transition
Read only
from RAS (row address strobe) to CAS
(column address strobe). The less the
clock cycles, the faster the DRAM
performance.
This setting allows you to select the
number of clock cycles allotted for the
RAS pulse width, according to DRAM
Read only
specifications. The less the clock
cycles, the faster the DRAM
performance.
72
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