Fbwc Cache; Super-Capacitor; Capturing Data During Power Loss - HP 273914-B21 - Smart Array 6404/256 RAID Controller Technology Brief

Smart array controller technology
Hide thumbs Also See for 273914-B21 - Smart Array 6404/256 RAID Controller:
Table of Contents

Advertisement

Figure 8. FBWC block diagram
Side band
control
signals
Cache module
Cache module
System board
System board
* Cache tracks that have been written over are designated as "dirty"
** Two wire interface (TWI)

FBWC cache

The FBWC cache module with a field programmable gate array (FPGA), DDR2 DRAMs, and NAND
flash devices can support up to 1 GB of DDR2 memory and up to 72 data bits (64 data bits plus 8
ECC bits). The FBWC can support up to 800 Mbps data rate when the Smart Array controller is
driving the DDR2 bus. When the FPGA is driving the bus in a data recovery situation, the data rate is
266 Mbps. The FBWC module connects to the Smart Array controller through a 244-pin mini-DIMM
connector.
At the time of publication, the FBWC cache is supported on the Smart Array 410i with support for
other present generation Smart Array controllers to follow in the first quarter of 2010.

Super-capacitor

The Super-cap module sub-assembly consists of two 35 Farad 2.7V capacitors, configured in series,
providing 17 Farads at up to 5.4V. The charger maintains the Super-cap at 4.8V, providing the
required amount of power to complete backup operations while extending the life of the Super-cap.
The charger also monitors Super-cap health and activates LED indicators on the FBWC module to
warn of impending failure. The Super-Cap module is contained within the same form factor and
housing as the HP 650 mAh P-Series battery used in the HP BBWC.

Capturing data during power loss

Loss of power in a server using the FBWC prompts the FPGA to copy data contained in the DRAM to
the NAND flash devices residing on the cache module. The Super-caps supply the energy needed to
power the FBWC system while performing the data backup operation.
NAND Flash
NAND Flash
4b 33MHz
4b 33MHz
FPGA
133 MHZ DDR IF
Command
& address
Register
400 MHZ DDR IF
Cache dirty N*
Reset N
RoC
Reg reset N
TWI**
Super-cap
In off-module pack connecting to
4b 33MHz
4b 33MHz
cache module
PROM
DRAM
8X
DRAM
DRAM
8X
8X
22

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

381513-b21 - smart array p800 controller raid

Table of Contents