Yaesu VX-7R - TECHNICAL Service Manual page 8

Circuit Description
(5) 0.5 - 30 MHz Reception
Received signals between 0.5 and 30 MHz pass through
the Triplexer circuit, low-pass filter circuit, HF T/R switch
circuit and protector diode D1003 before additional fil-
tering by a band-pass filter prior to application to RF
amplifier Q1009 (2SC4915-0). The amplified RF signal
is passed through a band-pass filter to first mixer Q1013
(2SC4915-0). Meanwhile, HF output from the VCO-
UNIT is amplified by Q1018 and applied through diode
T/R switch D1046 to mixer Q1013 as the first local signal.
The 47.25-MHz intermediate frequency product of the
mixer is delivered to the AF-UNIT.
The TUNE voltage from the CPU on the CNTL-UNIT
is amplified by DC amplifier Q3017 and applied to var-
actors D1013 (HVR100) in the variable frequency band-
pass filters. By changing the electrostatic capacitance of
the varactors, optimum filter characteristics are provid-
ed for each specific operating frequency.
(6) 540 - 999 MHz Reception
Received signals between 540 and 999 MHz pass
through the high-pass filter circuit, T/R switch D1004
(1SV271) prior to application to RF amplifier Q1002
(2SC5277). The amplified RF signal is passed through a
band-pass filter to first mixer Q1010 (2SC5277). Mean-
while, UHF output from the VCO-UNIT is amplified by
Q1016 and applied through diode T/R switch D1045 to
mixer Q1010 as the first local signal.
The 47.25-MHz intermediate frequency product of the
mixer is delivered to the AF-UNIT.
The TUNE voltage from the CPU on the CNTL-UNIT
is amplified by DC amplifier Q3017 and applied to var-
actors D1015 and D1017 (HVC355B) in the variable fre-
quency band-pass filters. By changing the electrostatic
capacitance of the varactors, optimum filter characteris-
tics are provided for each specific operating frequency.
(7) 47.25-MHz First Intermediate Frequency
The 47.25-MHz first intermediate frequency from the
first mixers is delivered from the RF-UNIT to the AF-
UNIT through jacks J1008 and J2001. On the AF-UNIT,
the IF for AM and FM-narrow signals is passed through
NAR/WIDE switch D2001 (DAP222) and the 47.25-MHz
monolithic crystal filter (MCF) XF2001 to narrow IF am-
plifier Q2002 (2SC4915-0) for input to pin 16 of the Nar-
row IF IC Q2016 (TA31136FN), after amplitude limiting
by D2003 (DA221).
Meanwhile, a portion of the output of 11.7-MHz crys-
8
tal X1001 on the RF-UNIT is multiplied fourfold by Q2004
(2SC4915-0) and Q2012 (2SC4154E) to provide the 46.8-
MHz second local signal, applied to the Narrow IF IC.
Within the IC, this signal is mixed with the 47.25-MHz
first intermediate frequency signal to produce the 450
kHz second intermediate frequency.
This second IF is filtered by ceramic filter CF2002
(ALFYM450F=k) and amplified by the limiting amplifi-
er within the Narrow IF IC before quadrature detection
by ceramic discriminator CD2001 (CDBM450C7).
Demodulated audio is passed from pin 9 of the Nar-
row IF IC through the "Mute" analog switch Q2029
(2SJ364) and squelch gate Q2036 (2SJ364) before de-em-
phasis at Q2028 (DTC144EE).
The resulting audio is amplified by AF amplifier Q2040
(TDA7233D) and fed through the MIC/EAR jack J2002
to internal speaker SP1001 or an external earphone.
(8) Squelch Control
Signal components in the neighborhood of 15 kHz con-
tained in the discriminator output pass through an ac-
tive band-pass filter composed of R2059, R2060, R2062,
C2076, C2078 and the operational amplifier between pins
7 and 8 within Narrow IF IC Q2016. They are then recti-
fied by D2012 and D2013 (MC2850) to obtain a DC volt-
age corresponding to the level of noise. This voltage is
fed to pin 49 of CPU Q3035 (HD6472237TF10), which
compares the input voltage with a previously set thresh-
old. When the input voltage drops below the threshold,
normally due to the presence of a carrier, the CPU turns
on squelch gate Q2036 and allows any demodulated au-
dio to pass. At the same time, Q3001 and/or Q3003 and/
or Q3004 goes on, causing the BUSY/TX lamp D3033
(FRGB1312CE-10-TF) to light.
Transmitter Signal Flow
(1) 145-MHz-Band Transmit/Receive Switching
Closing PTT switch S2002 on the AF-UNIT pulls the
base of Q3008 (DTA144EE) low, causing the collector to
go high. This signal is fed to pin 33 (PTT) of CPU Q3035,
allowing the CPU to recognize that the PTT switch has
been pushed. When the CPU detects closure of the PTT
switch, pin 10 (TX) goes high. This control signal is de-
livered to the RF-UNIT, where it switches Q1044 (UMW1)
and Q1043 (CPH6102) to produce the TX control signal
that activates Q1046 (2SA1774). At the same time, PLL
division data is fed to PLL IC Q1019 (MB15A01PFV1)
from the CPU, to disable the receiver power saver. Also,