Yaesu VX-7R - TECHNICAL Service Manual page 10

Circuit Description
PLL Frequency Synthesizer
PLL IC Q1019 on the RF-UNIT consists of a data shift
register, reference frequency divider, phase comparator,
charge pump, "intermittent operation" circuit, and band
selector switch. Serial PLL data from the CPU is con-
verted into parallel data by the shift register in the PLL
IC and is latched into the comparative frequency divid-
er and reference frequency divider to set a frequency
dividing ratio for each. An 11.7-MHz reference signal
produced by X1001 is fed to "REF" pin 1 of the PLL IC.
The internal reference frequency divider divides the 11.7-
MHz reference by 2,050 (or 1,640) to obtain a reference
frequency of 5 kHz (or 6.25 kHz), which is applied to the
phase comparator. Meanwhile, a sample of the output
of VHF VCO Q4004 or UHF VCO Q4002 or 50 MHz VCO
Q4005 on the VCO-UNIT, buffered by Q4006, is fed to
the PLL IC, where it is divided by the internal compara-
tive frequency divider to produce a comparative frequen-
cy which also is applied to the phase comparator. The
phase comparator compares the phase between the ref-
erence frequency and comparative frequency to output
10
a pulse corresponding to the phase difference between
them. This pulse is fed to the charge pump, and the out-
put from the charge pump passes through a loop filter
composed of L1044, R1089, C1175, and either R1090,
C1192, R1103 and C1195 for VHF, or R1086, C1189, R1102
and C1194 for UHF, or R1091, C1193, R1104 and C1196
for 50 MHz, which convert the pulse into a correspond-
ing smoothed varactor control voltage (VCV). The VCV
is applied to varactors D4004 and D4013 (1SV325) in the
VHF VCO tank circuit, or to varactor D4001 (HVC355B)
in the UHF VCO tank circuit, or to varactors D4007 and
D4008 (1SV325) in the 50 MHz VCO, to eliminate any
phase difference between the reference frequency and
comparative frequency, thus locking the VCO oscillation
frequency to the reference crystal. The VCO frequency
is determined by the frequency-dividing ratio sent from
the CPU to the PLL IC. During receiver power save op-
eration, the PLL circuit operates intermittently to reduce
current consumption, for which the "intermittent oper-
ation" control circuit reduces the lock-up time.