Texas Instruments LMK5C33216AEVM User Manual
Texas Instruments LMK5C33216AEVM User Manual

Texas Instruments LMK5C33216AEVM User Manual

Evaluation module

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User's Guide
LMK5C33216AEVM Evaluation Module
The LMK5C33216AEVM is an evaluation module for the LMK5C33216A Network Clock Generator and
Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping.
1
Introduction.............................................................................................................................................................................2
Start......................................................................................................................................................................4
Configuration..................................................................................................................................................................6
3.1 Power Supply.....................................................................................................................................................................
3.2 Logic Inputs and Outputs...................................................................................................................................................
3.3 Switching Between I2C and SPI......................................................................................................................................
3.4 Generating SYSREF Request..........................................................................................................................................
3.5 XO Input...........................................................................................................................................................................
Inputs....................................................................................................................................................13
Outputs...................................................................................................................................................................13
3.8 Status Outputs and LEDS................................................................................................................................................
3.9 Requirements for Making Measurements........................................................................................................................
4 EVM Schematics...................................................................................................................................................................
4.1 Power Supply Schematic.................................................................................................................................................
4.2 Alternative Power Supply Schematic...............................................................................................................................
4.3 Power Distribution Schematic..........................................................................................................................................
4.4 LMK5C33216A and Input References IN0 to IN1 Schematic..........................................................................................
4.8 XO Schematic..................................................................................................................................................................
4.9 Logic I/O Interfaces Schematic........................................................................................................................................
Schematic.....................................................................................................................................................20
Materials.............................................................................................................................................................21
5.1 Loop Filter and Vibration Nonsensitive Capacitors..........................................................................................................
6.1 Using the Start Page........................................................................................................................................................
6.2 Using the Status Page.....................................................................................................................................................
Page........................................................................................................................................................33
6.4 Using APLL1, APLL2, and APLL3 Pages........................................................................................................................
6.6 Using the Validation Page................................................................................................................................................
Page.......................................................................................................................................................38
6.8 Using the Outputs Page...................................................................................................................................................
6.9 EEPROM Page................................................................................................................................................................
Page.......................................................................................................................................................41
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SNAU295 - JULY 2024
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ABSTRACT

Table of Contents

Characteristics..............................................................................................................................14
Schematic........................................................................................................................17
Schematic........................................................................................................................18
Schematic....................................................................................................................19
Software..................................................................................................................28
Copyright © 2024 Texas Instruments Incorporated
Table of Contents
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  • Page 1: Table Of Contents

    Table of Contents User's Guide LMK5C33216AEVM Evaluation Module ABSTRACT The LMK5C33216AEVM is an evaluation module for the LMK5C33216A Network Clock Generator and Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping. Table of Contents Introduction.....................................2 2 EVM Quick Start..................................4...
  • Page 2: Introduction

    Introduction www.ti.com 1 Introduction Overview The LMK5C33216AEVM is an evaluation module for the LMK5C33216A Network Clock Generator and Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping. The LMK5C33216A integrates three Analog PLLs (APLL) and three Digital PLLs (DPLL) with programmable loop bandwidth.
  • Page 3 OUT13_N OUT5_N OUT13_P OUT5_P OUT0_P OUT3_P OUT0_N OUT3_N OUT1_N OUT2_N OUT1_P OUT2_P VIN1 VIN2 Figure 1-1. LMK5C33216AEVM Default Setting of Jumpers and DIP Switches SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 4: Evm Quick Start

    1 second on, 1 second off continuously. After clicking the Identify button, the LED flashes quickly at about 0.5 second on, 0.5 second off for about 5 seconds. LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 5 Wait to confirm the change. This can take some time for the DPLL status bits to reflect lock. Figure 2-2. Read Status Bits Measure Measurements can now be made at the clock outputs. SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 6: Evm Configuration

    R76 is installed by default. Jumper header for I C/SPI interface (MCU to LMK5C33216A) SCL or SCK busy indication LED. USB Port for MCU LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 7 OUT12_N OUT4_N OUT13_N OUT5_N OUT13_P OUT5_P OUT0_P OUT3_P OUT0_N OUT3_N OUT1_N OUT2_N OUT1_P OUT2_P VIN1 VIN2 Figure 3-1. Key Components - EVM Top Side SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 8: Power Supply

    Figure 3-2. Default Power Jumper Configuration Figure 3-2 shows the default power jumper locations and settings. Table 3-2 shows the suggested power configurations for the LMK5C33216A LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 9: Logic Inputs And Outputs

    Table 3-3. Device Start-Up Modes GPIO1 INPUT LEVEL START-UP MODE C Mode High SPI Mode The input levels on these pins are sampled only during POR. SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 10: Switching Between I2C And Spi

    Communication protocols must be set in TICS Pro. From the menu bar, select USB communications → Interface to get the Communication Setup window and change the protocol. Figure 3-6. Communication Setup Window (Changing from I2C to SPI) LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 11: Generating Sysref Request

    (DPLL not used), then the XO frequency can have an integer relationship with the APLL output frequency. The XO input of the LMK5C33216A has programmable on-chip input termination and AC-coupled input biasing options to support any clock interface type. SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 12: External Clock Input

    Take care if more than one device is installed to remove resistors to power down unused oscillators and isolate the outputs as described above. LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 13: Reference Clock Inputs

    Status outputs signals can be configured on the GPIO0, GPIO1, and GPIO2 pins. The status output types are 3.3V LVCMOS or NMOS open-drain. 3.9 Requirements for Making Measurements When performing measurements with the LMK5C33216AEVM, the following procedures must be completed: 1. Make sure all required outputs have proper termination components installed to match the desired output types.
  • Page 14: Typical Phase Noise Characteristics

    2. Outputs were configured as HSDS outputs following the methods described in Section 3.9. Figure 3-13. APLL3 122.88MHz Phase Noise Figure 3-12. APLL3 245.76MHz Phase Noise Performance Performance Figure 3-14. APLL3 491.52MHz Phase Noise Performance LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 15: Evm Schematics

    23.2k 10uF GND[CP] 10nF 13.3k LP38798SD-ADJ/NOPB LDO2 R202 IN[CP] OUT[FB] 10uF C155 0.01uF 23.2k 10uF GND[CP] 10nF 13.3k LP38798SD-ADJ/NOPB Figure 4-2. Alternative Power Supply SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 16: Power Distribution Schematic

    0.1uF 10uF 0.1uF FB11 VDD_APLL3 VDD_APLL3 0.1uF 10uF 0.1uF GND TEST POINTS TP19 TP20 TP21 TP22 TP23 TP24 TP25 TP26 Figure 4-3. Power Distribution LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 17: Lmk5C33216A And Input References In0 To In1 Schematic

    OUT3_N OUT3_A_N SMA_O3_N R173 0.1uF 0.1uF ClassName: OUT_LenMatch1a ClassName: OUT_LenMatch1b R174 OUT2_N ClassName: OUT_LenMatch1a ClassName: OUT_LenMatch1b OUT3_N Figure 4-5. Clock Outputs OUT0 to OUT3 SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 18: Clock Outputs Out4 To Out9 Schematic

    R108 C115 C116 OUT8_N OUT8_A_N SMA_O8_N OUT9_N OUT9_A_N SMA_O9_N R183 R117 R184 R119 0.1uF 0.1uF OUT8_N OUT9_N Figure 4-6. Clock Outputs OUT4 to OUT9 LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 19: Clock Outputs Out10 To Out15 Schematic

    ClassName: XO_trace ClassName: XO_trace R210 VCC_XO_FILT OUTPUT R211 VCC_XO_FILT CLK+ CLK- 0.1uF EN_XO 0.1uF ClassName: XO_trace CDC64XX-2520 ClassName: XO_trace ROX252 2S4 Figure 4-8. XO SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 20: Logic I/O Interfaces Schematic

    VBUS U2A_3V3 VUSB HTST-115-01-L-DV VUSB VSSU BSS138 AVSS1 AVCC1 AVSS2 DVCC1 DVSS1 DVCC2 DVSS2 C142 C143 C144 0.1uF 0.1uF 0.1uF Figure 4-10. USB MCU LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 21: Evm Bill Of Materials

    C116, C117, C118, C119, C120, C121, C122, C123, C124, C125, C126, C127, C128 C131 CAP, CERM, 22uF, 10V, +/- 20%, X5R, LMK212BJ226MG-T Taiyo Yuden 22uF 0805 SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 22 J15, J16, J17, J18, J19, J20, J21, J22, J23, J24, J25, J26, J27, J28, J29, J30, J31, J32, J33, J34, J35, J36, J37, J38, J39, J40 LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 23 R20, R21, R22, R23, R25, R41, R52, R55, R61, R64, R66, R71, R73, R150, R151, R152, R153, R154, R155, R156, R157, R158, R163, R164, R212 SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 24 RES, 1.80 k, 0.1%, 0.1 W, 0603 RT0603BRD071K8L Yageo America S1, S2, S4 Switch, SPST 4 Pos, Top Actuated, 219-4LPST Electrocomponents Switch, Slide, SPST 2 poles, SMT 219-2LPST Electrocomponents LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 25 CAP, CERM, 0.1µF, 50V,+/- 5%, C0G/ C3225C0G1H104J250AA 0.1uF NP0, 1210 C81, C83, C84, CAP, CERM, 0.1uF, 25V, +/- 5%, X7R, C0603C104J3RACTU Kemet 0.1uF C85, C87 0603 SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 26 R204, R205 R192, R193 RES, 100, 1%, 0.063 W, AEC-Q200 CRCW0402100RFKED Vishay-Dale Grade 0, 0402 R207 RES, 0, 5%, 0.1 W, 0603 RC0603JR-070RL Yageo LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 27: Loop Filter And Vibration Nonsensitive Capacitors

    47nF 06035C473JAT2A, 0603 C0805X473G3GEC7800, C0G/NP0, 0805 C0805C473J3GACTU, C0G/NP0, 0805 0.1µF C0603C104J3RACTU, 0603 GRM31C5C1E104JA01L, C0G/NP0, 1206 TAJR104K020RNJ, Tantalum, 0805 0.47µF GRM188R71A474KA61D, 0603 F921C474MPA, Tantalum, 0805 SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 28: Appendix A - Tics Pro Lmk5B33216 Software

    PLL R-divider and phase detector preview to the right. Figure 6-2. Step 1 and 2: XO Input and Clock Inputs LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 29 Set the clock output for ZDM. The PLL drives the PLL source mux for the selected output set for ZDM. Figure 6-4. Step 4: Zero Delay Mode SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 30 Output Clock Settings to Device button. By default, the analog PLL frequencies are shown. The DPLL calculated frequency from step 6, however, results in exact output frequencies. LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 31 To calculate the DPLL divider settings, select which DPLL loop filters and dividers to calculate and press the Run Script button. The software now runs and calculates the necessary settings. Figure 6-7. Step 7: Run Script SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 32: Using The Status Page

    Clear Latched Bits button is pressed. This gives additional insight into the behavior of the device. Press the Soft-chip reset button in the toolbar to reset the device and restart the lock. Figure 6-8. Status Page LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 33: Using The Input Page

    When using both feedback dividers, a requirement is not that the TDC rates are exactly the same; only that the TDC rates are within ±5% for the two DPLL feedback configurations. Figure 6-9. APLL or DPLL Frequency Selection SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 34: Cascaded Configurations

    APLLs can share priorities; if all APLL priorities are set to 0, then all APLLs starts up simultaneously. Figure 6-11. Cascade APLL Start Priorities LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 35: Using Apll1, Apll2, And Apll3

    When the DPLL is not used, the APLLs support an APLL-only mode with a programmable 24-bit denominator. Support for this mode is currently not implemented in the TICS Pro software. Figure 6-13. APLL1 Page SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 36 DPLLx_HOLD_SLEW_STEP is NOT equal to 0, otherwise the adjustment does not occur. The recommended DPLLx_HOLD_SLEW_STEP value is 63 (maximum value). A value of 63 results in the fastest adjustment. Figure 6-16. APLL DCO Controls LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 37: Using The Dpll1, Dpll2, And Dpll3

    This frequency deviation is shown in the DPLLx_FDEV control. To perform the shift, the increment or decrement button must be pressed. Figure 6-18. DPLL DCO Controls SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 38: Using The Validation Page

    When using SPI readback on the EVM, GPIO2 must be configured as STATUS or INT… and SDO output. When using the device in I C mode, refer to Section 3.3. Figure 6-20. GPIO Page LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 39 = 1 and GPIO_SYSREF_SEL to the appropriate OUT_x_y). The GPIOx replicated SYSREF output is a continuous frequency. Pulsed SYSREF mode is not supported for the GPIOx replica outputs. Figure 6-21. SYNC/SYSREF/1-PPS Page SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 40: Using The Outputs Page

    The black line between OUT2 to OUT3, OUT4 to OUT7, OUT8 to OUT13, and OUT14 to OUT15 signifies that all these outputs must source from the same VCO. Figure 6-22. Outputs Page LMK5C33216AEVM Evaluation Module SNAU295 – JULY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 41: Eeprom Page

    Figure 6-23. EEPROM Page A.10 Design Report Page The Design Report Page shows an overview of the current profile settings. Figure 6-24. Design Report Page SNAU295 – JULY 2024 LMK5C33216AEVM Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 42 STANDARD TERMS FOR EVALUATION MODULES Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms set forth herein.
  • Page 43 www.ti.com Regulatory Notices: 3.1 United States 3.1.1 Notice applicable to EVMs not FCC-Approved: FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit to determine whether to incorporate such items in a finished product and software developers to write software applications for use with the end product.
  • Page 44 www.ti.com Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à...
  • Page 45 www.ti.com EVM Use Restrictions and Warnings: 4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS. 4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling or using the EVM, including without limitation any warning or restriction notices.
  • Page 46 Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief in any United States or foreign court. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated...
  • Page 47: Important Notice

    TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2024, Texas Instruments Incorporated...

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