Texas Instruments TUSB564 Manual
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Texas Instruments TUSB564 Manual

Texas Instruments TUSB564 Manual

Usb type-c dp alt mode 8.1 gbps sink-side linear redriver crosspoint switch
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TUSB564 USB TYPE-C™ DP Alt Mode 8.1 Gbps
1 Features
•
USB Type-C
™
crosspoint switch supporting
– USB 3.1 Gen 1 + 2 DP 1.4 lanes
– 4 DP 1.4 lanes
•
USB 3.1 Gen 1 up to 5 Gbps
•
DisplayPort 1.4 up to 8.1 Gbps (HBR3)
•
VESA DisplayPort
™
alt mode UFP_D redriving
crosspoint switch supporting c, d, and e pin
assignments
•
Ultra-low-power architecture
•
Linear redriver with up to 12 dB equalization
•
Transparent to DisplayPort link training
•
Automatic LFPS de-emphasis control to meet USB
3.1 certification requirements
•
Configuration through GPIO or I
•
Hot-plug capable
•
Industrial temperature range: –40°C to 85°C
(TUSB564I)
•
Commercial temperature range: 0°C to 70°C
(TUSB564)
•
4 mm × 6 mm, 0.4 mm Pitch WQFN package
D+/-
TUSB564
TX1
RX1
RX2
TX2
SBU1
SBU2
CTL
1
CC1
PD Controller
CC2
Copyright © 2017, Texas Instruments Incorporated
Simplified Schematics
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Sink-Side Linear Redriver Crosspoint Switch
2
C
SSRX
USB Hub
SSTX
DP0
DP1
DP2
DP RX
DP3
AUXn
AUXp
HPDIN
0
FLIP
HPD
Control
SLLSF29G – OCTOBER 2017 – REVISED NOVEMBER 2022
2 Applications
•
Monitors
•
HDTV
•
Projectors
•
Docking stations
3 Description
The TUSB564 s a VESA USB Type-C
redriving switch supporting USB 3.1 data rates up
to 5 Gbps and DisplayPort 1.4 up to 8.1 Gbps for
upstream facing port (Sink). The device is used for
UFP_D pin assignments C, D, and E from the VESA
DisplayPort Alt Mode on USB Type-C Standard.
The TUSB564 provides several levels of receive
linear equalization to compensate for inter symbol
interference (ISI) due to cable and board trace
loss. Operates on a single 3.3-V supply and comes
in a commercial temperature range and industrial
temperature range.
Package Information
PART NUMBER
PACKAGE
TUSB564
RNQ (WQFN, 40)
TUSB564I
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
TUSB564
TUSB564 Use-Case Example
TUSB564
™
Alt Mode
(1)
BODY SIZE (NOM)
4.00 mm × 6.00 mm

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Summary of Contents for Texas Instruments TUSB564

  • Page 1 TUSB564 SLLSF29G – OCTOBER 2017 – REVISED NOVEMBER 2022 TUSB564 USB TYPE-C™ DP Alt Mode 8.1 Gbps Sink-Side Linear Redriver Crosspoint Switch 1 Features 2 Applications • USB Type-C ™ crosspoint switch supporting • Monitors • HDTV – USB 3.1 Gen 1 + 2 DP 1.4 lanes •...

  • Page 2: Revision History

    Updated AUX_SBU_OVR Description field in Table 8-15 to match Table 8-6 ..........28 Changes from Revision A (October 2017) to Revision B (January 2018) Page • Changed From: DP0EQ_SEL To: DP3EQ_SEL ....................Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TUSB564...
  • Page 3 • Added Note which describes AUX snoop feature is only supported in I2C mode. In GPIO mode, AUX snoop is disabled and all four lanes are enabled....................... Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...

  • Page 4: Pin Configuration And Functions

    Differential positive input for USB3.1 downstream facing port. SSTXn Diff I Differential negative input for USB3.1 downstream facing port. SSRXp Diff O Differential positive output for USB3.1 downstream facing port. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TUSB564...
  • Page 5 AUXp I/O, CMOS resistor to DP_PWR (3.3 V). This pin along with AUXN is used by the TUSB564 for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C. AUXn. DisplayPort AUX negative I/O connected to the DisplayPort sink through a AC coupling capacitor.

  • Page 6: Specifications

    Junction-to-board characterization parameter °C/W Junction-to-case (bottom) thermal resistance °C/W θJC(bot) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TUSB564...

  • Page 7: Electrical Characteristics

    Common-mode voltage bias in the RX-DC- receiver (DC) Present after a USB3.1 device is detected RX-DIFF- Differential input impedance (DC) Ω on TXP/TXN Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TUSB564...
  • Page 8 Differential Return Loss 2.5 GHz at 90 Ω DIFF-2.5G Common Mode Return Loss 50 MHz – 2.5 GHz at 90 Ω TX-CM AC Electrical Characteristics for USB and DP Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TUSB564...
  • Page 9 = 3.3 V; CTL1 = 1; V = 0 V or 3.3 V AUX_ON OFF-state capacitance = 3.3 V; CTL1 = 0; V = 0 V or 3.3 V AUX_OFF Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TUSB564...

  • Page 10: Switching Characteristics

    Rise time of both SDA and SCL signals 20 × Fall time of both SDA and SCL signals /5.5 Setup time for STOP condition 0.26 µs SUSTO Capacitive load for each bus line Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TUSB564...

  • Page 11: Timing Requirements

    Time when Vcc reaches 70% to device active Output Rise/Fall Time Output Rise/Fall time mismatch (20%-80% of differential voltage measured RF-MM 1.7 inch from the output pin) Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TUSB564...

  • Page 12: Typical Characteristics

    Differential Input Voltage (mV) Differential Input Voltage (mV) Figure 6-5. USB TX (DFP) Linearity Curves at 2.5 GHz Figure 6-6. USB RX (UFP) Linearity Curves at 2.5 GHz Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TUSB564...
  • Page 13 Figure 6-9. DisplayPort HBR3 Eye-Pattern Performance with 12- Figure 6-10. USB 3.1 Gen1 Eye-Pattern Performance with 12- inch Input PCB Trace at 8.1 Gbps inch Input PCB Trace at 5 Gbps Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TUSB564...

  • Page 14: Parameter Measurement Information

    Figure 7-1. I C Timing Diagram Definitions (min) CTL1 pin CTL0 pin Figure 7-2. USB3.1 to 4-Lane DisplayPort in GPIO Mode T DIFF_DLY T DIFF_DLY Figure 7-3. Propagation Delay Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TUSB564...
  • Page 15 Figure 7-5. Output Rise and Fall Times CTL1 V OUT T AUX_SW_ON T AUX_SW_OFF + T CTL1_DEBOUNCE Figure 7-6. AUX and SBU Switch ON and OFF Timing Diagram Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TUSB564...

  • Page 16: Detailed Description

    8 Detailed Description 8.1 Overview The TUSB564 is a VESA USB Type-C Alt Mode redriving switch supporting data rates up to 8.1 Gbps for upstream facing port. This device uses 5 generation USB redriver technology. The device is used for UFP pin assignments C and D from the VESA DisplayPort Alt Mode on USB Type-C Standard.

  • Page 17: Functional Block Diagram

    SSEQ_SEL DPEQ_SEL DPEQ[1:0]/A1 EQ[1:0] SSEQ[1:0]/A0 I2C_EN FSM, Control Logic and FLIP/SCL HPDIN Registers CTL0/SDA Target CTL1 SBU1 AUXn SBU2 AUXp VREG Copyright © 2017, Texas Instruments Incorporated Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TUSB564...

  • Page 18: Feature Description

    8.3.1 USB 3.1 The TUSB564 supports USB 3.1 Gen 1 datarates up to 5 Gbps. The TUSB564 supports all the USB defined power states (U0, U1, U2, and U3). Because the TUSB564 is a linear redriver, it can’t decode USB3.1 physical layer traffic.

  • Page 19: Device Functional Modes

    Type-C port or USB3.1 operation not required by attached device must take TUSB564 out of USB3.1 mode by transitioning the CTL0 pin from L to H and back to L. Table 8-2. GPIO Configuration Control...
  • Page 20 TX1p SSTXn TX1n TX2p DP0p TX2n DP0n RX2p DP1p RX2n DP1n RX2p SSRXp RX2n SSRXn SSTXp TX2p SSTXn TX2n TX1p DP0p TX1n DP0n RX1p DP1p RX1n DP1n Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TUSB564...
  • Page 21 Open 8.4.3 DisplayPort Mode The TUSB564 supports up to four DisplayPort lanes at datarates up to 8.1 Gbps. TUSB564 can be enabled for DisplayPort through GPIO control pin CTL1 or through I C register CTLSEL1. When I2C_EN is ‘0’, DisplayPort...
  • Page 22 SuperSpeed signaling rate to determine the state of the USB3.1 interface. Depending on the state of the USB 3.1 interface, the TUSB564 can be in one of four primary modes of operation when USB 3.1 is enabled (CTL0 = H or CTLSEL0 = 1b1): Disconnect, U2/U3, U1, and U0.
  • Page 23 CTL_DB VCC supply ramp requirement VCC_RAMP Following pins comprise CFG pins: I2C_EN, EQ[1:0], SSEQ[1:0], and DPEQ[1:0]. Recommend CFG pins are stable when V is at minimum value. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TUSB564...
  • Page 24 The following procedure should be followed to write to TUSB564 I C registers: 1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB564 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  • Page 25 The field may be cleared by a write of one. Write of zero to the field have no effect. Update Hardware may autonomously update this field. No Access Not accessible or not applicable Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TUSB564...

  • Page 26: Register Maps

    1’b0, this field reflects the sampled state of DPEQ[1:0] pins. DP3EQ_SEL R/W/U 0000 When EQ_OVERRIDE = 1’b1, software can change the EQ setting for DP lane 3 based on value written to this field. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TUSB564...
  • Page 27 Reserved This field represents the snooped value of the AUX write to DPCD address 0x00600. When AUX_SNOOP_DISABLE = 1’b0, the TUSB564 will enable/disable DP lanes based on the SET_POWER_STATE snooped value. When AUX_SNOOP_DISABLE = 1’b1, then DP lane enable/disable are determined by state of DPx_DISABLE registers, where x = 0, 1, 2, or 3.
  • Page 28 8.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000] Figure 8-7. USB3.1 Control/Status Registers (0x20) EQ2_SEL EQ1_SEL R/W/U R/W/U LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TUSB564...
  • Page 29 0000 sampled state of SSEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can change the EQ setting for USB3.1 SSTXP/N receiver based on value written to this field. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TUSB564...
  • Page 30 01 – Compliance Mode enabled in DFP direction (SSTX -> TX1/ TX2) USB3_COMPLIANCE_CTRL 10 – Compliance Mode enabled in UFP direction (RX1/RX2 -> SSRX) 11 – Compliance Mode Disabled. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TUSB564...

  • Page 31: Application And Implementation

    The TUSB564 is a linear redriver designed specifically to compensation for intersymbol interference (ISI) jitter caused by signal attenuation through a passive medium like PCB traces and cables. Because the TUSB564 has four independent DisplayPort 1.4 inputs, one upstream facing USB 3.1 Gen 1 input, and two downstream facing USB 3.1 Gen 1 inputs, it can be optimized to correct ISI on all those seven inputs through 16 different...
  • Page 32 (EQ[1:0], SSEQ[1:0], and DPEQ[1:0]) can be left unconnected. If these pins are left unconnected, the TUSB564 7-bit I2C target address will be 0x12 because both DPEQ/A1 and SSEQ0/A0 will be at pin level "F". If a different I2C target address is desired, DPEQ/A1 and SSEQ0/A0 pins should be set to a level which produces the desired I2C target address.
  • Page 33 I2C_EN 3.3V 3.3V SSEQ0/A0 SSEQ1 DPEQ0/A1 FLIP/SCL DPEQ1 3.3V 3.3V 3.3V 3.3V CTL0/SDA Type-C CTL1 Controller HPDIN Copyright © 2017, Texas Instruments Incorporated Figure 9-2. Application Circuit Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TUSB564...
  • Page 34 Moreover, the DisplayPort sink has to handle the lane swapping with the following lane-to-pin mapping as received by the TUSB564 device: Lane 0 → DP1, Lane 1 → DP0, Lane 2 → DP3, and Lane 3 → DP2.
  • Page 35 PD controller is capable of correcting the polarity inversion of the AUX signal and the TUSB564 is provided with the corrected polarity of the AUX signal through its AUXp/AUXn pins. If the TUSB564 device configuration is through the I C Mode, AUX snooping should be disabled by setting AUX_SNOOP_DISABLE register 0x13[7] = 1'b1.

  • Page 36: System Examples

    SLLSF29G – OCTOBER 2017 – REVISED NOVEMBER 2022 9.3 System Examples 9.3.1 USB 3.1 Only The TUSB564 is in USB3.1 only when the CTL1 pin is low and CTL0 pin is high. D+/- D+/- 1 Port USB USB Host...
  • Page 37 SLLSF29G – OCTOBER 2017 – REVISED NOVEMBER 2022 9.3.2 USB 3.1 and 2 Lanes of DisplayPort The TUSB564 operates in USB3.1 and 2 Lanes of DisplayPort mode when the CTL1 pin is high and CTL0 pin is high. 1 Port USB &...
  • Page 38 TUSB564 www.ti.com SLLSF29G – OCTOBER 2017 – REVISED NOVEMBER 2022 9.3.3 DisplayPort Only The TUSB564 operates in 4 Lanes of DisplayPort only mode when the CTL1 pin is high and CTL0 pin is low. D+/- D+/- 4 Lane DP USB Host...

  • Page 39: Power Supply Recommendations

    10 Power Supply Recommendations The TUSB564 is designed to operate with a 3.3-V power supply. Levels above those listed in the table should not be used. If using a higher voltage system power supply, a voltage regulator can be used to step down to 3.3 V.

  • Page 40: Layout Example

    If test points are used, they should be placed in series and symmetrically. They must not be placed in a manner that causes a stub on the differential pair. 11.2 Layout Example To USB Hub AC Coupling capacitors Figure 11-1. Layout Example Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TUSB564...

  • Page 41: Device And Documentation Support

    All trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 42 PACKAGE OPTION ADDENDUM www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking Ball material Peak reflow TUSB564IRNQR Active Production WQFN (RNQ) | 40 3000 | LARGE T&R NIPDAU Level-1-260C-UNLIM...
  • Page 43 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TUSB564 :...
  • Page 44 PACKAGE MATERIALS INFORMATION www.ti.com 5-Mar-2024 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS B0 W Reel Diameter Cavity Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE...
  • Page 45 PACKAGE MATERIALS INFORMATION www.ti.com 5-Mar-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) TUSB564IRNQR WQFN 3000 367.0 367.0 35.0 TUSB564IRNQT WQFN 210.0 185.0 35.0 TUSB564RNQR WQFN 3000 367.0...

  • Page 46: Package Outline

    PACKAGE OUTLINE RNQ0040A WQFN - 0.8 mm max height SCALE 2.500 PLASTIC QUAD FLATPACK - NO LEAD PIN 1 INDEX AREA 0.8 MAX SEATING PLANE 0.05 0.00 0.08 4.7±0.1 2X 4.4 (0.2) TYP EXPOSED 36X 0.4 THERMAL PAD 2.7±0.1 0.25 0.15 PIN 1 ID (OPTIONAL)
  • Page 47 NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4222125/B 01/2016 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com...
  • Page 48 EXAMPLE STENCIL DESIGN RNQ0040A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD SYMM 4X (1.5) 40X (0.6) 40X (0.2) (0.695) SYMM (3.8) (1.19) 36X (0.4) 0.05 ) TYP METAL 6X (1.3) (5.8) SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 73% PRINTED SOLDER COVERAGE BY AREA SCALE:18X...
  • Page 49 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated...

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