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Manuals and User Guides for NEC uPD76F0018. We have
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NEC uPD76F0018 manual available for free PDF download: Preliminary User's Manual
NEC uPD76F0018 Preliminary User's Manual (592 pages)
32-/16-bit Single-Chip Microcontroller with CAN and VAN Interfaces
Brand:
NEC
| Category:
Microcontrollers
| Size: 2 MB
Table of Contents
Regional Information
4
Table of Contents
7
Chapter 1 Introduction
21
General
21
Device Features
22
Application Fields
23
Ordering Information
23
Pin Configuration (Top View)
24
Figure 1-1: Pin Configuration of the Vanstorm Microcontroller
24
Configuration of Function Block
26
Block Diagram of Vanstorm
26
Figure 1-2: Block Diagram of the Vanstorm Microcontroller
26
On-Chip Units
27
Chapter 2 Pin Functions
29
List of Pin Functions
29
Description of Pin Functions
34
Types of Pin I/O Circuit and Connection of Unused Pin
48
Figure 2-1: Pin I/O Circuits
51
Chapter 3 CPU Function
53
Features
53
CPU Register Set
54
Figure 3-1: CPU Register Set
54
System Register Set
54
Program Register Set
55
Figure 3-2: Program Counter (PC)
55
Table 3-1: Program Registers
55
System Register Set
56
Figure 3-3: Interrupt Source Register (ECR)
56
Table 3-2: System Register Numbers
56
Figure 3-4: Program Status Word (PSW)
57
Operation Modes
58
Operation Mode Specification
58
Table 3-3: Register Initial Values by Operation Modes
58
Address Space
59
CPU Address Space
59
Figure 3-5: CPU Address Space
59
Image
60
Figure 3-6: Image on Address Space
60
Wrap-Around of CPU Address Space
61
Figure 3-7: Wrap-Around of Program Space
61
Figure 3-8: Wrap-Around of Data Space
61
Memory Map
62
Figure 3-9: Memory Map
62
Area
63
Table 3-4: Interrupt/Exception Table (Sheet 1 of 2)
64
Figure 3-10: Internal RAM Area
66
Figure 3-11: Internal Peripheral I/O Area
67
External Memory Expansion
69
Recommended Use of Address Space
70
Figure 3-12: Example Application of Wrap-Around
70
Figure 3-13: Recommended Memory Map
71
Peripheral I/O Registers
72
Table 3-5: List of Peripheral I/O Registers (Sheet 1 of 8)
72
Programmable Peripheral I/O Registers
80
Figure 3-14: Programmable Peripheral I/O Register (Outline)
80
Figure 3-15: Peripheral Area Selection Control Register (BPC)
81
Table 3-6: List of Programmable Peripheral I/O Registers for the FCAN (Sheet 1 of 25)
82
Table 3-7: List of Programmable Peripheral I/O Registers for the FVAN (Sheet 1 of 6)
107
Specific Registers
113
Command Register (PRCMD)
114
Peripheral Command Register (PHCMD)
115
Peripheral Status Register (PHS)
116
Internal Peripheral Function Wait Control Register VSWC
117
Chapter 4 Bus Control Function
119
Features
119
Bus Control Pins
120
Memory Block Function
121
Figure 4-1: Memory Block Function
121
Chip Select Control Function
122
Figure 4-2: Chip Area Select Control Registers 0, 1 (1/2)
122
Bus Cycle Type Control Function
124
Figure 4-3: Bus Cycle Type Configuration Registers 0, 1 (BCT0, BCT1)
124
Bus Access
125
Number of Access Clocks
125
Bus Sizing Function
125
Table 4-1: Number of Bus Access Clocks
125
Endian Control Function
126
Figure 4-4: Big Endian Addresses Within Word
127
Figure 4-5: Little Endian Addresses Within Word
127
Bus Width
128
Halfword Access (16 Bits)
130
Word Access (32 Bits)
132
Wait Function
140
Programmable Wait Function
140
External Wait Function
142
Relationship between Programmable Wait and External Wait
142
Figure 4-6: Example of Wait Insertion
142
Idle State Insertion Function
143
Bus Priority Order
144
Table 4-2: Bus Priority Order
144
Boundary Operation Conditions
145
Program Space
145
Data Space
145
Chapter 5 Memory Access Control Function
147
SRAM, External ROM, External I/O Interface
147
Features
147
SRAM Connections
148
Figure 5-1: Example of Connection to SRAM
148
SRAM, External ROM, External I/O Access
149
Figure 5-2: SRAM, External ROM, External I/O Access Timing (1/6)
149
Page ROM Controller (ROMC)
155
Features
155
Page ROM Connections
156
Figure 5-3: Example of Page ROM Connections
156
On-Page/Off
157
Figure 5-4: On-Page/Off-Page Judgment During Page ROM Connection (1/2)
157
Page ROM Configuration Register (PRC)
159
Figure 5-5: Page ROM Configuration Register (PRC)
159
Page ROM Access
160
Figure 5-6: Page ROM Access Timing (1/4)
160
Chapter 6 Interrupt/Exception Processing Function
165
Features
165
Table 6-1: Interrupt/Exception Source List (Sheet 1 of 3)
166
Non-Maskable Interrupts
169
Operation
170
Figure 6-1: Processing Configuration of Non-Maskable Interrupt
170
Figure 6-2: Acknowledging Non-Maskable Interrupt Request
171
Figure 6-3: Example of Non-Maskable Interrupt Request Acknowledgement Operation (1/2)
172
Restore
174
Figure 6-4: RETI Instruction Processing
174
Non-Maskable Interrupt Status Flag (NP)
175
Figure 6-5: Non-Maskable Interrupt Status Flag (NP)
175
Edge Detection Function
176
Figure 6-6: Voltage Comparator Mode Register (VCMPM)
176
Maskable Interrupts
177
Operation
177
Figure 6-7: Maskable Interrupt Processing
178
Restore
179
Figure 6-8: RETI Instruction Processing
179
Priorities of Maskable Interrupts
180
Figure 6-9: Example of Processing in Which Another Interrupt Request Is Issued
181
Figure 6-10: Example of Processing Interrupt Requests Simultaneously Generated
183
Interrupt Control Register (Picn)
184
Figure 6-11: Interrupt Control Register (Picn)
184
Table 6-2: Addresses and Bits of Interrupt Control Registers (Sheet 1 of 2)
185
Interrupt Mask Registers 0 to 3 (IMR0 to IMR3)
187
Figure 6-12: Interrupt Mask Registers 0 to 3 (IMR0 to IMR3)
187
In-Service Priority Register (ISPR)
188
Maskable Interrupt Status Flag (ID)
188
Figure 6-13: In-Service Priority Register (ISPR)
188
Figure 6-14: Maskable Interrupt Status Flag (ID)
188
Noise Elimination Circuit
189
Figure 6-15: Timer E Input Circuit Overview
189
Analog Filter
190
Digital Filter
190
Figure 6-16: Port Interrupt Input Circuit Overview
190
Interrupt Trigger Mode Selection
191
Figure 6-17: Digital Filter State Machine Diagram
191
Filter Edge Detect Mode Register (Fem0N to Fem5N) for Timer E Input Pins
192
Figure 6-18: Timer E Input Pin Filter Edge Detect Mode Registers (Fem0N to Fem5N) (N=0 to 2) (1/2)
192
Input Pins
194
Figure 6-19: INT0, INT1 and INT2 Input Pin Filter Edge Detect Mode Registers (FEM03 to FEM23)
194
Software Exception
195
Operation
195
Figure 6-20: Software Exception Processing
195
Restore
196
Figure 6-21: RETI Instruction Processing
196
Exception Status Flag (EP)
197
Figure 6-22: Exception Status Flag (EP)
197
Exception Trap
198
Illegal Opcode Definition
198
Figure 6-23: Exception Trap Processing
198
Figure 6-24: Restore Processing from Exception Trap
199
Debug Trap
200
Figure 6-25: Debug Trap Processing
200
Figure 6-26: Restore Processing from Debug Trap
201
Multiple Interrupt Processing Control
202
Interrupt Response Time
204
Figure 6-27: Pipeline Operation at Interrupt Request Acknowledgment (Outline)
204
Table 6-3: Interrupt Response Time
204
Periods in Which Interrupts Are Not Acknowledged
205
Chapter 7 Clock Generator
207
Features
207
Configuration
207
Figure 7-1: Block Diagram of the Clock Generator
207
Main System Clock Oscillator
208
Figure 7-2: Main System Clock Oscillator
208
Control Registers
209
Clock Control Register (CKC)
209
PLL Status Register (PSTAT)
210
Clock Select Pin
210
Table 7-1: PLL Mode / Direct Mode
210
Table 7-2: Relation System Clock to Resonator Frequency
211
Table 7-3: CESEL Setting
211
Power Saving Functions
212
General
212
Table 7-4: Power Saving Modes Overview
212
Figure 7-3: Power Save Mode State Transition Diagram
213
Table 7-5: Power Saving Mode Frequencies
214
Power Save Modes Outline
215
HALT Mode
216
Table 7-6: Operating States in HALT Mode
216
Table 7-7: Operation after HALT Mode Release by Interrupt Request
217
IDLE Mode
218
Table 7-8: Operating States in IDLE Mode
218
WATCH Mode
219
Table 7-9: Operating States in WATCH Mode
219
Table 7-10: Operation after WATCH Mode Release by Interrupt Request
220
Software STOP Mode
221
Table 7-11: Operating States in STOP Mode
221
Register Description
222
Power Save Control Register (PSC)
222
Power Save Mode Register (PSM)
224
Securing Oscillation Stabilization Time
225
Oscillation Stabilization Time Security Specification
225
Figure 7-4: WATCH Mode Release by NMI or INT
225
Figure 7-5: STOP Mode Release by NMI or INT
226
Figure 7-6: WATCH Mode Release by Reset or Watchdog Timer
227
Figure 7-7: STOP Mode Release by RESET Pin Input
227
Time Base Counter (TBC)
228
Table 7-12: Counting Time Examples
228
Chapter 8 Timer / Counter (Real-Time Pulse Unit)
229
Timer D
229
Features (Timer D)
229
Function Overview (Timer D)
229
Basic Configuration
230
Figure 8-1: Block Diagram of Timer D
230
Table 8-1: Timer D Configuration List
230
Figure 8-2: Timer D Registers 0, 1 (TMD0, TMD1)
231
Figure 8-3: Timer D Compare Registers 0, 1 (CMD0 to CMD1)
232
Figure 8-4: Example of Timing During TMD Operation
233
Control Register
234
Figure 8-5: Timer D Control Register 0, 1 (TMCD0 to TMCD1)
234
Operation
235
Figure 8-6: TMD Compare Operation Example (1/2)
235
Application Example
236
Precautions
237
Timer E
238
Features (Timer E)
238
Function Overview (Timer E)
238
Basic Configuration
240
Table 8-2: Timer E Configuration List
240
Figure 8-7: Block Diagram of Timer E
241
Table 8-3: Meaning of Signals in Block Diagram
242
Figure 8-8: Timer E Time Base Counter 0 Registers 0 to 2 (TBASE00 to TBASE02)
243
Figure 8-9: Timer E Time Base Counter 1 Registers 0 to 2 (TBASE10 to TBASE12)
243
Figure 8-10: Timer E Sub-Channel 0 Capture/Compare Registers 0 to 2 (CVSE00 to 02)
244
Figure 8-11: Timer E Sub-Channel X Main Capture/Compare Registers 0 to 2 (Cvpex0 to Cvpex2) (X = 1 to 4)
245
Figure 8-12: Timer E Sub-Channel X Sub Capture/Compare Registers 0 to 2 (Cvsex0 to Cvsex2) (X = 1 to 4)
246
Figure 8-13: Timer E Sub-Channel 5 Capture/Compare Registers (CVSE50 to CVSE52)
247
Control Registers
248
Figure 8-14: Timer E Clock Stop Registers 0 to 2 (STOPTE0 to STOPTE2)
248
Figure 8-15: Timer E Count Clock/Control Edge Selection Registers 0 to 2 (CSE0 to CSE2)
249
Figure 8-16: Timer E Sub-Channel Input Event Edge Selection Register 0 to 2 (SESE0 to SESE2)
250
Figure 8-17: Timer E Time Base Control Registers 0 to 2 (TCRE0 to TCRE2) (1/2)
251
Figure 8-18: Timer E Output Control Registers 0 to 2 (OCTLE0 to OCTLE2)
253
Figure 8-19: Timer E Sub-Channel 0, 5 Capture/Compare Control Registers 0 to 2 (CMSE050 to CMSE052)
254
Figure 8-20: Timer E Sub-Channel 1, 2 Capture/Compare Control Registers 0 to 2 (CMSE120 to CMSE122) (1/2)
255
Figure 8-21: Timer E Sub-Channel 3, 4 Capture/Compare Control Registers 0 to 2 (CMSE340 to CMSE342) (1/2)
257
Figure 8-22: Timer E Time Base Status Register (TBSTATE0 to TBSTATE2)
259
Figure 8-23: Timer E Capture/Compare Status Registers 0 to 2 (CCSTATE0 to CCSTATE2)
260
Figure 8-24: Timer E Output Delay Registers 0 to 2 (ODELE0 to ODELE2)
261
Figure 8-25: Timer E Software Event Capture Registers 0 to 2 (CSCE0 to CSCE2)
262
Operation
263
Figure 8-26: Edge Detection Timing
263
Figure 8-27: Timer E up Count Timing
264
Figure 8-28: External Control Timing of Timer E
265
Figure 8-29: Operation in Timer E Up/Down Count Mode
266
Figure 8-30: Timer E Timing in 32-Bit Cascade Operation Mode
267
Figure 8-31: Block Diagram of Timer E Multiplex Count Generation Circuit
268
Figure 8-32: Timer E Multiplex Count Timing
269
Figure 8-33: Timer E Capture Operation: 16-Bit Buffer-Less Mode
270
Figure 8-34: Timer E Capture Operation: Mode with 16-Bit Buffer
271
Figure 8-35: Timer E Capture Operation: 32-Bit Cascade Operation Mode
272
Figure 8-36: Timer E Capture Operation: Capture Control by Software and Trigger Timing
273
Figure 8-37: Timer E Compare Operation: Buffer-Less Mode
274
Figure 8-38: Timer E Compare Operation: Mode with Buffer
275
Figure 8-39: Timer E Capture Operation: Count Value Read Timing
276
Figure 8-40: Timer E Compare Operation: Timing of Compare Match and Write Operation to Register
277
Figure 8-41: Timer E Signal Output Operation: Toggle Mode 0 and Toggle Mode 1
278
Figure 8-42: Timer E Signal Output Operation: Toggle Mode 2 and Toggle Mode 3
279
Figure 8-43: Timer E Signal Output Operation: During Software Control
280
Figure 8-44: Timer E Signal Output Operation: During Delay Output Operation
280
Chapter 9 Watch Timer
281
Function
281
Figure 9-1: Block Diagram of Watch Timer
281
Configuration
282
Table 9-1: Interval Time of Interval Timer (F SUB = 4 Mhz)
282
Table 9-2: Configuration of Watch Timer
282
Watch Timer Control Register
283
Figure 9-2: Watch Timer Mode Control Register (WTM)
284
Operations
285
Operation as Watch Timer
285
Operation as Interval Timer
285
Table 9-3: Interval Time of Interval Timer
285
Figure 9-3: Operation Timing of Watch Timer/Interval Timer
286
Chapter 10 Watchdog Timer
287
Features
287
Watchdog Timer Mode
287
Figure 10-1: Block Diagram of Watchdog Timer Unit
287
Table 10-1: Runaway Detection Time by Watchdog Timer
287
Control Register
288
Watchdog Timer Mode Register (WDTM)
288
Figure 10-2: Watchdog Timer Mode Register (WDTM)
288
Operation
289
Operating as Watchdog Timer
289
Table 10-2: Runaway Detection Time by Watchdog Timer
289
Chapter 11 Serial Interface Function
291
Features
291
Asynchronous Serial Interfaces 0, 1 (UART0, UART1)
292
Features
292
Configuration
293
Figure 11-1: Asynchronous Serial Interfaces 0, 1 Block Diagram
294
Control Registers
295
Figure 11-2: Asynchronous Serial Interface Mode Registers 0, 1 (ASIM0, ASIM1) (1/3)
295
Figure 11-3: Asynchronous Serial Interface Status Registers 0, 1 (ASIS0, ASIS1)
298
Figure 11-4: Asynchronous Serial Interface Transmit Status Registers 0, 1 (ASIF0, ASIF1)
299
Figure 11-5: Reception Buffer Registers 0, 1 (RXB0, RXB1)
300
Figure 11-6: Transmission Buffer Registers 0, 1 (TXB0, TXB1)
301
Interrupt Requests
302
Table 11-1: Generated Interrupts and Default Priorities
302
Operation
303
Figure 11-7: Asynchronous Serial Interface Transmit/Receive Data Format
303
Figure 11-8: Asynchronous Serial Interface Transmission Completion Interrupt Timing
304
Table 11-2: Transmission Status and Whether or Not Writing Is Enabled
305
Figure 11-9: Continuous Transmission Starting Procedure
306
Figure 11-10: Continuous Transmission End Procedure
307
Figure 11-11: Asynchronous Serial Interface Reception Completion Interrupt Timing
308
Figure 11-12: When Reception Error Interrupt Is Separated from Intsrn Interrupt (ISRM Bit = 0)
309
Figure 11-13: When Reception Error Interrupt Is Included in Intsrn Interrupt (ISRM Bit = 1)
309
Table 11-3: Reception Error Causes
309
Figure 11-14: Noise Filter Circuit
311
Figure 11-15: Timing of Rxdn Signal Judged as Noise
311
Dedicated Baud Rate Generators (BRG) of Uartm (M = 0, 1)
312
Figure 11-16: Baud Rate Generator (BRG) Configuration of Uartm (M = 0, 1)
312
Figure 11-17: Clock Select Registers 0, 1 (CKSR0 to CKSR1)
313
Figure 11-18: Baud Rate Generator Control Registers 0, 1 (BRGC0, BRGC1)
314
Table 11-4: Baud Rate Generator Setting Data
316
Figure 11-19: Allowable Baud Rate Range During Reception
317
Table 11-5: Maximum and Minimum Allowable Baud Rate Error
318
Precautions
319
Figure 11-20: Transfer Rate During Continuous Transmission
319
Clocked Serial Interfaces 0, 1 (CSI0, CSI1)
320
Features
320
Configuration
321
Figure 11-21: Block Diagram of Clocked Serial Interfaces
322
Control Registers
323
Figure 11-22: Clocked Serial Interface Mode Registers 0, 1 (CSIM0, CSIM1)
323
Figure 11-23: Clocked Serial Interface Clock Selection Registers 0, 1 (CSIC0, CSIC1)
324
Figure 11-24: Clocked Serial Interface Reception Buffer Registers 0, 1 (SIRB0, SIRB1)
325
Figure 11-25: Clocked Serial Interface Reception Buffer Registers L0, L1 (SIRBL0, SIRBL1)
326
Figure 11-26: Clocked Serial Interface Read-Only Reception Buffer Registers 0, 1 (SIRBE0, SIRBE1)
327
Figure 11-27: Clocked Serial Interface Read-Only Reception Buffer Registers L0, L1(SIRBEL0, SIRBEL1)
328
Figure 11-28: Clocked Serial Interface Transmission Buffer Registers 0, 1 (SOTB0, SOTB1)
329
Figure 11-29: Clocked Serial Interface Transmission Buffer Registers L0, L1 (SOTBL0, SOTBL1)
330
Figure 11-30: Clocked Serial Interface Initial Transmission Buffer Registers 0, 1 (SOTBF0, SOTBF1)
331
Figure 11-31: Clocked Serial Interface Initial Transmission Buffer Registers L0, L1 (SOTBFL0, SOTBFL1)
332
Figure 11-32: Serial I/O Shift Registers 0, 1 (SIO0, SIO1)
333
Figure 11-33: Serial I/O Shift Registers L0, L1 (SIOL0, SIOL1)
334
Operation
335
Figure 11-34: Timing Chart in Single Transfer Mode (1/2)
335
Figure 11-35: Timing Chart According to Clock Phase Selection (1/2)
337
Figure 11-36: Timing Chart of Interrupt Request Signal Output in Delay Mode (1/2)
339
Figure 11-37: Repeat Transfer (Receive-Only) Timing Chart
341
Figure 11-38: Repeat Transfer (Transmission/Reception) Timing Chart
342
Figure 11-39: Timing Chart of Next Transfer Reservation Period
343
Figure 11-40: Transfer Request Clear and Register Access Contention
344
Figure 11-41: Interrupt Request and Register Access Contention
345
Output Pins
346
Dedicated Baud Rate Generators 0, 1 (BRG0, BRG1)
347
Figure 11-42: Baud Rate Generators 0, 1 (BRG0, BRG1) Block Diagram
347
Figure 11-43: Prescaler Mode Registers 0, 1 (PRSM0, PRSM1)
348
Figure 11-44: Prescaler Compare Registers 0, 1 (PRSCM0, PRSCM1)
349
Table 11-6: Baud Rate Generator Setting Data
350
Chapter 12 FCAN Interface Function
351
Features
351
Outline of the FCAN System
352
General
352
Figure 12-1: Functional Blocks of the FCAN Interface
352
CAN Memory and Register Layout
353
Figure 12-2: Memory Area of the FCAN System
353
Table 12-1: Configuration of the CAN Message Buffer Section
354
Table 12-2: CAN Message Buffer Registers Layout
355
Table 12-3: Relative Addresses of CAN Interrupt Pending Registers
356
Table 12-4: Relative Addresses of CAN Common Registers
357
Table 12-5: Relative Addresses of CAN Module 1 Registers
358
Clock Structure
359
Figure 12-3: Clock Structure of the FCAN System
359
Interrupt Handling
360
Figure 12-4: FCAN Interrupt Bundling of V850E/ Vanstorm
360
Time Stamp
361
Figure 12-5: Time Stamp Capturing at Message Reception
361
Figure 12-6: Time Stamp Capturing at Message Transmission
362
Table 12-6: Transmitted Data on the CAN Bus (ATS = 1)
362
Message Handling
363
Table 12-7: Example for Automatic Transmission Priority Detection
364
Table 12-8: Example for Transmit Buffer Allocation When more than 5 Buffers Linked to a CAN Module
365
Table 12-9: Storage Priority for Reception of Data Frames
366
Table 12-10: Storage Priority for Reception of Remote Frames
366
Table 12-11: Inner Storage Priority Within a Priority Class
367
Mask Handling
368
Remote Frame Handling
369
Table 12-12: Remote Frame Handling Upon Reception into a Transmit Message Buffer
371
Control and Data Registers
372
Bit Set/Clear Function
372
Figure 12-7: 16-Bit Data Write Operation for Specific Registers
373
Common Registers
374
Figure 12-8: CAN Stop Register (CSTOP)
374
Figure 12-9: CAN Main Clock Select Register (CGSC) (1/2)
375
Figure 12-10: Configuration of FCAN System Main Clock
376
Figure 12-11: Configuration of FCAN Global Time System Clock
376
Figure 12-12: CAN Global Status Register (CGST) (1/2)
377
Figure 12-13: CAN Global Interrupt Enable Register (CGIE)
379
Figure 12-14: CAN Global Time System Counter (CGTSC)
380
Figure 12-15: CAN Message Search Start Register (CGMSS)
381
Figure 12-16: CAN Message Search Start Register (CGMSS)
382
CAN Interrupt Pending Registers
383
Figure 12-17: CAN Interrupt Pending Register (CCINTP)
383
Figure 12-18: CAN Global Interrupt Pending Register (CGINTP) (1/2)
384
Figure 12-19: CAN 1 Interrupt Pending Register (C1INTP) (1/2)
386
CAN Message Buffer Registers
388
Figure 12-20: Message Identifier Registers L00 to L63 and H00 to H63
388
Figure 12-21: Message Configuration Registers 00 to 63 (M_CONF00 to M_CONF63)
389
Figure 12-22: Message Status Registers 00 to 63 (M_STAT00 to M_STAT63)
390
Table 12-13: CAN Message Processing by TRQ and RDY Bits
391
Figure 12-23: Message Set/Clear Status Registers 00 to 63 (SC_STAT00 to SC_STAT63)
392
Figure 12-24: Message Data Registers M0 to M7 (M_Datam0 to M_Datam7)
393
Figure 12-25: Message Data Length Code Registers 00 to 63 (M_DLC00 to M_DLC63)
395
Figure 12-26: Message Control Registers 00 to 63 (M_CTRL00 to M_CTRL63) (1/2)
396
Figure 12-27: Message Time Stamp Registers 00 to 63 (M_TIME00 to M_TIME63)
398
CAN Module Registers
399
Figure 12-28: CAN 1 Mask 0 to 3 Registers L, H (C1MASKL0 to C1MASKL3, C1MASKH0 to C1MASKH3)
399
Table 12-14: Address Offsets of the CAN 1 Mask Registers
400
Figure 12-29: CAN 1 Control Register (C1CTRL) (1/4)
401
Figure 12-30: CAN 1 Definition Register (C1DEF) (1/3)
405
Figure 12-31: CAN 1 Information Register (C1LAST)
408
Figure 12-32: CAN 1 Error Counter Register (C1ERC)
409
Figure 12-33: CAN 1 Interrupt Enable Register (C1IE) (1/3)
410
Figure 12-34: CAN 1 Bus Activity Register (C1BA) (1/2)
413
Figure 12-35: CAN 1 Bit Rate Prescaler Register (C1BRP) (1/2)
415
Figure 12-36: CAN Bus Bit Timing
417
Figure 12-37: CAN 1 Synchronization Control Register (C1SYNC) (1/2)
418
Figure 12-38: CAN 1 Bus Diagnostic Information Register (C1DINF)
420
Operating Considerations
421
Rules to be Observed for Correct Baudrate Settings
421
Example for Baudrate Setting of CAN Module
422
Ensuring Data Consistency
424
Figure 12-39: Sequential CAN Data Read by CPU
424
Operating States of the CAN Module
426
Figure 12-40: State Transition Diagram for the CAN Module
426
Initialization Routines
427
Figure 12-41: General Initialization Sequence for the CAN Interface
427
Figure 12-42: Initialization Sequence for the CAN Module
429
Figure 12-43: Setting CAN Module into Initialization State
431
Chapter 13 Full VAN (FVAN)
433
Description of Full VAN
433
Introduction
433
Features
434
Block Diagram
435
Figure 13-1: Block Diagram
435
Operation of FVAN
436
Interrupt
436
Reset
436
Oscillator
437
Table 13-1: Division Rate Versus Network Frequency
437
Table 13-2: CD [2:0] and DIV5 Values
437
VAN Protocol
438
Line Interface
438
Figure 13-2: CSMA/CD Arbitration
438
VAN Frame
439
Figure 13-3: Van Frame
439
Figure 13-4: Unacknowledged Data Transfer
440
Figure 13-5: Acknowledge Data Transferred
440
Figure 13-6: Reply Request Message with Immediate Response Frame with Acknowledges
441
Figure 13-7: Request Reply Answer Without in Frame Response with Acknowledgment
442
Figure 13-8: Deferred Response Frame
442
Diagnosis System
444
Figure 13-9: Diagnosis States
445
Table 13-3: Status Bits: Sa & Sb
446
Generation of Internal Signals
448
Programming Modes
448
Table 13-4: Programming Modes
448
Registers Description
449
Memory Map
449
Table 13-5: Register Mapping of FVAN0 and FVAN1
449
Table 13-6: Memory Map FVAN Macro
450
Control and Status Registers
451
Table 13-7: Retries
452
Table 13-8: System Diagnosis Clock Divider
454
Table 13-9: Diagnosis System Command Bits
454
Table 13-10: Diagnosis System Status Bits
457
Figure 13-10: ACKE Status Bit
461
Figure 13-11: FV Status Bit
462
Figure 13-12: Exceeded Retry with MR[3..0] = 3
463
Figure 13-13: Update of the Status Register
466
Channel Registers
467
Table 13-11: Channel Register Sets Map for FVAN0
467
Table 13-12: Channel Register Sets Map for FVAN1
467
Table 13-13: Channel Register Set Structure
467
Figure 13-14: Message Buffer Structure for Transmission
472
Figure 13-15: Message Buffer Structure for Reception
473
Figure 13-16: Message Status Updating
474
Functional Description
476
Messages Types
476
Table 13-14: Transmit Message
476
Table 13-15: Receive Message
476
Table 13-16: Reply Request Message
476
Table 13-17: Reply Request Message Without Transmission
477
Table 13-18: Immediate Reply Message
477
Table 13-19: Deferred Reply Message
477
Table 13-20: Reply Request Detection Message
477
Priority Among the Different Channels
478
Table 13-21: Inactive Message
478
Retries, Rearbitrate and Abort
479
Figure 13-17: Transmit Function
479
Figure 13-18: Rearbitrate Example
481
Figure 13-19: Idle and Rearbitrate Example
482
Figure 13-20: Disable Channel after Rearbitrate Example
483
Figure 13-21: Abort Example
484
Activate, Idle and Sleep Modes
485
Figure 13-22: Idle and Activate Timings
485
Linked Channels
487
Figure 13-23: Link Mechanism
487
Chapter 14 A/D Converter
489
Features
489
Configuration
490
Figure 14-1: Block Diagram of A/D Converter
492
Control Registers
493
A/D Scan Mode Register 0 (ADSCM0) (1/2)
493
Figure 14-3: A/D Scan Mode Register 1 (ADSCM1)
495
Figure 14-4: A/D Voltage Detection Mode Register (ADETM)
498
A/D Conversion Result Registers 0 to 11 (ADCR0 to ADCR11)
499
Table 14-1: Correspondence between Adcrm (M = 0 to 11) Register Names and Addresses
499
Figure 14-6: Relationship between Analog Input Voltages and A/D Conversion Results
500
Table 14-2: Correspondence between each Analog Input Pin and Adcrm Registers
500
Interrupt Requests
501
A/D Converter Operation
502
A/D Converter Basic Operation
502
Operation Modes and Trigger Modes
503
Figure 14-7: Example of Select Mode Operation Timing (ANI1)
504
Figure 14-8: Example of Scan Mode Operation Timing (4-Channel Scan (ANI0 to ANI3))
505
Operation in A/D Trigger Mode
506
Operation in Select Mode
506
Figure 14-9: Example of Select Mode (A/D Trigger Select) Operation (ANI2)
506
Operation in Scan Mode
507
Figure 14-10: Example of Scan Mode (A/D Trigger Scan) Operation (ANI2-ANI5)
507
Operation in A/D Trigger Polling Mode
508
Operation in Select Mode
508
Figure 14-11: Example of Select Mode (A/D Trigger Polling Select) Operation (ANI2)
508
Operation in Scan Mode
509
Figure 14-12: Example of Scan Mode (A/D Trigger Polling Scan) Operation (ANI2 to ANI5)
509
Operation in Timer Trigger Mode
510
Operation in Select Mode
510
Figure 14-13: Example of Timer Trigger Select Mode Operation (ANI4)
510
Operation in Scan Mode
511
Figure 14-14: Example of Timer Trigger Scan Mode Operation (ANI1 to ANI4)
512
Precautions
513
Stopping Conversion Operation
513
Trigger Input During Conversion Operation
513
Timer Trigger Interval
513
Operation in Standby Modes
513
Chapter 15 Port Functions
515
Features
515
Port Configuration
516
Figure 15-2: Type a Block Diagram
520
Figure 15-3: Type B Block Diagram
521
Figure 15-4: Type C Block Diagram
522
Figure 15-5: Type D Block Diagram
523
Figure 15-6: Type E Block Diagram
524
Figure 15-7: Type F Block Diagram
525
Figure 15-8: Type G Block Diagram
526
Figure 15-9: Type H Block Diagram
527
Pin Functions of each Port
528
Port 1
528
Figure 15-10: Port 1 (P1)
528
Figure 15-11: Port 1 Mode Register (PM1)
528
Figure 15-12: Port 1 Mode Control Register (PMC1)
529
Port 2
530
Figure 15-13: Port 2 (P2)
530
Figure 15-14: Port 2 Mode Register (PM2)
530
Figure 15-15: Port 2 Mode Control Register (PMC2)
531
Port 3
532
Figure 15-16: Port 3 (P3)
532
Figure 15-17: Port 3 Mode Register (PM3)
532
Figure 15-18: Port 3 Mode Control Register (PMC3)
533
Port 4
534
Figure 15-19: Port 4 (P4)
534
Figure 15-20: Port 4 Mode Register (PM4)
534
Figure 15-21: Port 4 Mode Control Register (PMC4)
535
Port 5
536
Figure 15-22: Port 5 (P5)
536
Figure 15-23: Port 5 Mode Register (PM5)
536
Figure 15-24: Port 5 Mode Control Register (PMC5)
537
Port 6
538
Figure 15-25: Port 6 (P6)
538
Figure 15-26: Port 6 Mode Register (PM6)
538
Figure 15-27: Port 6 Mode Control Register (PMC6)
539
Port al
540
Figure 15-28: Port al (PAL)
540
Figure 15-29: Port al Mode Register (PMAL)
540
Figure 15-30: Port al Mode Control Register (PMCAL)
541
Port AH
542
Figure 15-31: Port AH (PAH)
542
Figure 15-32: Port AH Mode Register (PMAH)
542
Figure 15-33: Port AH Mode Control Register (PMCAH)
543
Port DL
544
Figure 15-34: Port DL (PDL)
544
Figure 15-35: Port DL Mode Register (PMDL)
544
Figure 15-36: Port DL Mode Control Register (PMCDL)
545
Port CS
546
Figure 15-37: Port CS (PCS)
546
Figure 15-38: Port CS Mode Register (PMCS)
546
Figure 15-39: Port CS Mode Control Register (PMCCS)
547
Port CT
548
Figure 15-40: Port CT (PCT)
548
Figure 15-41: Port CT Mode Register (PMCT)
548
Figure 15-42: Port CT Mode Control Register (PMCCT)
549
Port CM
550
Figure 15-43: Port CM (PCM)
550
Figure 15-44: Port CM Mode Register (PMCM)
550
Figure 15-45: Port CM Mode Control Register (PMCCM)
551
Chapter 16 Reset Function
553
Features
553
Pin Functions
553
Table 16-1: Operation Status of each Pin During Reset Period
553
Figure 16-1: Reset Signal Acknowledgment
554
Figure 16-2: Reset at Power-On
554
Initialization
555
Table 16-2: Initial Values of CPU and Internal RAM after Reset
555
Chapter 17 Voltage Regulator
557
Outline
557
Operation
557
Figure 17-1: Regulator
557
Chapter 18 Internal Voltage Comparator
559
Features
559
Figure 18-1: Block Diagram of Voltage Comparator
559
Voltage Comparator Functions
560
Table 18-1: Power Supply Voltage Operating Modes
560
Figure 18-2: Internal Voltage Comparator
561
Internal Voltage Comparator Control Register (VCMPM)
562
Chapter 19 Flash Memory
563
Features
563
Writing by Flash Writer
564
Programming Environment
564
Figure 19-1: Programming Environment in Conjunction with External Flash Writer
564
Communication System
565
Figure 19-2: Flash Writer Communication Via CSI0
565
Flash Programming Circuitry
566
Figure 19-3: Application Example for Flash Selfprogramming
566
Pin Handling
567
Vpp0 /V
567
Pp0 Pp1
567
PP1 Pins
567
Figure 19-4: Pin Handling of V
567
Serial Interface Pins
568
Figure 19-5: Conflict between Flash Writer and Other Output Pin
568
Figure 19-6: Malfunction of Other Input Pins
569
RESET Pin
570
NMI Pin
570
MODE Pin
570
Port Pins
570
Other Signal Pins
570
Power Supply
570
Figure 19-7: Conflict between Flash Writer Reset Line and Reset Signal Generation Circuit
570
Programming Method
571
Flash Memory Control
571
Selection of Communication Mode
571
Figure 19-8: Flow Chart of Flash Memory Manipulation
571
Table 19-1: List of Communication Systems
571
Selfprogramming Mode
572
Figure 19-9: Configuration in Selfprogramming Mode
572
Secure Selfprogramming
573
General Description
573
Signature Structure
573
Secure Selfprogramming Flow
573
Figure 19-10: Secure Selfprogramming Flow (1/2)
574
Advantages of Secure Selfprogramming
575
Appendix A Instruction Set List
577
Instruction Set (in Alphabetical Order)
580
Appendix B Index
585
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