VIPER RedBoot and AEL Quickstart
Parameter
hsync and
vsync
outputen
pixclockpol Configures the polarity of the pixel clock signal.
The required values for all of the above parameters are generally defined in the
datasheet for a given LCD panel. Often the timing parameters (pixel clock, margins,
sync pulse lengths) can be derived from values in the datasheet along with a certain
amount of trial and error. It is recommended that you read chapter 7 of the PXA255
Processor Developers manual since many of the parameters given to the driver
correspond directly to settings in the LCD controller hardware.
The default parameters are set to support a TFT type panel, so it is therefore possible
to support another TFT panel by passing only the mode and timings parameters. For
example, to support a 640 x 480 panel such as the NL6448AC20 you would use the
following command:
# modprobe pxafb options=mode:640x480-
16,pixclock:39722,left:16,right:81,upper:12,lower:31,hsynclen:63,vsynclen:2
The options string must be a single line with no spaces or line-breaks.
There is much greater variation between STN type panels, so it is necessary to pass all
parameters. For example, to support a Kyocera KCS057QV1AA-G00 320x240 single
panel color STN display you would use the following command:
# modprobe pxafb options=mode:320x240-
8,pixclock:154000,left:1,right:1,upper:0,lower:0,hsynclen:8,vsynclen:32,passive,c
olor,single,outputen:1,pixclockpol:0,hsync:1,vsync:1
The options string must be a single line with no spaces or line-breaks.
© 2005 Arcom
Issue D
Description
Configures the polarity of the horizontal and
vertical sync pulses. A value of 0 indicates an
active low sync pulse, while 1 indicates active
high. These parameters correspond to the
LCCR3[HSP] and LCCR3[VSP] registers.
Configures the polarity of the output enable
signal. A value of 0 indicates an active low
signal while 1 indicates active high. This
parameter corresponds to the LCCR3[OEP]
register.
A value of 0 indicates a falling edge while 1
indicates rising edge. This parameter
corresponds to the LCCR3[PCP] register.
Arcom Embedded Linux (AEL)
Default
hsync:0,vsync:0
outputen:1
pixclockpol:0
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