Asus AAEON EPIC-TGH7-PUC User Manual
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Asus AAEON EPIC-TGH7-PUC User Manual

Asus AAEON EPIC-TGH7-PUC User Manual

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EPIC-TGH7-PUC
EPIC System
nd
User's Manual 2
Ed
Last Updated: September 28, 2023

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Summary of Contents for Asus AAEON EPIC-TGH7-PUC

  • Page 1 EPIC-TGH7-PUC EPIC System User’s Manual 2 Last Updated: September 28, 2023...

  • Page 2: Copyright Notice

    Copyright Notice This document is copyrighted, 2023. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of the original manufacturer.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp. ⚫ Intel® and Xeon® are registered trademarks of Intel Corporation ⚫ Intel® Core™ is a trademark of Intel Corporation ⚫...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity EPIC-TGH7-PUC ⚫ Screw, Thermal Pads and Accessories Kit ⚫ SATA Cable ⚫ Dual SATA Power Cable ⚫ If any of these items are missing or damaged, please contact your distributor or sales representative immediately.
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page on AAEON.com for the latest version of this document.
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON System QO4-381 Rev.A0 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 × ○ ○ ○ ○ ○ 及其电子组件 外部信号 × ○ ○ ○ ○ ○ 连接器及线材 外壳 ○...
  • Page 10 China RoHS Requirement (EN) Hazardous and Toxic Materials List AAEON System QO4-381 Rev.A0 Hazardous or Toxic Materials or Elements Component Name PCB and Components Wires & Connectors for Ext.Connections Chassis CPU & RAM HDD Drive LCD Module Optical Drive Touch Control Module Battery This form is prepared in compliance with the provisions of SJ/T 11364.

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Block Diagram ......................6 Chapter 2 – Hardware Information ..................7 Dimensions ....................... 8 Jumpers and Connectors ..................10 List of Jumpers ......................11 2.3.1 Auto Power Button Enable/Disable Selection (JP5) ......11 2.3.2 Clear CMOS Jumper (JP6) ..............
  • Page 12 2.4.17 Nano SIM Card Socket (CN39) ............26 2.4.18 Half Size Mini Card Slot (CN41) ............27 2.4.19 M.2 3052 B-Key Slot (CN42) ............... 29 2.4.20 M.2 2280 M-Key Slot (CN43) .............. 29 2.4.20 SPI Flash Programming Port (CN44) ..........32 2.4.21 COM Port 1/2 (CN45) ................
  • Page 13 3.4.10.6 Device #* Detecting Configuration – Super I/O ....63 3.4.10.7 Device #* Detecting Configuration – MMIO ...... 65 Setup Submenu: System I/O ................67 3.5.1 PCI Express Configuration ..............68 3.5.2 Storage Configuration ................69 3.5.3 HD Audio Configuration ..............70 3.5.4 Digital IO Port Configuration ...............
  • Page 14 Appendix B – Mating Connectors ..................99 List of Mating Connectors and Cables ............100 Appendix C – Assembly Guide.....................101 Introduction ......................102 DDR4 Module Installation (CN17/DDR4 SODIMM 0) ........102 DDR4 Module Installation (CN40/DDR4 SODIMM 1) ........105 M.2 3052 B-Key Installation ................108 M.2 2280 M-Key Installation ................

  • Page 15: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 16: Specifications

    Specifications System Form Factor EPIC System 11th Generation Intel® Xeon/Core™ Processor: Intel® Core™ i7-11850HE (8C/16T, 2.60 GHz, 45W) Intel® Xeon® W-11865MRE (8C/16T, 2.60 GHz, 45W) Chipset Intel® 500 Series Mobile Chipsets (RM590E/HM570E) Memory Type DDR4 3200, Dual-Channel SODIMM x 2, Max 64GB (ECC supported by Intel®...
  • Page 17 Display Controller Intel® UHD Graphics for 11th Gen Intel® Processors LVDS/eDP — Display Interface VGA x 1, up to 1920 x 1080 DP++ 1.2 x 2, up to 3840 x 2160 @60Hz HDMI 2.0 x 1, up to 3840 x 2160 @60Hz Multiple Display Up to 4 Simultaneous Displays Audio...
  • Page 18 Internal I/O — Serial Port — Video — SATA SATA 6Gb/s x 2 +5V SATA Power Connector x 1 (Total up to 5V @2A, up to 5V @1A, shared with 2.5” SSD x 2 as limitation with 170X000592) Audio — DIO/GPIO GPIO 16-bit SMBus/I2C...
  • Page 19 Environmental Operating Temperature 32°F ~ 122°F (0°C ~ 50°C) with 0.5m/sec air flow Storage Temperature -40°F ~ 176°F (-40°C ~ 80°C) Operating Humidity 0% ~ 90% relative humidity, non-condensing MTBF (Hours) 250,817 CE/FCC Class A Chapter 1 – Product Specifications...

  • Page 20: Block Diagram

    Block Diagram Chapter 1 – Product Specifications...

  • Page 21: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 22: Dimensions

    Dimensions System Chapter 2 – Hardware Information...
  • Page 23 Board Chapter 2 – Hardware Information...

  • Page 24: Jumpers And Connectors

    Jumpers and Connectors Component Side Solder Side Chapter 2 – Hardware Information...

  • Page 25: List Of Jumpers

    List of Jumpers The board features a number of jumpers which can be configured for your application. Please refer to the table below and following sections for all jumpers which can be configured. Label Function Auto Power Button Enable/Disable Selection Clear CMOS Jumper 2.3.1 Auto Power Button Enable/Disable Selection (JP5)

  • Page 26: List Of Connectors

    List of Connectors This section details the connectors featured on the board, which can be configured for your application. For a list of mating connectors and cables, please see Appendix C. For Electrical Specifications of I/O Ports, please see Appendix D. Please refer to the table below for a list of all connectors on this board which can be configured.
  • Page 27 Label Function CN40 DDR4 SODIMM1 CN41 Half Size Mini Card/mSATA CN42 M.2 3052 B-Key CN43 M.2 2280 M-Key CN44 SPI Flash Programming Port CN45 COM Port 1 & 2 (RS232/422/485) CN48 DIO (16-bit) CN51 External Power Input Chapter 2 – Hardware Information...

  • Page 28: Vga Connector (Cn1)

    2.4.1 VGA Connector (CN1) Pin Name Signal Type Signal Level VSYNC HSYNC DDC_CLK DDC_DATA BLUE GREEN Chapter 2 – Hardware Information...

  • Page 29: Fan Connector (Cn2 & Cn34)

    2.4.2 FAN Connector (CN2 & CN34) Pin Name Signal Type Signal Level +V12S +12V TACH 2.4.3 SATA Port (CN4) Pin Name Signal Type Signal Level SATA_TX+ DIFF SATA_TX- DIFF SATA_RX- DIFF SATA_RX+ DIFF Chapter 2 – Hardware Information...

  • Page 30: Sata Port (Cn5)

    2.4.4 SATA Port (CN5) Pin Name Signal Type Signal Level SATA_TX+ DIFF SATA_TX- DIFF SATA_RX- DIFF SATA_RX+ DIFF 2.4.5 External +12V Input (CN7) Standard ATX 12V Power Connector. Chapter 2 – Hardware Information...

  • Page 31: Output For Sata Hdd (Cn12)

    2.4.6 +5V Output for SATA HDD (CN12) Pin Name Signal Type Signal Level 2.4.7 DDR4 SODIMM Slot (CN17 & CN40) Standard specification. 2.4.8 Front Panel (CN18) Pin Name Pin Name Pin 1 PWR_BTN- Pin 2 PWR_BTN+ Pin 3 HDD_LED- Pin 4 HDD_LED+ Pin 5 SPEAKER-...

  • Page 32: Usb 2.0 Port 1 & 2 (Cn22)

    2.4.9 USB 2.0 Port 1 & 2 (CN22) Pin Name Pin Name Pin 1 5V_USB Pin 2 5V_USB Pin 3 USB2_5_DN Pin 4 USB2_6_DN Pin 5 USB2_5_DP Pin 6 USB2_6_DP Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 5V_USB Pin 12 5V_USB...

  • Page 33: Rtc Battery Connector (Cn26)

    Pin Name Signal Type Signal Level SMB_DATA/I2C_SDA/3. +3.3V SMB_CLK/I2C_CLK +3.3V SMB_ALERT/SERIRQ +3.3V 2.4.11 RTC Battery Connector (CN26) Pin Name Signal Type Signal Level +3.3V +3.3V Chapter 2 – Hardware Information...

  • Page 34: Hdmi (Cn28)

    2.4.12 HDMI (CN28) Pin Name Signal Type Signal Level HDMI_TX2+ DIFF HDMI_TX2- DIFF HDMI_TX1+ DIFF HDMI_TX1- DIFF HDMI_TX0+ DIFF HDMI_TX0- DIFF HDMI_CLK+ DIFF HDMI_CLK- DIFF DDC_CLK DDC_DATA HDMI_HPD Chapter 2 – Hardware Information...

  • Page 35: Lan I225 (Left), I219 (Right) (Cn29)

    2.4.13 RJ-45 LAN I225 (Left), I219 (Right) (CN29) Pin Name Pin Name LAN2_MDI0_P LAN1_MDI0_P LAN2_MDI0_N LAN1_MDI0_N LAN2_MDI1_P LAN1_MDI1_P LAN2_MDI1_N LAN1_MDI1_N 1CT5 2CT5 1CT6 2CT6 LAN2_MDI2_P LAN1_MDI2_P LAN2_MDI2_N LAN1_MDI2_N LAN2_MDI3_P LAN1_MDI3_P 1P10 LAN2_MDI3_N 2P10 LAN1_MDI3_N LAN2_LED_LINK# LAN1_LED_LINK# LAN2_LED_3P3A LAN1_LED_3P3A LAN2_LED_2500# LAN1_LED_100# LAN2_LED_1000# LAN1_LED_1000# Chapter 2 –...

  • Page 36: Usb 3.2/Usb 2.0 Port 1 & 2 (Cn31 & Cn32)

    2.4.14 USB 3.2/USB 2.0 Port 1 & 2 (CN31 & CN32) Pin Name Signal Type Signal Level +5VSB USB0_D- DIFF USB0_D+ DIFF USB0_SSRX− DIFF USB0_SSRX+ DIFF USB0_SSTX− DIFF USB0_SSTX+ DIFF +5VSB USB1_D- DIFF USB1_D+ DIFF USB1_SSRX− DIFF USB1_SSRX+ DIFF USB1_SSTX− DIFF USB1_SSTX+ DIFF...

  • Page 37: Dual Dp Port (Cn33)

    2.4.15 Dual DP Port (CN33) Pin Name Signal Type Signal Level DP1_TX0_DP DIFF DP1_TX0_DN DIFF DP1_TX1_DP DIFF DP1_TX1_DN DIFF DP1_TX2_DP DIFF DP1_TX2_DN DIFF DP1_TX3_DP DIFF DP1_TX3_DN DIFF DP1_OB_AUX_EN DP1_AUX_DP DP1_AUX_DN HDMI_HPD1 +V3P3S +3.3V DP2_TX0_DP DIFF DP2_TX0_DN DIFF DP2_TX1_DP DIFF Chapter 2 – Hardware Information...

  • Page 38: Pcie Fpc Connector (Cn38)

    Pin Name Signal Type Signal Level DP2_TX1_DN DIFF DP2_TX2_DP DIFF DP2_TX2_DN DIFF DP2_TX3_DP DIFF DP2_TX3_DN DIFF DP2_OB_AUX_EN DP2_AUX_DP DP2_AUX_DN HDMI_HPD2 +V3P3S +3.3V 2.4.16 PCIe FPC Connector (CN38) Pin Name Signal Type Signal Level +V3P3S +3.3V +V3P3S +3.3V +V3P3S +3.3V SMB_DATA SMB_CLK BUF_PLT_RST# +V3P3A...
  • Page 39 Pin Name Signal Type Signal Level PCIE_18_RXP DIFF PCIE_18_RXN DIFF PCIE_20_RXP DIFF PCIE_20_RXN DIFF PCIE_19_RXP DIFF PCIE_19_RXN DIFF PCIE_17_RXP DIFF PCIE_17_RXN DIFF PCIE_20_TXN DIFF PCIE_20_TXP DIFF PCIE_19_TXN DIFF PCIE_19_TXP DIFF PCIE_18_TXN DIFF PCIE_18_TXP DIFF CLK_PCIE_FPC_N DIFF CLK_PCIE_FPC_P DIFF PCIE_17_TXN DIFF PCIE_17_TXP DIFF Chapter 2 –...

  • Page 40: Nano Sim Card Socket (Cn39)

    Pin Name Signal Type Signal Level +V12S +V12S +V12S +V12S +V12S 2.4.17 Nano SIM Card Socket (CN39) Pin Name Signal Type Signal Level UIM_PWR UIM_RST UIM_CLK UIM_VPP UIM_DATA Chapter 2 – Hardware Information...

  • Page 41: Half Size Mini Card Slot (Cn41)

    2.4.18 Half Size Mini Card Slot (CN41) Pin Name Signal Type Signal Level PCIE_WAKE# +3.3VSB +3.3V +1.5V +1.5V PCIE_CLK_REQ# UIM_PWR UIM_DATA PCIE_REF_CLK- DIFF UIM_CLK PCIE_REF_CLK+ DIFF UIM_RST UIM_VPP W_DISABLE# +3.3V PCIE_RST# +3.3V PCIE_RX- DIFF +3.3VSB +3.3V Chapter 2 – Hardware Information...
  • Page 42 Pin Name Signal Type Signal Level PCIE_RX+ DIFF +1.5V +1.5V SMB_CLK +3.3V PCIE_TX- DIFF SMB_DATA +3.3V PCIE_TX+ DIFF USB_D- DIFF USB_D+ DIFF +3.3VSB +3.3V +3.3VSB +3.3V +1.5V +1.5V Chapter 2 – Hardware Information...

  • Page 43: 3052 B-Key Slot (Cn42)

    Pin Name Signal Type Signal Level +3.3VSB +3.3V 2.4.19 M.2 3052 B-Key Slot (CN42) Standard specification. 2.4.20 M.2 2280 M-Key Slot (CN43) Pin Name Signal Type Signal Level +3.3V +3.3V +3.3V +3.3V PCIE3_RX- DIFF PCIE3_RX+ DIFF SATA_LED +3.3V PCIE3_TX- +3.3V +3.3V PCIE3_TX+ +3.3V...
  • Page 44 Pin Name Signal Type Signal Level PCIE2_RX+ DIFF PCIE2_TX- DIFF PCIE2_TX+ DIFF PCIE1_RX- DIFF PCIE1_RX+ DIFF PCIE1_TX- DIFF PCIE1_TX+ DIFF DECSLP PCIE0_RX- DIFF PCIE0_RX+ DIFF Chapter 2 – Hardware Information...
  • Page 45 Pin Name Signal Type Signal Level PCIE0_TX- DIFF PCIE0_TX+ DIFF PERST# PCIE_CLK_REQ# PCIE_CLK- DIFF PCIE_WAKE PCIE_CLK+ DIFF +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V Chapter 2 – Hardware Information...

  • Page 46: Spi Flash Programming Port (Cn44)

    2.4.20 SPI Flash Programming Port (CN44) Pin Name Signal Type Signal Level SPI_MISO SPI_CLK +3.3VSB +3.3V SPI_MOSI SPI_CS Chapter 2 – Hardware Information...

  • Page 47: Com Port 1/2 (Cn45)

    2.4.21 COM Port 1/2 (CN45) RS-232 Pin Port 1 Pin Port 2 Pin Name Signal Type Signal Level ±5V ±5V ±5V Chapter 2 – Hardware Information...
  • Page 48 RS-422 Pin Port 1 Pin Port 2 Pin Name Signal Type Signal Level RS422_TX- ±5V RS422_TX+ ±5V RS422_RX+ RS422_RX- +5V/+12V(0.5A) PWR +5V/+12V RS-485 Pin Port 1 Pin Port 2 Pin Name Signal Type Signal Level RS485_ D- ±5V RS485_D+ ±5V +5V/+12V(0.5A) PWR +5V/+12V Note: COM2 RS-232/422/485 can be set by BIOS setting.

  • Page 49: Dio Port (Cn48)

    2.4.22 DIO Port (CN48) Pin Name Pin Name Pin 1 Pin 2 Pin 3 DIO7_0 Pin 4 DIO8_0 Pin 5 DIO7_1 Pin 6 DIO8_1 Pin 7 DIO7_2 Pin 8 DIO8_2 Pin 9 DIO7_3 Pin 10 DIO8_3 Chapter 2 – Hardware Information...

  • Page 50: External Power Input (Cn51)

    Pin Name Pin Name Pin 11 DIO7_4 Pin 12 DIO8_4 Pin 13 DIO7_5 Pin 14 DIO8_5 Pin 15 DIO7_6 Pin 16 DIO8_6 Pin 17 DIO7_7 Pin 18 DIO8_7 2.4.23 External Power Input (CN51) Pin Name Signal Type Signal Level +VIN +12V Chapter 2 –...

  • Page 51: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 52: System Test And Initialization

    System Test and Initialization These routines test and initialize board hardware. If the routines encounter an error during the tests, you will either hear a few short beeps or see an error message on the screen. There are two kinds of errors: fatal and non-fatal. The system can usually continue the boot up sequence with non-fatal errors.

  • Page 53: Ami Bios Setup

    AMI BIOS Setup AMI BIOS ROM has a built-in Setup program that allows users to modify the basic system configuration. This type of information is stored in battery-backed CMOS RAM and BIOS NVRAM so that it retains the Setup information when the power is turned off. Entering Setup Power on the computer and press <Del>or <ESC>...

  • Page 54: Setup Submenu: Main

    Setup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 55: Setup Submenu: Advanced

    Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 56: Cpu Configuration

    3.4.1 CPU Configuration Options Summary Disabled Intel (VMX) Virtualization Technology Enabled Optimal Default, Failsafe Default When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology. Disabled Intel(R) SpeedStep(tm) Enabled Optimal Default, Failsafe Default Allows more than two frequency ranges to be supported. Disabled Turbo Mode Enabled...

  • Page 57: Memory Configuration

    3.4.2 Memory Configuration Chapter 3 – AMI BIOS Setup...

  • Page 58: Hardware Monitor

    3.4.3 Hardware Monitor Options Summary Disabled Smart Fan Enabled Optimal Default, Failsafe Default Enable or Disable Smart Fan. Chapter 3 – AMI BIOS Setup...

  • Page 59: Smart Fan Mode Configuration

    3.4.4 Smart Fan Mode Configuration Options Summary Output PWM mode (push pull) FAN1 Output Mode Linear Fan Application Output PWM mode Optimal Default, Failsafe Default (open drain) Output PWM mode (push pull) to control 4-wire fans. Linear fan application circuit to control 3-wire fan speed by fan’s power terminal.
  • Page 60 Options Summary Duty Cycle Auto fan speed control. Fan speed will follow different Temperature temperature by different duty cycle 1-100 Options Summary Output PWM mode (push pull) FAN2 Output Mode Linear Fan Application Output PWM mode Optimal Default, Failsafe Default (open drain) Output PWM mode (push pull) to control 4-wire fans.
  • Page 61 Options Summary CPU(PECI) Temperature Optimal Default, Failsafe Default Temperature Source System Temperature 2 System Temperature Select the monitored temperature source for this fan. Duty Cycle Auto fan speed control. Fan speed will follow different temperature by different duty cycle 1-100 Temperature Options Summary Manual Duty Mode...

  • Page 62: Pch-Fw Configuration

    3.4.5 PCH-FW Configuration Chapter 3 – AMI BIOS Setup...

  • Page 63: Firmware Update Configuration

    3.4.6 Firmware Update Configuration Options Summary Disabled Optimal Default, Failsafe Default Me FW Image Re-Flash Enabled Enable/Disable Me FW Image Re-Flash function. Disabled FW Update Enabled Optimal Default, Failsafe Default Enable/Disable ME FW Update function. Chapter 3 – AMI BIOS Setup...

  • Page 64: Nvme Configuration

    3.4.7 NVMe Configuration Chapter 3 – AMI BIOS Setup...

  • Page 65: Power Management

    3.4.8 Power Management Options Summary ATX Type Optimal Default, Failsafe Default Power Mode AT Type Select system power mode. Last State Optimal Default, Failsafe Default Restore AC Power Loss Always On Always Off IO Restore AC power Loss. Disable Optimal Default, Failsafe Default Fixed Time RTC wake system from S5 Dynamic Time...

  • Page 66: Aaeon Bios Robot

    3.4.9 AAEON BIOS Robot Options Summary Disabled Optimal Default, Failsafe Default Sends watch dog before BIOS POST Enabled Enabled - Robot set Watch Dog Timer (WDT) right after power on, before BIOS start POST process. And then Robot will clear WDT on completion of POST. WDT will reset system automatically if it is not cleared before its timer counts down to zero.
  • Page 67 Options Summary OS Timer (minute) Optimal Default, Failsafe Default Timer count set to Watch Dog Timer for OS loading. Disabled Optimal Default, Failsafe Default Delayed POST (PEI phase) Enabled Enabled - Robot holds BIOS from starting POST, right after power on. This allows BIOS POST to start with stable power or start after system is physically warmed-up.

  • Page 68: Device Detecting Configuration

    3.4.10 Device Detecting Configuration Options Summary Action Reset System Optimal Default, Failsafe Default Hold System Select action that robot should do. Soft or hard reset Soft Optimal Default, Failsafe Default Hard Select reset type robot should send on each boot. Retry-Count Optimal Default, Failsafe Default Fill retry counter here.
  • Page 69 Options Summary Action Reset System Optimal Default, Failsafe Default Hold System Select action that robot should do. Holding time out (second) Optimal Default, Failsafe Default Fill hold time out here. Robot will hold system no longer then time-out value, and then let system continue its POST.

  • Page 70: Device #* Detecting Configuration - Interface

    3.4.10.1 Device #* Detecting Configuration – Interface Options Summary Interface Disabled Optimal Default, Failsafe Default SMBUS Legacy I/O Super I/O MMIO Select interface robot should use to communicate with device. Chapter 3 – AMI BIOS Setup...

  • Page 71: Device #* Detecting Configuration - Pci

    3.4.10.2 Device #* Detecting Configuration – PCI Options Summary When interface item set to "PCI" it will show below items Optimal Default, Failsafe Default Fill BUS number to a PCI device, in hexadecimal. Range: 0 – FF. Device Optimal Default, Failsafe Default Fill DEVICE number to a PCI device, in hexadecimal.
  • Page 72 Options Summary Register data is bitwise equal to Optimal Default, Failsafe Default bytewise equal to bytewise lesser than bytewise larger than Select how robot should compare data read from register, to a value configured below. Register offset Optimal Default, Failsafe Default Fill register offset (or index) for robot to read, in hexadecimal.

  • Page 73: Device #* Detecting Configuration - Dio

    3.4.10.3 Device #* Detecting Configuration – DIO Options Summary When interface item set to "DIO" will show below items Device Is not Optimal Default, Failsafe Default Select that robot should or should not do action if condition met. DIO pin number DIO1 Optimal Default, Failsafe Default DIO*...

  • Page 74: Device #* Detecting Configuration - Smbus

    3.4.10.4 Device #* Detecting Configuration – SMBUS Options Summary When interface item set to "SMBUS" will show below items SMBUS Slave Address Optimal Default, Failsafe Default Fill slave address to a SMBUS device, in hexadecimal. Range: 0 – FF. Device Is not Optimal Default, Failsafe Default Select that robot should or should not do action if condition met.
  • Page 75 Options Summary Select how robot should compare data read from register, to a value configured below. Register offset Optimal Default, Failsafe Default Fill register offset (or index) for robot to read, in hexadecimal. Range: 0 – FF. Bit offset Optimal Default, Failsafe Default Fill bit offset for register, for robot to compare with bit value.

  • Page 76: Device #* Detecting Configuration - Legacy I/O

    3.4.10.5 Device #* Detecting Configuration – Legacy I/O Options Summary When interface item set to "Legacy I/O" will show below items I/O Address Optimal Default, Failsafe Default Fill I/O address device is responding to. Range: 0~FFFF. Device Is not Optimal Default, Failsafe Default Select that robot should or should not do action if condition met.

  • Page 77: Device #* Detecting Configuration - Super I/O

    Options Summary Select how robot should compare data read from register, to a value configured below. Bit offset Optimal Default, Failsafe Default Fill bit offset for register, for robot to compare with bit value. 3.4.10.6 Device #* Detecting Configuration – Super I/O Options Summary When interface item set to "Super I/O"...
  • Page 78 Options Summary Select the condition that robot should check for device. Present - device is detected. According to register - Robot read register according to configuration. Note: Device will be considered 'Present' by Robot, when data read from device is not 0xFF. Register data is bitwise equal to Optimal Default, Failsafe Default...

  • Page 79: Device #* Detecting Configuration - Mmio

    3.4.10.7 Device #* Detecting Configuration – MMIO Options Summary When interface item set to "MMIO" will show below items MMIO Address Optimal Default, Failsafe Default Fill Memory Mapped I/O address device is responding to. Range: 0~FFFFFFFF. Device Is not Optimal Default, Failsafe Default Select that robot should or should not do action if condition met.
  • Page 80 Options Summary Select how robot should compare data read from register, to a value configured below. Bit offset Optimal Default, Failsafe Default Fill bit offset for register, for robot to compare with bit value. Bit value Optimal Default, Failsafe Default High Fill bit value for robot to compare register-bit with specified offset.

  • Page 81: Setup Submenu: System I/O

    Setup Submenu: System I/O Chapter 3 – AMI BIOS Setup...

  • Page 82: Pci Express Configuration

    3.5.1 PCI Express Configuration Options Summary PCI Express Root Port 16 Enabled Optimal Default, Failsafe Default (CN41) Disabled Control the PCI Express Root Port. Chapter 3 – AMI BIOS Setup...

  • Page 83: Storage Configuration

    3.5.2 Storage Configuration Options Summary SATA Controller(s) Disabled Enabled Optimal Default, Failsafe Default Enable/Disable SATA Device. Port 0 Disabled Enabled Optimal Default, Failsafe Default Enable or Disable SATA Port. Hot Plug Disabled Optimal Default, Failsafe Default Enabled Designates this port as Hot Pluggable. Port 1 Disabled Enabled...

  • Page 84: Hd Audio Configuration

    3.5.3 HD Audio Configuration Options Summary HD Audio Disabled Enabled Optimal Default, Failsafe Default Control Detection of the HD-Audio device. Disabled = HDA will be unconditionally disabled. Enabled = HDA will be unconditionally enabled. Chapter 3 – AMI BIOS Setup...

  • Page 85: Digital Io Port Configuration

    3.5.4 Digital IO Port Configuration Options Summary DIO Port* Output Input Set DIO as Input or Output. Output Level High Optimal Default, Failsafe Default Set output level when DIO pin is output. Chapter 3 – AMI BIOS Setup...

  • Page 86: Legacy Logical Devices Configuration

    3.5.5 Legacy Logical Devices Configuration Chapter 3 – AMI BIOS Setup...

  • Page 87: Serial Port 1 Configuration

    3.5.5.1 Serial Port 1 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=3F8h; IRQ=4 IO=2F8h; IRQ=3 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 88: Serial Port 2 Configuration

    3.5.5.2 Serial Port 2 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=2F8h; IRQ=3 IO=3F8h; IRQ=4 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 89: Serial Port Console Redirection

    3.5.6 Serial Port Console Redirection Options Summary Console Redirection Disabled Optimal Default, Failsafe Default Enabled Console Redirection Enable or Disable. Console Redirection EMS Disabled Optimal Default, Failsafe Default Enabled Console Redirection Enable or Disable. Chapter 3 – AMI BIOS Setup...

  • Page 90: Console Redirection Settings

    3.5.7 Console Redirection Settings Options Summary Terminal Type VT100 VT100+ VT-UTF8 ANSI Optimal Default, Failsafe Default Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes. Bits Per second 9600 19200...
  • Page 91 Options Summary Data Bits Optimal Default, Failsafe Default Parity None Optimal Default, Failsafe Default Even Mark Space A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1's in the data bits is even. Odd: parity bit is 0 if num of 1's in the data bits is odd.

  • Page 92: Vmd Setup Menu

    Options Summary Putty KeyPad VT100 Optimal Default, Failsafe Default LINUX XTERMR6 ESCN VT400 Select FunctionKey and KeyPad on Putty. 3.5.8 VMD Setup Menu Options Summary Enable VMD controller Disabled Optimal Default, Failsafe Default Enabled Enable/Disable to VMD controller. Chapter 3 – AMI BIOS Setup...
  • Page 93 Options Summary Enable VMD Global Disabled Optimal Default, Failsafe Default Mapping Enabled Enable/Disable to VMD Global Mapping. Map this Root Port under Disabled Enabled Optimal Default, Failsafe Default Map/UnMap this Root Port to VMD. RAID0 Disabled Enabled Optimal Default, Failsafe Default Enable/Disable RAID0 support".

  • Page 94: Pch-Io Configuration

    Options Summary Intel Rapid Recovery Disabled Technology Enabled Optimal Default, Failsafe Default Enable/Disable Intel Rapid Recovery Technology. RRT volumes can span Disabled internal and eSATA drives Enabled Optimal Default, Failsafe Default Enable/Disable RRT volumes can span internal and eSATA drives. Intel(R) Optane(TM) Disabled Memory...

  • Page 95: Setup Submenu: Security

    Setup Submenu: Security Change User/Supervisor Password You can install a Supervisor password, and if you install a supervisor password, you can then install a user password. A user password does not provide access to many of the features in the Setup utility. If you highlight these items and press Enter, a dialog box appears which lets you enter a password.

  • Page 96: Trusted Computing

    3.6.1 Trusted Computing Options Summary Security Device Support Disable Enable Optimal Default, Failsafe Default Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. SHA-1 PCR Bank Disable Enable Optimal Default, Failsafe Default...
  • Page 97 Options Summary Platform Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or disable Platform Hierarchy. Storage Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Storage Hierarchy. Endorsement Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Endorsement Hierarchy. TPM2.0 UEFI Spec Version TCG_1_2 TCG_2...

  • Page 98: Secure Boot

    3.6.2 Secure Boot Options Summary Secure Boot Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System is in User mode. The mode change requires platform reset. Secure Boot Mode Custom Optimal Default, Failsafe Default...

  • Page 99: Key Management

    3.6.3 Key Management Options Summary Factory Key Provision Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System is in User mode. The mode change requires platform reset. Restore Factory Keys Force System to User Mode.
  • Page 100 Options Summary Device Guard ready system must not list 'Microsoft UEFI CA' Certificate in Authorized Signature database (db). Restore DB defaults Restore DB variable to factory defaults. Platform Key (PK) Details Export Update Delete Key Exchange Keys Details Export Update Append Delete Authorized Signatures...

  • Page 101: Setup Submenu: Boot

    Setup Submenu: Boot Options Summary Quiet Boot Disabled Enabled Optimal Default, Failsafe Default Enable/Disable showing boot logo. Lunch PXE ROM Disabled Optimal Default, Failsafe Default Enabled Enable/Disable UEFI Network Stack. Chapter 3 – AMI BIOS Setup...

  • Page 102: Bbs Priorities

    3.7.1 BBS Priorities Chapter 3 – AMI BIOS Setup...

  • Page 103: Setup Submenu: Save & Exit

    Setup Submenu: Save & Exit Chapter 3 – AMI BIOS Setup...

  • Page 104: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 105: Drivers Download And Installation

    Drivers Download and Installation Drivers for the EPIC-TGH7-PUC can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/epic-boards-11gen-intel-epic-tgh7-puc Download the driver(s) you need and follow the steps below to install them. Install Chipset Drivers Open the Chipset Driver folder Open the SetupChipset.exe file Follow the instructions...
  • Page 106 Install Peripheral Driver Open the– Peripheral Driver folder Open the SetupSerialIO.exe file Follow the instructions Drivers will be installed automatically Install ME & TXE Drivers Open the ME & TXE Driver folder Open the SetupME.exe file Follow the instructions Drivers will be installed automatically Install VMD Driver Open the VMD Driver folder Open the RstMwService.exe file...

  • Page 107: Appendix A - I/O Information

    Appendix A Appendix A – I/O Information...

  • Page 108: I/O Address Map

    I/O Address Map Appendix A – I/O Information...

  • Page 109: A.2 Memory Address Map

    A.2 Memory Address Map Appendix A – I/O Information...

  • Page 110: A.3 Irq Mapping Chart

    A.3 IRQ Mapping Chart Appendix A – I/O Information...
  • Page 111 Appendix A – I/O Information...
  • Page 112 Appendix A – I/O Information...

  • Page 113: Appendix B - Mating Connectors

    Appendix B Appendix B – Mating Connectors...

  • Page 114: List Of Mating Connectors And Cables

    List of Mating Connectors and Cables Mating Connector Conn. Function Vendo Available Cable Cable P/N Label Model no VGA Connector Molex 510211300 VGA cable 15cm 170X000715 Molex 22-01-2045 SATA Connector Molex 887505318 SATA Cable 15cm 170X000593 SATA Connector Molex 887505318 SATA Cable 15cm 170X000593 SATA power cable...

  • Page 115: Appendix C - Assembly Guide

    Appendix C Appendix C – Assembly Guide...

  • Page 116: Introduction

    Introduction This section details the steps needed to install various hardware components for the EPIC-TGH7-PUC. It is recommended that you read through each step before beginning installation and to make sure you have all necessary tools and components. DDR4 Module Installation (CN17/DDR4 SODIMM 0) Step 1: Loosen the two (2) screws located on the rear I/O side of the chassis, as shown.
  • Page 117 Following top cover removal, you will have access to the system’s motherboard. Step 3: Vertically insert the DDR4 module to the SODIMM slot until you hear a sharp click. Appendix C – Assembly Guide...
  • Page 118 Step 4: Replace the chassis top and tighten the two (2) screws that you loosened during step 1. Appendix C – Assembly Guide...

  • Page 119: Ddr4 Module Installation (Cn40/Ddr4 Sodimm 1)

    DDR4 Module Installation (CN40/DDR4 SODIMM 1) Note: The system’s second SODIMM slot is accessible via the bottom side of the chassis. Step 1: Remove the two (2) screws located on the bottom chassis cover, as shown. Step 2: Remove the bottom chassis cover by lifting slightly, then sliding it in the direction shown, keeping the cover flat throughout to avoid damage to the cover’s hinges.
  • Page 120 Step 3: Remove the plastic from the thermal pads and affix to the backplate, as shown. Following bottom cover removal, you will have access to the component side of the motherboard. Appendix C – Assembly Guide...
  • Page 121 Step 4: Horizontally insert your DDR4 module at a 30° angle, and then gently push down to affix to SODIMM hinges, at which point you will hear a sharp click. Appendix C – Assembly Guide...

  • Page 122: C.4 M.2 3052 B-Key Installation

    C.4 M.2 3052 B-Key Installation Follow standard procedures for expansion card installation, aligning the notch on the M.2 3052 module with the M.2 B-Key slot. Note the location of the mounting screws. Appendix C – Assembly Guide...

  • Page 123: M.2 2280 M-Key Installation

    M.2 2280 M-Key Installation Follow standard procedures for expansion card installation, aligning the notch on the M.2 2280 module with the M.2 M-Key slot. Note the location of the mounting screws. Once all expansion modules have been installed, reaffix backplate to chassis and affix with the two (2) screws removed during B.4 Step 1.

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