Compaq BL10e - HP ProLiant - 512 MB RAM Overview
Memory technology evolution: an overview of system memory technologies, 7th edition
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Memory technology evolution:
an overview of system memory technologies
technology brief, 8
th
Abstract .............................................................................................................................................. 2
Introduction ......................................................................................................................................... 2
Basic DRAM operation ......................................................................................................................... 2
DRAM storage density and power consumption ................................................................................... 4
Memory access time ......................................................................................................................... 5
System bus timing ............................................................................................................................ 5
Memory bus speed ........................................................................................................................... 6
Burst mode access ............................................................................................................................ 6
SDRAM technology .............................................................................................................................. 7
Bank interleaving ............................................................................................................................. 7
Increased bandwidth ........................................................................................................................ 7
Registered SDRAM modules .............................................................................................................. 8
DIMM configurations ........................................................................................................................ 8
DIMM error detection/correction technologies ................................................................................... 10
Memory protection technologies ...................................................................................................... 13
Advanced memory technologies .......................................................................................................... 15
Double data rate SDRAM technologies ............................................................................................. 15
Fully-buffered DIMMs ...................................................................................................................... 19
Rambus DRAM .............................................................................................................................. 21
Importance of using HP-certified memory modules in ProLiant servers ....................................................... 23
Conclusion ........................................................................................................................................ 23
For more information .......................................................................................................................... 24
Call to action .................................................................................................................................... 24
edition
Single-sided and double-sided DIMMs ............................................................................................ 8
Single-rank, dual-rank, and quad-rank DIMMs ................................................................................. 8
The increasing possibility of memory errors ................................................................................... 10
Basic ECC memory ..................................................................................................................... 11
Advanced ECC memory .............................................................................................................. 12
Online spare memory mode ........................................................................................................ 13
Mirrored memory mode .............................................................................................................. 13
Lockstep memory mode ............................................................................................................... 14
Memory protection mode summary ............................................................................................... 14
DDR-1 ....................................................................................................................................... 15
DDR-2 ....................................................................................................................................... 17
DDR-3 ....................................................................................................................................... 18
Module naming convention and peak bandwidth ........................................................................... 18
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Summary of Contents for Compaq BL10e - HP ProLiant - 512 MB RAM
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Page 1: Table Of Contents
Memory technology evolution: an overview of system memory technologies technology brief, 8 edition Abstract .............................. 2 Introduction ............................2 Basic DRAM operation ......................... 2 DRAM storage density and power consumption ................... 4 Memory access time ......................... 5 System bus timing ..........................5 Memory bus speed ........................... -
Page 2: Abstract
Abstract Both the widening performance gap between processors and memory and the growth of memory- intensive business applications are driving the need for better memory technologies for servers and workstations. Consequently, several memory technologies are on the market at any given time. HP evaluates developing memory technologies in terms of price, performance, and backward compatibility, and implements the most promising technologies in ProLiant servers. - Page 3 Each DRAM chip contains millions of memory locations (or cells), which are arranged in a matrix of rows and columns (Figure 1). Peripheral circuitry on the DIMM reads, amplifies, and transfers the data from the memory cells to the memory bus. Each DRAM row, called a page, consists of several DRAM cells.
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Page 4: Dram Storage Density And Power Consumption
When FPM or EDO memory writes data to a particular cell, the memory controller selects the location in which to write the data. The memory controller first selects the page by strobing the Row Address onto the address/command bus. It then selects the exact location by strobing the Column Address onto the address/command bus (see Figure 2). -
Page 5: Memory Access Time
Memory access time The length of time it takes for DRAM to produce the data, from the CAS signal until the data is available on the data bus, is called the memory access time or CAS Latency. For asynchronous DRAM, memory access time is measured in billionths of a second (nanoseconds, ns). For synchronous DRAM, the memory access time is measured by the number of memory bus clocks. -
Page 6: Memory Bus Speed
Memory bus speed The speed of the DRAM is not the same as the true speed (or frequency) of the overall memory subsystem. The memory subsystem operates at the memory bus speed, which may not be the same frequency (in MHz) as the main system bus clock. The two main factors that control the speed of the memory subsystem are the memory timing and the maximum DRAM speed. -
Page 7: Sdram Technology
SDRAM technology FPM and EDO DRAMs are controlled asynchronously, that is, without a memory bus clock. The memory controller determines when to assert signals and when to expect data based on absolute timing. The inefficiencies of transferring data between a synchronous system bus and an asynchronous memory bus results in longer latency. -
Page 8: Registered Sdram Modules
Registered SDRAM modules To achieve higher memory subsystem capacity, some DIMMs have register logic chips (registers) that act as a pass-through buffer for address and command signals (Figure 6). Registers prevent the memory controller from having to drive the entire arrangement of DRAM chips on each module. Rather, the memory controller drives only the loading of the registers on each module. - Page 9 A single-rank ECC DIMM (x4 or x8) uses all of its DRAM chips to create a single block of 72 bits, and all the chips are activated by one chip-select (CS) signal from the memory controller (top two illustrations in Figure 7). A dual-rank ECC DIMM produces two 72-bit blocks from two sets of DRAM chips on the DIMM, requiring two chip-select signals.
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Page 10: Dimm Error Detection/Correction Technologies
To prevent this and other memory-related problems, HP urges customers to use only HP-certified DIMMs, which are available in the memory option kits for each ProLiant server (see the “Importance of using HP-certified memory modules in ProLiant servers” section). Another important difference between single-rank and dual-rank DIMMs is cost. Typically, memory costs increase with DRAM density. -
Page 11: Basic Ecc Memory
Basic ECC memory Parity checking detects only single-bit errors. It does not correct memory errors or detect multi-bit errors. HP introduced error correction code (ECC) memory in 1993 and continues to implement advanced ECC in all HP ProLiant servers. ECC detects both single-bit and multi-bit errors in a 64-bit data word, and it corrects single-bit errors. -
Page 12: Advanced Ecc Memory
Advanced ECC memory To improve memory protection beyond standard ECC, HP introduced Advanced ECC technology in 1996. HP and most other server manufacturers use this solution in industry-standard products. Advanced ECC can correct a multi-bit error that occurs within one DRAM chip; thus, it can correct a complete DRAM chip failure. -
Page 13: Memory Protection Technologies
Memory protection technologies While advanced ECC provides memory correction, it does not provide failover capability. Replacing a failed DIMM requires powering down the system. Taking a server off line for unscheduled maintenance almost always raises operating costs—both in terms of replacement parts and in lost revenue from a server’s lack of availability. -
Page 14: Lockstep Memory Mode
Lockstep memory mode Lockstep memory mode uses two memory channels at a time and provides an even higher level of protection. In lockstep mode, two channels operate as a single channel—each write and read operation moves a data word two channels wide. The cache line is split across both channels to provide 2x 8-bit error detection and 8-bit error correction within a single DRAM. -
Page 15: Advanced Memory Technologies
Advanced memory technologies Despite the performance improvement in the overall system from using SDRAM, the growing performance gap between the memory and processor must be filled by more advanced memory technologies. These technologies, described on the following pages, boost the overall performance of systems using the latest high-speed processors (Figure 10). -
Page 16: Ddr-1
Double transition clocking Standard DRAM transfers one data bit to the bus on the rising edge of the bus clock signal, while DDR-1 uses both the rising and falling edges of the clock to trigger the data transfer to the bus (Figure 11). -
Page 17: Ddr-2
DDR-1 DIMMs DDR-1 DIMMs require 184 pins instead of the 168 pins used by standard SDRAM DIMMs. DDR-1 is versatile enough for use in desktop PCs or servers. To vary the cost of DDR-1 DIMMs for these different markets, memory manufacturers provide unbuffered and registered versions. Unbuffered DDR-1 DIMMs place the load of all the DDR modules on the system memory bus. -
Page 18: Ddr-3
DDR-3 DDR-3, the third-generation of DDR SDRAM technology, makes further improvements in bandwidth and power consumption. Manufacturers of DDR-3 started with 90 nm fabrication technology and are moving toward 70 nm as production volumes increase. DDR-3 operates at clock rates from 400 MHz to 800 MHz with theoretical peak bandwidths ranging from 6.40 GB/s to 12.8 GB/s. -
Page 19: Fully-Buffered Dimms
Table 2. Summary of DDR SDRAM technologies Type Component Module naming Bus speed Peak bandwidth naming convention convention DDR-1 DDR200 PC1600 100 MHz 1.6 GB/s DDR266 PC2100 133 MHz 2.1 GB/s DDR333 PC2700 166 MHz 2.7 GB/s DDR400 PC3200 200 MHz 3.2 GB/s DDR-2 DDR2-400... - Page 20 Each stub-bus connection creates an impedance discontinuity that negatively affects signal integrity. In addition, each DIMM creates an electrical load on the bus. The electrical load accumulates as DIMMs are added. These factors decrease the number DIMMs per channel that can be supported as the bus speed increases.
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Page 21: Rambus Dram
a read operation, the AMB serializes data from the DRAM devices and transmits it to the memory controller through the inbound links. Figure 17. Serial communication between daisy-chained FB-DIMMs on a single channel NOTE: AMD® Opteron® and Intel® Xeon® E55xx/X55xx CPU designs include the memory controller and clock functions integrated into processor module. - Page 22 Figure 18. Rambus DRAM RDRAM is capable of supporting up to 32 RDRAM devices on one memory channel while maintaining a 1.2-GHz data rate. Through the use of a repeater chip, even more devices can be placed on one RDRAM channel. The repeater interfaces to two different RDRAM channels and passes the data and command signals between them.
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Page 23: Importance Of Using Hp-Certified Memory Modules In Proliant Servers
Importance of using HP-certified memory modules in ProLiant servers There are several reasons why customers should use only HP memory option kits to replace or add memory in ProLiant servers. This section describes three of the most important reasons. First, not all DIMMs are created equal: They can vary greatly in quality and reliability. In the highly competitive memory market, some third-party memory resellers forego the level of qualification and testing needed for servers because it adds to the price of DIMMs. -
Page 24: For More Information
For more information For additional information, refer to the resources listed below. Resource description Web address JEDEC Web site http://www.jedec.org Fully-Buffered DIMM technology in HP http://h18004.www1.hp.com/products/servers/technology/whitepap ers/adv-technology.html#mem ProLiant servers Call to action Send comments about this paper to TechCom@HP.com © 2009 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.
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