Fully-Buffered Dimms - Compaq BL10e - HP ProLiant - 512 MB RAM Overview

Table 2. Summary of DDR SDRAM technologies
Type Component
naming
convention
DDR-1 DDR200
DDR266
DDR333
DDR400
DDR-2 DDR2-400
DDR2-533
DDR2-667
DDR2-800
DDR-3 DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600

Fully-buffered DIMMs

Traditional DIMM architectures use a stub-bus topology with parallel branches (stubs) that connect to
a shared memory bus (Figure 15). Each DIMM connects to the data bus using a set of pin connectors.
For the electrical signals from the memory controller to reach the DIMM bus-pin connections at the
same time, all the traces must be the same length. This can result in circuitous traces on the
motherboard between the memory controller and memory slots. Both the latency resulting from
complex routing of traces and signal degradation at the bus-pin connections cause the error rate to
increase as the bus speed increases.
Figure 15. Stub-bus topology
NOTE: In some CPU designs, the memory controller function is integrated into processor module.
Module naming Bus speed
convention
PC1600 100 MHz
PC2100 133 MHz
PC2700 166 MHz
PC3200 200 MHz
PC2-3200R 200 MHz
PC2-4300 266 MHz
PC2-5300 333 MHz
PC2-6400 400 MHz
PC3-6400 400 MHz
PC3-8500 533 MHz
PC3-10600 667 MHz
PC3-12800 800 MHz
Peak bandwidth
1.6 GB/s
2.1 GB/s
2.7 GB/s
3.2 GB/s
3.2 GB/s
4.3 GB/s
5.3 GB/s
6.4 GB/s
6.4 GB/s
8.5 GB/s
10.6 GB/s
12.8 GB/s
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