Chip Configuration - Asus Terminator Tualatin User Manual

Barebone system
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5.4.1 Chip Configuration

SDRAM Timing [By SPD]
This sets the optimal timings for items 2–4, depending on the memory
modules that you are using. The default setting is [By SPD], which
configures items 2–4 by reading the contents in the SPD (Serial
Presence Detect) device. The EEPROM on the memory module
stores critical parameter information about the module, such as
memory type, size, speed, voltage interface, and module banks.
Configuration options: [User Defined] [By SPD]
SDRAM CAS Latency [3T]
This controls the latency between the SDRAM read command and
the time that the data actually becomes available. NOTE: This field
is configurable only when you set the SDRAM Configuration to [User
Defined].
SDRAM RAS to CAS Delay [3T]
This controls the latency between the SDRAM active command and
the read/write command. NOTE: This field is configurable only when
you set the SDRAM Configuration to [User Defined].
SDRAM RAS Precharge Time [3T]
This controls the idle clocks after issuing a precharge command to
the SDRAM. NOTE: This field is configurable only when you set the
SDRAM Configuration to [User Defined].
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