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Siemens SIMATIC S5-155U CPU 948 Programming Manual

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SIMATIC S5

S5-155U

CPU 948

Programming Guide

Order No. 6ES5 998-3PR21

Release 03

C79000-H8576-C848-03

Introduction

User Program

Program Execution

Operating Statuses and Program

Execution Levels

Interrupt and Error Diagnosis

Integrated Special Functions

Extended Data Block DX 0

Memory Assignment and

Memory Organization

Memory Access Using

Absolute Addresses

Multiprocessor Mode and

Communication in the S5-155U

PG Interfaces and

Functions

Appendix

Further Reading

List of Abbreviations,

List of Key Words,

List of Tables and Figures

The Pocket Guide CPU 922/CPU 928/CPU 928B/

CPU 948

Order No. 6ES5 997-3UA22

is included with this manual.

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Table of Contents

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Summary of Contents for Siemens SIMATIC S5-155U CPU 948

Page 1 Introduction User Program SIMATIC S5 Program Execution S5-155U Operating Statuses and Program CPU 948 Execution Levels Interrupt and Error Diagnosis Programming Guide Integrated Special Functions Order No. 6ES5 998-3PR21 Release 03 Extended Data Block DX 0 Memory Assignment and Memory Organization Memory Access Using Absolute Addresses Multiprocessor Mode and...
Page 2: Disclaimer Of Liability
Copyright Copyright © Siemens AG 1993 All Rights Reserved The reproduction, transmission or use of this document or its contents is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved.
Page 3: How To Use This Manual
How to Use this Manual Scope This programming guide describes the following versions of the CPU 948 and its system software: Versions of the CPU 948 • • CPU 948-1 with 640 Kbytes of user memory, Order no. 6ES5 948-3UA11, from version A03 •...
Page 4: Overview Of The Chapters
How to Use this Manual Overview of the Chapters Chapter 1 This informs you about the areas of application of the S5-155U programmable controller with the CPU 948 and its device structure. It explains the typical mode of operation of the CPU and illustrates how a CPU program is structured.
Page 5 How to Use this Manual Chapter 6 This covers the special functions integrated in the system program. It tells you how to use the special functions and how to call and assign parameters to the special function OBs. The chapter also explains how to recognize and deal with errors in the processing of a special function.
Page 6 How to Use this Manual Chapter 13 This lists documentation for further reading. Chapter 14 This is intended to help you find themes quickly and contains a list of abbreviations and a list of keywords as well as lists of all the numbered tables and figures.
Page 7 How to Use this Manual Conventions used in the text To provide you with an overview of the contents of the pages, the manual uses the following conventions in addition to a 2nd and 3rd order of titles: Entries in the margin Entries in the margin are keywords printed in italics on the left-hand edge of a page.
Page 8: Reference Tables
How to Use this Manual Reference tables Specific information you may require at any time is contained in numbered tables as shown in the following example and can be found in the list of tables (refer to Chapter 14). Table 3-2 Binary logic operations Operation Operand...
Page 9: Table Of Contents
Contents Contents Introduction..............1-3 Area of Application for the S5-155U with the CPU 948 .
Page 10 2.3.2 Programming Function Blocks ........... 2-26 2.3.3 Calling Function Blocks and Assigning Parameters to them .
Page 11 Interrupt and Error Diagnostics ..........5-3 Frequent Errors in the User Program .
Page 12 6.12 OB 143: "Delay Single Cyclic Timed Interrupts" On/Off ......6-35 6.13 OB 150: Set/Read System Time .
Page 13 Memory Access Using Absolute Addresses ......... 9-3 Introduction .
Page 14 10.6 SEND TEST Function (OB 203) ..........10-45 10.6.1 Function .
Page 15 Appendix ..............12-3 Appendix 1: Jumper Settings for System Interrupts.
Page 16: Introduction
Introduction Contents of Chapter 1 Area of Application for the S5-155U with the CPU 948 ......1 - 4 Typical Mode of Operation of a CPU .
Page 17: Contents Of Chapter 1
STEP 5 /3/ or take part in a course at our training center. SIEMENS provides comprehensive training for SIMATIC S5. For more detailed information, contact your local SIEMENS office.
Page 18: Area Of Application For The S5-155U With The Cpu 948
Area of Application for the S5-155U with the CPU 948 Area of Application for the S5-155U with the CPU 948 SIMATIC S5 family The S5-155U programmable controller belongs to the family of SIMATIC S5 programmable controllers. With the CPU 948, it is the most powerful multiprocessor unit for process automation (open and closed loop control, signalling, monitoring, logging).
Page 19: Example Of Application
Area of Application for the S5-155U with the CPU 948 Example of application Fig. 1-1 illustrates the use of the S5-155U programmable controller in a cement works. PG 7 7 0 PG 7 7 0 PG 7 7 0 PG 7 7 0 PG 7 7 0 System management Data base/...
Page 20: Typical Mode Of Operation Of A Cpu
Typical Mode of Operation of a CPU Typical Mode of Operation of a CPU Mode of operation of a CPU The following modes of operation are possible in a CPU: Time-controlled processing Cyclic processing Interrupt-driven processing Cyclic processing This is the main part of all activities in the CPU. As the name already says, the same operations are repeated in an endless cycle.
Page 21 Typical Mode of Operation of a CPU Time-controlled processing In addition to the cyclic processing, time-controlled processing is also available for processes requiring control signals at constant intervals, e.g. non-time critical monitoring functions performed every second. Interrupt-driven processing If the reaction to a particular process signal must be particularly fast, this should be handled with interrupt-driven processing.
Page 22: The Programs In A Cpu
The Programs in a CPU The Programs in a CPU The program existing on every CPU is divided into the following: • • the system program • • the user program. System program The system program organizes all the functions and sequences of the CPU which do not involve a specific control task (refer to Fig.
Page 23 The Programs in a CPU Tasks The tasks include the following: • • cold and warm restart, • • updating the process image of the inputs and outputting the process image of the outputs, • • calling the cyclic, time-controlled and interrupt-driven programs, •...
Page 24 The Programs in a CPU User program Tasks The user program contains all the functions required for processing a specific control task. In general terms, these functions can be assigned to the interface provided by the system program for the various types of processing, as follows: Type of processing Task...
Page 25: User Program
The Programs in a CPU Structure User memory User program Code blocks Organization Program Sequence Function blocks blocks blocks blocks FB/FX STEP 5 STEP 5 STEP 5 STEP 5 operations operations operations operations I 1.5 & F 1.7 FB 8 F 50.1 I 2.6 I 1.6...
Page 26: Which Operands Are Available To The User Program
Which Operands are available to the User Program? Which Operands are available to the User Program? The CPU 948 provides the following operand areas for programming: • • process image and I/Os • • flags (F flags and S flags) •...
Page 27 Which Operands are available to the User Program? F flags Characteristics Size The flag area is a memory area which the user 2048 bits program can access extremely quickly with certain operations. The flag area should be used ideally for working data required often.
Page 28 Which Operands are available to the User Program? Timers (T) Characteristics Size The user program loads timer cells with a time value 256 timer between 10 ms and 9990 s and by means of a start cells operation, decrements the timer from this value at the preselected intervals until it reaches the value zero.
Page 29: How Much Memory Is Available For The User Program
How much Memory is available for the User Program? How much Memory is available for the User Program? For storing logic and data blocks, the CPU 948 only has the user memory in the internal RAM. The CPU 948 is available with two versions of the user memory: •...
Page 30: How To Tackle Programming
How to Tackle Programming How to Tackle Programming If you are an experienced user, you have probably found the most suitable method for creating programs for yourself and you can skip this section. Less experienced readers will find tips for designing, programming, testing and starting up your STEP 5 program.
Page 31 How to Tackle Programming Stage 2 Designing the program Stage Activity Based on the improved block diagram, decide on the types of processing required of your program (cyclic processing, time-controlled processing etc.) and select the OBs required for this. Divide the types of processing into technological and/or functional units.
Page 32 How to Tackle Programming Stage 3 Creating, testing and starting up the program: Stage Activity Decide on the type of representation for the logic blocks (LAD, CSF or STL, refer to Chapter 2). Remember that function blocks can only be created in the STL method of representation.
Page 33: Programming Tools
Programming Tools Programming Tools Suitable PGs The following programmers are available for creating your user program, PG 685, PG 710, PG 730, PG 750 and PG 770. You can check on the performance and characteristics of these devices in the catalog ST 59 /9/.
Page 34: What Is New With The Cpu 948
What is New with the CPU 948? What is New with the CPU 948? 1.8.1 CPU 948, Version A01 Compared with the CPU 946/947, the CPU 948 version A01 has new characteristics and functions and significant improvements in performance. Faster processing The CPU 948 is between three and five times faster than the CPU 946/947.
Page 35 What is New with the CPU 948? Interruptability at block or With a CPU 948, there is no longer a distinction between 150/155U operation boundaries modes. This means the following changes compared with the CPU 946/947: CPU 948 CPU 946/947 Processing system interrupts: Processing systems interrupts: possible with interrupts at the...
Page 36 What is New with the CPU 948? Self test functions WHAT IS TESTED? WHEN? The user memory In OVERALL RESET The BASP signal In STOP (disable command output) The hardware clock In COLD RESTART The cycle time monitoring In START-UP The address lines Cyclically in RUN The code of the system program...
Page 37: Cpu 948, Version A02
What is New with the CPU 948? 1.8.2 CPU 948, Version The CPU 948, version A02, provides you with new features and functions compared with the CPU 948, version A01: Communication via the As with the CPU 928B, the following communications options are second serial interface available via the second serial interface: •...
Page 38: Converting User Programs Of The Cpu 928B For The Cpu 948
Converting User Programs of the CPU 928B for the CPU 948 Converting User Programs of the CPU 928B for the CPU 948 The following section informs you about the points you should remember when you convert user programs written for the CPU 928B for use on the CPU 948.
Page 39 Converting User Programs of the CPU 928B for the CPU 948 Timer processing CPU 928B CPU 948 The timers are updated during The timers are only updated in start-up. the RUN mode (Reason: compatibility with CPU 946/947) FB 0 as cycle block CPU 928B CPU 948 If no cycle block OB 1 exists, the...
Page 40: Organization Blocks
Converting User Programs of the CPU 928B for the CPU 948 Data block DX 0 You must create a new DX 0 data block (see Chapter 7), since the DX 0 for the CPU 928B has a different structure and settings. Using the RT area With the CPU 928B, the RT area is not used by the system program, with the CPU 948 it is used to some extent by the handling blocks.
Page 41 Converting User Programs of the CPU 928B for the CPU 948 Note OB 180 In contrast to the CPU 928B, the access window of the CPU 948 can only be shifted by a multiple of OB 200 In contrast to the CPU 928B, these CPU 948 OBs OB 202 to 205 change the content of ACCU 4.
Page 42: User Program
User Program Contents of Chapter 2 STEP 5 Programming Language ......... . . 2 - 4 2.1.1 The LAD, CSF, STL Methods of Representation .
Page 43 User Program The following chapter explains the components that make up a STEP 5 user program for the CPU 948 and how it can be structured. CPU 948 Programming Guide 2 - 3 C79000-B8576-C848-03...
Page 44: Step 5 Programming Language
STEP 5 Programming Language STEP 5 Programming Language With the STEP 5 programming language, you convert automation tasks into programs that run on SIMATIC S5 programmable controllers. You can program simple binary functions, complex digital functions and arithmetic operations including floating point arithmetic using STEP 5.
Page 45: Structured Programming
STEP 5 Programming Language Ladder diagram Statement list Control system flowchart Programming with Programming with Programming with graphic symbols graphic symbols mnemonic abbreviations like a circuit diagram of function designations complies with complies with complies with IEC 117-15 DIN 19239 DIN 19239 DIN 40700 DIN 40719...
Page 46: Step 5 Operations
STEP 5 Programming Language Structured programming offers you the following advantages: • • simple and clear creation of programs, even large ones • • standardization of program parts • • simple program organization • • easy program changes • • simple, section by section program test •...
Page 47 STEP 5 Programming Language Absolute and symbolic You can enter the operand absolutely or symbolically (using an operands assignment list) as shown in the following example: Absolute representation: :A I 1.4 Symbolic representation: :A -Motor1 For more information on absolute and symbolic programming, refer to your STEP 5 manual.
Page 48: Number Representation
STEP 5 Programming Language 2.1.4 Number Representation To allow the CPU to logically combine, modify or compare numerical values, these values must be located in the accumulators (working registers of the CPU) as binary numbers. Depending on the operations to be carried out, the following number representations are permitted in STEP 5: Binary numbers: 16-bit fixed point numbers...
Page 49 STEP 5 Programming Language 16-bit and 32-bit fixed Fixed point numbers are whole binary numbers with a sign. point numbers Coding of fixed point numbers Fixed point numbers are 16 bit (= 1 word) or 32 bit (= 2 words) in binary representation.
Page 50 STEP 5 Programming Language Using floating point numbers Use floating point numbers for solving extensive calculations, especially for multiplication and division or when you are working with very large or very small numbers! Accuracy The mantissa indicates the accuracy of the floating point number as follows: •...
Page 51 STEP 5 Programming Language in a data block: PG display after you enter the line: KG + 1234567 + 02 Mantissa with sign Exponent (base 10) with sign Value of the number input: +0.1234567 x 10 = 12.34567 You want to define the number N = - 0.005 as a floating point constant.
Page 52: Step 5 Blocks And Storing Them In Memory
STEP 5 Programming Language 2.1.5 STEP 5 Blocks and Storing them in Memory Identification A block is identified as follows: • • the block type (OB, PB, SB, FB, FX, DB, DX) • • the block number (number between 0 and 255). Block types The STEP 5 programming language differentiates between the following block types:...
Page 53 STEP 5 Programming Language Function blocks (FB/FX) You use function blocks to program frequently recurring and/or complex functions (e.g. digital functions, sequence control systems, closed loop controls and signalling functions). A function block can be called several times by higher order blocks and supplied with new operands (assigned parameters) at each call.
Page 54 STEP 5 Programming Language Block preheader The programmer also generates a block preheader (DV, DXV, FV, FXV) for block types DB, DX, FB and FX. These block preheaders contain information about the data format (for DB and DX) or the jump labels (for FB and FX).
Page 55: Fig. 2-2 Example Of Block Storage In The User Memory
STEP 5 Programming Language Block storage The programmer stores all programmed blocks in the program memory in the order in which they are transferred (Fig. 2-2). With the PG function "transfer data blocks A" the logic blocks are transferred first followed by the data blocks. The start addresses of all stored blocks are placed in an address list in data block DB 0.
Page 56: Program, Organization And Sequence Blocks
Program, Organization and Sequence Blocks Program, Organization and Sequence Blocks Program blocks (PBs), organization blocks (OBs) and sequence blocks (SBs) are the same with respect to programming and calling. You can program all three types in the LAD, CSF and STL methods of representation.
Page 57: Fig. 2-3 Block Calls That Enable Processing Of A Program Block
Program, Organization and Sequence Blocks Block calls can be unconditional or conditional as follows: Unconditional call The "JU" statement belongs to the unconditional operations. It has no effect on the RLO. The RLO is carried along with the jump to the new block.
Page 58: Organization Blocks As User Interfaces
Program, Organization and Sequence Blocks Effect of the BE statement After the "BE" statement (block end), the CPU continues the user program in the block in which the block call was programmed. Program execution continues at the STEP 5 statement following the block call.
Page 59: Table 2-1 Overview Of The Organization Blocks Of The Cpu 948 For Program Execution
Program, Organization and Sequence Blocks Table 2-1 Overview of the organization blocks of the CPU 948 for program execution Organization blocks for controlling program execution Block Function and call criterion OB 1 Organization of cyclic program execution; first call after a start-up, then cyclic call. With DX-0 setting "Process interrupt servicing via input byte IB 0 =on": (interruptability at block boundaries, can be set in DX 0)
Page 60: Table 2-2 Overview Of The Organization Blocks Of The Cpu 948 For Start-Up
Program, Organization and Sequence Blocks Table 2-2 Overview of the organization blocks of the CPU 948 for start-up Organization blocks to control the start-up procedure Block Function and call criterion OB 20 Call on request for COLD RESTART (manual and automatic) OB 21 Call on request for MANUAL WARM RESTART/COLD RESTART WITH MEMORY...
Page 61 Program, Organization and Sequence Blocks Organization blocks for reaction to device or program errors Block Function and call criterion OB 28 Timeout input byte IB 0 (process interrupts) OB 29 Timeout distributed I/Os, extended address volume OB 30 Timeout and parity error (PARE) accessing the user memory (OB 31) (set cycle monitoring time) OB 32...
Page 62: Organization Blocks For Special Functions
Program, Organization and Sequence Blocks 2.2.2 Organization Blocks for The following organization blocks contain special functions of the Special Functions system program. You cannot program these blocks, but simply call them (this applies to all OBs with numbers between 121 and 255!). They do not contain a STEP 5 program.
Page 63: Function Blocks
In the user program, each function block represents a complex complete function. You can obtain function blocks as follows: • • as a software product from SIEMENS (standard function blocks on diskette - see /11/); with these function blocks you can generate user programs for fast and simple open loop control, signalling, closed loop control and logging;...
Page 64: Structure Of Function Blocks
Function Blocks 2.3.1 Structure of Function Blocks The block header (five words) of a function block has the same structure as the headers of the other STEP 5 block types. The block body on the other hand, has a different structure from the bodies of the other block types.
Page 65 Function Blocks The memory contains all the information that the programmer needs to represent the function block graphically when it is called and to check the operands during parameter assignment and programming of the function block. The programmer rejects incorrect input. When handling function blocks, distinguish between the following procedures: •...
Page 66: Programming Function Blocks
Function Blocks 2.3.2 Programming You can program a function block only in the "statement list" Function Blocks method of representation. When entering a function block at a programmer, perform the following steps: Step Action Enter the block type (FB/FX) and the number of the function block.
Page 67: Table 2-5 Permitted Formal Operands For Function Blocks
Function Blocks Note If you change the order or the number of formal operands in the formal operand list, you must also update all STEP 5 statements in the function block that reference a formal operand and also the block parameter list in the calling block! Program or change function blocks only on diskette or hard disk and then transfer them to your CPU! Formal operands...
Page 68: Calling Function Blocks And Assigning Parameters To Them
Function Blocks 2.3.3 Calling Function Blocks You can call every function block as often as you want anywhere in and Assigning Parameters your STEP 5 program. You can call function blocks in a statement list to them or in one of the graphic methods of representation (CSF or LAD). To call a function block and assign parameters to it, perform the following steps: Step...
Page 69: Table 2-6 Permitted Actual Operands For Function Blocks
Function Blocks Permitted actual operands Which operands can be assigned as actual operands is shown in the following table. Table 2-6 Permitted actual operands for function blocks Parameter Data type Actual operands permitted type I, Q for an operand input with bit address output flag...
Page 70 Function Blocks Parameter Data type Actual operands permitted type for a fixed point number Constants -32768 to +32767 (Cont.) for a floating point number Data type designation not possible DB Data block; the operation C DB n is executed Function block (permitted only without parameters) called unconditionally (JU .
Page 71 Function Blocks Examples Example 1: the following (complete) example is intended to further clarify the programming and calling of a function block and the assign- ment of parameters to it. You yourself can easily try out the example. Programming the function block FB 202: FB 202 SEGMENT 1 EXAMPLE...
Page 72 Function Blocks Example 2: calling a function block and assigning parameters to it with the STL and CSF/LAD methods of representation in a program block. STL method of representation PB 25 SEGMENT 1 : C DB 5 : JU FB 201 NAME : REQUEST DATA : MTIM :...
Page 73: Special Function Blocks
Function Blocks 2.3.4 Special Function Blocks Apart from the function blocks that you program yourself, you can order standard function blocks as a finished software product. These contain standard functions for general use (e.g. signalling functions and sequence control). Standard function blocks are assigned numbers FB 1 to FB 199. If you order standard function blocks, remember the special instructions in the accompanying description (i.e.
Page 74 Function Blocks "Floating point root extractor" continued: STL method of representation LAD method of representation Seg- : C DB 17 ment SEGMENT 2 :*** : JU FB 6 FB 6 Seg- NAME : RAD : GP ment RADI : DD 5 DD 5 RADI F 15.0...
Page 75: Data Blocks
Data Blocks Data Blocks Data blocks (DB) or extended data blocks (DX) are used to store the fixed or variable data with which the user program works. No STEP 5 operations are processed in data blocks. The data of a data block includes the following: •...
Page 76: Block Header
Data Blocks Block header The block header occupies five words in the memory and contains the following: • • the block identifier • • the programmer identifier • • the block type and the block number • • the library number •...
Page 77: Creating Data Blocks
Data Blocks 2.4.1 Creating Data Blocks To create a data block, perform the following steps: Step Action Enter the block type (DB/DX) and data block number (2 or 3 to 255). Enter individual data words in the data format you require.
Page 78: Opening Data Blocks
Data Blocks 2.4.2 Opening Data Blocks You can only open a data block (DB/DX) unconditionally. This is possible within an organization, program, sequence or function block. You can open a specific data block more than once in a program. To open a data block, perform the following steps: IF...
Page 79 Data Blocks Note Before accessing a data word, you must open the data block you require in your program. This is the only way that the CPU can find the correct data word. The referenced data word must be contained in the opened block, otherwise the system program detects a load or transfer error.
Page 80 Data Blocks Example 2: range of validity of data blocks (Fig. 2-5) Data block DB 10 is opened in program block PB 7 (C DB 10). During the subsequent program execution, the data of this data block are processed. After the call (JU PB 20) program block PB 20 is processed. Data block DB 10, however, remains valid.
Page 81: Special Data Blocks
Data Blocks 2.4.3 Special Data Blocks On the CPU 948 data blocks DB 0, DB 1, DX 0, DX 1 and DX 2 are reserved for special functions. They are managed by the system program and you cannot use them freely for other functions. DB 0 PB 7 PB 20...
Page 82 Data Blocks DB 1 must be assigned parameters and loaded as follows: a) for multiprocessing b) when IPC flags exist with CPs • • Data block DX 0 (see Chapter 7) DX 0 If you assign parameters to data block DX 0 and load it, you can chan- ge the defaults of certain system program functions (e.g.
Page 83: Program Execution
Program Execution Contents of Chapter 3 Principle of Program Execution ..........3 - 4 Program Organization.
Page 84 3.5.4 Executive Operations ........... . 3 - 59 Jump operations.
Page 85 Program Execution This chapter is intended for readers who do not yet have any great experience in using the programming language. The chapter therefore deals with the basics of STEP 5 programming and explains in detail (with examples) the STEP 5 operations for the CPU 948. Experienced readers who require more information about a specific STEP 5 operation listed in the Pocket Guide can refer to the reference section in 3.5.
Page 86: Principle Of Program Execution
Principle of Program Execution Principle of Program Execution You can process your STEP 5 user program in various ways. Cyclic program execution is most common with programmable controllers (PLCs). The system program runs through a program loop (the cycle, refer to Section 3.4) and calls organization block OB 1 cyclically in each loop (refer to Fig.
Page 87: Program Organization
Program Organization Program Organization Program organization allows you to specify which conditions affect the processing of your blocks and the order in which they are processed. Organize your program by programming organization blocks with conditional or unconditional calls for the blocks you require. You can call additional program, function and sequence blocks in any combination in the program of individual organization, program, function and sequence blocks.
Page 88: Fig. 3-2 Example Of The Organization Of The User Program According To The Program Structure
Program Organization OB 1 PB ’A’ Op e r a t in g mo d e Stop to the system p r o g r a m EMERGENCY JU PB ’A’ Go to in itia l state PB ‘B‘ Co n t r o l o f Se q u e n c e Se q u e n c e c o n t r o l...
Page 89: Fig. 3-3 Example Of The Organization Of The User Program According To The Structure Of The
Program Organization P B ‘ X ‘ C o n t r o l l e d I n d i v i d u a l c o n t r o l s y s t e m p a r t ‘ X ‘ J U P B ‘...
Page 90: Fig. 3-4 Nested Logic Block Calls
Program Organization Nesting blocks Fig. 3-4 shows the principle of nested block calls. OB 1 PB 5 PB 20 1st STEP 5 op. 1st STEP 5 op. DB 20 DB 30 PB 20 F 1.5 FB 30 JU PB 5 NAME: KURV F 200.5 I 55.0...
Page 91: Fig. 3-5 Example Of Block Nesting Depth
Program Organization Nesting depth You can only nest 40 blocks within one another. If more than 40 blocks are called, the CPU signals an error and goes to the stop mode. Example of nesting depth Program processing level OB 25 OB 2 FB 21 PB 131...
Page 92: Storing Program And Data Blocks
Storing Program and Data Blocks Storing Program and Data Blocks On the CPU 948, the user program runs solely in the internal RAM. The user program including data blocks must, therefore, be loaded in the CPU 948 user memory. How do I load programs and You can use the following methods: data blocks in the internal RAM?
Page 93: Processing The User Program
Processing the User Program Processing the User Program The complete software on the CPU (consisting of the system program and the STEP 5 user program) has the following tasks: • • CPU START-UP • • Controlling an automation process by continuously repeating operations (CYCLE).
Page 94: Definition Of Terms Used In Program Execution
Processing the User Program Reactions to interrupts To allow you to specify the reactions to interrupts or errors, special and errors organization blocks (OB 2 to OB 18 for interrupt servicing, OB 19 and OB 23 to OB 34 for reactions to errors) are available on the CPU 948.
Page 95 Processing the User Program Cycle time monitoring The CPU monitors the cycle time in case it exceeds a maximum value. The standard setting for this maximum value is 200 ms. You can set the cycle time monitoring yourself or restart it during user program execution (refer to DX 0/Chapter 7 and special function OB OB 222/Section 6.16).
Page 96: Interrupt Events
Processing the User Program Interrupt events Cyclic program execution can be interrupted by the following: • • time-controlled program execution (delayed interrupt, cyclic timed interrupts, clock-controlled interrupts), • • interrupt-driven program execution (process interrupt, system interrupt). The cyclic program can be interrupted or even aborted completely by the following: •...
Page 97: Step 5 Operations With Examples
STEP 5 Operations with Examples STEP 5 Operations with Examples A STEP 5 operation consists of the operation and an operand. The operation specifies what the CPU is to do (operation). The operand specifies with what an operation is to be executed. STEP 5 operations can be divided into the following groups: •...
Page 98: Condition Codes
STEP 5 Operations with Examples • • Arithmetic operations combine the contents of ACCU 1 with those of ACCU 2, write the result to ACCU 1 and transfer the contents of ACCU 3 to ACCU 2 and the contents of ACCU 4 to ACCU 3 (stack drop).
Page 99 STEP 5 Operations with Examples Example of ERAB ERAB I 1.0 is set to ’1’, the new RLO is formed by an AND operation I 6.3 The RLO is influenced by an OR operation I 2.1 The RLO is influenced by an AND NOT operation.
Page 100: Table 3-1 Result Condition Codes Of Step 5 Operations
STEP 5 Operations with Examples • • CC 1 and CC 0 These are the result condition codes that you can interpret from the following table: Note To evaluate the condition codes directly, comparison and jump operations are available (refer to Sections 3.5.1 and 3.5.3). Table 3-1 Result condition codes of STEP 5 operations Word...
Page 101: Basic Operations
Basic Operations 3.5.1 Basic Operations You can use the basic operations in all logic blocks and all methods of representation (STL, LAD, CSF). Binary logic operations Table 3-2 Binary logic operations Operation Operand Function AND logic operation after scanning for signal state "1" OR logic operation after scanning for signal state "1"...
Page 102: Set/Reset Operations
Basic Operations Within a sequence of logic operations, the RLO is formed from the type of operation, previous RLO and the scanned signal state. A sequence of logic operations is completed by an operation (e.g. set/reset operations) which retains the RLO (ERAB = 0). Following this, the RLO can be evaluated but cannot be further combined.
Page 103: Load And Transfer Operations
Basic Operations Load and transfer operations Table 3-4 Load and transfer operations/part 1 Operation Operand Function Load Transfer 0 to 127 an input byte from/to the PII 0 to 126 an input word from/to the PII 0 to 124 an input double word from/to the PII 0 to 127 an output byte from/to the PIQ 0 to 126...
Page 104: Load Operations
Basic Operations Table 3-5 Load and transfer operations/part 2 Operation Operand Function Load 0 to 255 a constant, 1 byte 2 ASCII a constant, 2 ASCII characters characters -32768 to a constant as fixed point number +32767 a constant as floating point number 0 to FFFF a constant as hexadecimal number 0 to...
Page 105: Fig. 3-6 Load And Transfer Operations In A Byte-Oriented Memory Area
Basic Operations Examples of load and transfer operations Example 1: Fig. 3-6 illustrates loading/transferring a byte, word or double word bytes from/to a memory area organized in (PII, PIQ, flags, I/O). :L IB i load byte i of the PII into ACCU-1-LL :L IW j load bytes j and j+1 of the PII into ACCU-1-L :L FD k...
Page 106: Fig. 3-7 Load And Transfer Operations In A Word-Oriented Memory Area
Basic Operations Example 2: Fig. 3-7 illustrates the loading/transfer of a byte, word or double word from/into a memory area organized in words :L DR i load the right byte of data word i into ACCU-1-LL :L DL j load the left byte of data word j into ACCU-1-LL :L DW k load data word k into ACCU-1-L :L DD l load data words l and l+1 into ACCU 1 ACCU 1...
Page 107 Basic Operations Addressing I/Os You can use load and transfer operations to address the I/O peripherals as follows: • • directly using the following operations: L../T..PY, ..PW, ..OY, ..OW • • using the process image with the following operations: L../T..
Page 108: Timer And Counter Operations
Basic Operations Timer and Counter To load a timer using a start operation or a counter using a set operations operation, you must first load the value in ACCU 1. The following load operations are preferable: For timers: L KT, L IW, L QW, L FW, L DW, L SW. For counters: L KC, L IW, L QW, L FW, L DW, L SW.
Page 109 Basic Operations Timer value With the operation L KT, you can load a timer value directly into ACCU 1 or indirectly from a flag or data word. The value must have the following structure (with L KT, you specify the time base after the period in the operand as shown below): Bit no.
Page 110: Counter Value
Basic Operations Counter value With the operation L KC, you can load a counter value directly in ACCU 1 or indirectly from a flag or a data word. The value must have the following structure: Bit no. 15 14 13 Counter value 0 ...
Page 111 Basic Operations Further examples of timer and counter values Loading timer values directly: Ti m e r v a l u e Ti m e r T 1 0 A C C U 1 ’ 0 ’ "L T 10": Loads the binary timer value of timer T 10 directly into ACCU 1 The time base is not loaded.
Page 112 Basic Operations timer values Loading in BCD code: T i m e b a s e T i m e r v a l u e T i m e r T 1 0 B i n a r y B C D ’...
Page 113: Arithmetic Operations
Basic Operations Arithmetic operations Table 3-7 Arithmetic operations Operation Operand Function – Add two fixed point numbers (16 bits) Subtract one fixed point number from another (16 bits) Multiply two fixed point numbers (16 bits) Divide one fixed point number by another (16 bits): quotient in ACCU-1-L, remainder in ACCU-1-H Add two floating point numbers (32 bits) Subtract one floating point number from another (32 bits)
Page 114: Comparison Operations
Basic Operations Comparison operations Table 3-8 Comparison operations Operation Operand Function – Compare for equal to >< Compare for not equal to > Compare for greater than > = Compare for greater than or equal to < Compare for less than <= Compare for less than or equal to ...F:...
Page 115: Nop/Display/Stop Operations
Basic Operations G DB/GX DX Generating a data block The operation G DBx generates a DB data block with the number x (2 ≤ x ≤ 255) in the user memory of the CPU. The content of the data block is not assigned the value 0, i.e. the data words can have any contents.
Page 116: Programming Examples In The Stl, Lad And Csf Methods Of Representation
Programming Examples in the STL, LAD and CSF Methods of Representation 3.5.2 Programming Examples in the STL, LAD and CSF Methods of Representation Logic operations AND operation STEP 5 representation Logical/circuit diagram Statement Ladder Control system list diagram flowchart I 1.1 I 1.1 I 1.3 I 1.7...
Page 117 Programming Examples in the STL, LAD and CSF Methods of Representation Logic operations (continued) OR operation STEP 5 representation Logical/circuit diagram Statement Ladder Control system list diagram flowchart I 1.2 I 1.2 Q 3.2 I 1.2 1.7 1.5 I 1.2 I 1.7 I 1.7 I 1.5...
Page 118 Programming Examples in the STL, LAD and CSF Methods of Representation Logic operations (continued) /1st example OR-before-AND operation STEP 5 representation Logical/circuit diagram Statement Ladder Control system list diagram flowchart I 6.0 I 6.0 Q 2.1 I 6.0 I 6.1 I 6.2 I 6.3 I 6.0 I 6.2 I 6.3...
Page 119: Programming Examples In The Stl, Lad And Csf Methods Of Representation
Programming Examples in the STL, LAD and CSF Methods of Representation Logic operations (continued) Scan for signal state "0" STEP 5 representation Logical/circuit diagram Statement Ladder Control system list diagram flowchart I 1.5 I 1.6 Q 3.0 I 1.5 I 1.5 I 1.6 &...
Page 120 Programming Examples in the STL, LAD and CSF Methods of Representation Set/reset operations (continued) RS flip-flop with flags STEP 5 representation Logical/circuit diagram Statement Ladder Control system list diagram flowchart F 1.7 F 1.7 I 2.6 I 2.6 I 1.3 I 2.6 F 1.7 I 2.6...
Page 121 Programming Examples in the STL, LAD and CSF Methods of Representation Set/reset operations (continued) Simulation of a momentary contact relay (one shot) STEP 5 representation Logical/circuit diagram Statement Ladder Control system list diagram flowchart I 1.7 I 1.7 I 1.7 F 2.0 I 1.7 F 4.0 I 1.7...
Page 122: Timer Operations
Programming Examples in the STL, LAD and CSF Methods of Representation Timer operations Pulse timer STEP 5 representation Logical/circuit diagram Statement Ladder Control system list diagram flowchart I 3.0 I 3.0 KT 10.2 I 3.0 I 3.0 10.2 10.2 QW 0 Q4.0 QW 2 I 3.0...
Page 123 Programming Examples in the STL, LAD and CSF Methods of Representation Timer operations (continued) Extended pulse timer STEP 5 representation Logical/circuit diagram Statement Ladder Control system list diagram flowchart I 3.1 I 3.1 IW 15 I 3.1 I 3.1 IW15 IW15 Q4.1 Q4.1...
Page 124 Programming Examples in the STL, LAD and CSF Methods of Representation Timer operations (continued) ON-delay timer STEP 5 representation Logical/circuit diagram Statement Ladder Control system list diagram flowchart I 3.5 I 3.5 I 3.5 I 3.5 KT9.2 KT9.2 9s 0 Q4.2 I 3.5 Q4.2...
Page 125 Programming Examples in the STL, LAD and CSF Methods of Representation Timer operations (continued) Stored ON-delay timer STEP 5 representation Logical/circuit diagram Statement Ladder Control system list diagram flowchart I 3.3 I 3.2 I 3.3 I 3.3 I 3.3 KT 20.2 20.2 20.2 SS T...
Page 126: Counter Operations
Programming Examples in the STL, LAD and CSF Methods of Representation Counter operations Set counter STEP 5 representation Logical/circuit operation Statement Ladder Control system list diagram flowchart I 4.0 I 4.1 KC 150 I 4.0 I 4.1 I 4.1 KC 150 binary KC 150 16 bits...
Page 127 Programming Examples in the STL, LAD and CSF Methods of Representation Counter operations (continued) Count up STEP 5 representation Logical/circuit diagram Statement Ladder Control system list diagram flowchart I 4.1 I 4.1 CU C I 4.1 binary 16 bits The value of the addressed counter is incremented by "1"...
Page 128 Programming Examples in the STL, LAD and CSF Methods of Representation Counter operations (continued) Count down STEP 5 representation Logical/circuit diagram Statement Ladder Control system list diagram flowchart I 4.0 I 4.0 CD C R S CI I 4.0 binary 16 bits The value of the addressed counter is decremented by 1 to a maximum counter value of 0.
Page 129 Programming Examples in the STL, LAD and CSF Methods of Representation Comparison operations Compare for equal to STEP 5 representation Logical/circuit diagram Statement Ladder Control system list diagram flowchart I B19 IB19 IB20 IB20 IB19 IB19 Q 3.0 ! = F IB20 IB20 Q 3.0...
Page 130 Programming Examples in the STL, LAD and CSF Methods of Representation Comparison operations (continued) Compare for not equal to STEP 5 representation Logical/circuit diagram Statement Ladder Control system list diagram flowchart I B21 IB21 IB21 IB21 > < > < Q 3.1 >...
Page 131: Supplementary Operations
Supplementary Operations 3.5.3 Supplementary Operations You can use the supplementary operations set on the programmer only in function blocks (FB and FX). This means that the total operations set for function blocks consists of the basic operations and the supplementary operations. The system operations also belong to the supplementary functions.
Page 132: Binary Logic Operations
Supplementary Operations Binary logic operations Table 3-11 Binary logic operations with formal operands Operation Operand Function AND operation, scan a formal operand for signal state ’1’ AND operation, scan a formal operand for signal state ’0’ OR operation, scan a formal operand for signal state ’1’ OR operation, scan a formal operand for signal state ’0’...
Page 133: Bit Test Operations
Supplementary Operations Bit test operations Table 3-13 Bit test operations Operation Operand Function Scan for signal state "1" 0.0 to 127.7 of an input (PII) Q 0.0 to 127.7 of an output (PIQ) F 0.0 to 255.7 of a flag D 0.0 to 255.15 of a data word bit T 0.0 to 255.15...
Page 134: Set/Reset Operations
Supplementary Operations Set/reset operations Table 3-14 Set/reset operations with formal operands Operation Operand Function Set a formal operand (binary) Reset a formal operand (binary) Reset a formal operand (digital) for timers and counters Assign the value of the RLO to a formal operand Insert formal operand Inputs, outputs and F flags addressed in binary...
Page 135: Timer And Counter Operations
Supplementary Operations Timer and counter operations Table 3-16 Timer and counter operations with formal operands Operation Operand Function Start timer specified by the formal operand as a pulse with the value stored in ACCU-1-L (parameter type T). Start timer specified by the formal operand as ON delay with the value stored in ACCU-1-L (parameter type T).
Page 136 Supplementary Operations Examples Function block call Program in the Program executed function block FB 203 NAME :EXAMPLE1 ANNA : I 10.3 =ANNA I 10.3 BERT : T 17 010.2 KT 010.2 JOHN : Q 18.4 :SSU =BERT T 17 =BERT T 17 =JOHN Q 18.4...
Page 137: Load And Transfer Operations
Supplementary Operations Load and transfer operations Table 3-17 Load and transfer operations with formal operands Operation Operand Function Load a formal operand: The value of the operand specified as a formal operand is loaded into the ACCU (parameter type: I, T, C, Q; data type: BY, W, D). LCD = Load a formal operand in BCD code: The value of the timer or counter specified as a formal operand is...
Page 138: Table 3-18 Load And Transfer Operations With Special Operands
Supplementary Operations Table 3-18 Load and transfer operations with special operands Operation Operand Function 0 to 255 Load a word from the interface data area into ACCU 1 (RI area) 0 to 255 Load a word from the extended interface area into ACCU 1 (RJ area) 0 to 255 Load a word from the system data area...
Page 139: Table 3-19 Arithmetic Operation Ent
Supplementary Operations Arithmetic operations Table 3-19 Arithmetic operation ENT Operation Operand Function – This causes a stack lift into ACCUs 3 and 4: <ACCU 4> := <ACCU 3> <ACCU 3> := <ACCU 2> <ACCU 2> := <ACCU 2> <ACCU 1> := <ACCU 1> ACCUs 1 and 2 are not changed.
Page 140: Table 3-20 Supplementary Arithmetic Operations
Supplementary Operations Table 3-20 Supplementary arithmetic operations Operation Operand Function S ADD -128 to Add a byte constant (fixed point) to ACCU-1-L (includes +127 sign change)/the condition code in CC 0, CC 1, OV and OS are not affected! – ACCU-1-H and ACCUs 2 to 4 remain unchanged.
Page 141: Executive Operations
Executive Operations 3.5.4 Executive Operations The executive operations also include system operations. Caution System operations should only be used with great care and then only by experienced programmers familiar with the system. System operations are indicated in the table by Jump operations When you use the supplementary jump operations, you indicate the jump destination for unconditional jumps symbolically.
Page 142 Executive Operations Operation Operand Function Table 3-21 continued: JN = addr Jump if result is not 0 : the jump is executed only if CC1 (addr = symbolic is not equal to CC0. address with The RLO is not changed. maximum JP = 4 characters)
Page 143: Table 3-22 Shift Operations
Executive Operations Shift operations Table 3-22 Shift operations Operation Operand Function (operation with ACCU 1) 0 to 15 Shift a word to the left (vacant positions to the right are padded with zeros) 0 to 15 Shift a word to the right (vacant position to the left are padded with zeros) 0 to 32 Shift a double word to the left (vacant positions...
Page 144 Executive Operations Examples 1. You want to shift the contents of data word DW 52 four bits to the left and write them to data word DW 53. STEP 5 program: Contents of the data words: DW 52 KH = 14AF :SLW 4 DW 53 KH = 4AF0...
Page 145: Table 3-23 Conversion Operations
Executive Operations Conversion operations Table 3-23 Conversion operations Operation Function Form the 1’s complement of ACCU-1-L (16 bits) Form the 2’s complement of ACCU-1-L (16 bits) Form the 2’s complement of ACCU 1 (32 bits) Convert a fixed point number (16 bits) from BCD to binary Convert a fixed point number (16 bits) from binary to BCD Convert a double word (32 bits) from BCD to binary Convert a double word (32 bits) from binary to BCD...
Page 146 Executive Operations The value in ACCU 1 (bits 0 to 31) is interpreted as a BCD number. After the conversion, ACCU 1 contains a 32-bit fixed point number. The value in ACCU 1 (bits 0 to 31) is interpreted as a 32-bit fixed point number.
Page 147: Conversion Examples
Executive Operations This conversion algorithm produces the following result classes: • • Floating point numbers ≥ 0 or ≤ -1 result in the next lower number. • • Floating point numbers < 0 and > -1 result in the value ’0’. Conversion examples Floating point number 32-bit fixed point number...
Page 148: Table 3-24 Decrement/Increment Operation
Executive Operations Decrement/ increment Table 3-24 Decrement/increment operation Operation Operand Function 1 to 255 Decrement the low byte (bits 0 to 7) of ACCU-1-L by the value of the operand 1 to 255 Increment the low byte (bits 0 to 7) of ACCU-1-L by the value of the operand The contents of the low byte of ACCU-1-L are decremented or incremented by the number specified as the operand without a carry.
Page 149 Executive Operations Operation Operand Function Table 3-25 continued: S BI Indirect processing of a formal operand: execute an operation whose operation code is stored in a formal operand. The number of the formal operand must be stored in ACCU 1. Execute an operation whose operation code 60 to 63 is stored in the system data area (RS = free...
Page 150 Executive Operations Examples of DO operations DO DW/DO FW Operand substitution Using the statements "DO DW" and "DO FW" you can access data with a substitution, e.g. in a program loop. The substituted access consists of the statement DO DW/DO FW followed immediately by one of the STEP 5 operations listed above.
Page 151 Executive Operations Examples of operand substitution continued: Jump distributor for subroutine techniques: FW 5 =M001 Contents of flag word FW 5: =M002 Jump =M003 jump distance ± distance =M004 (maximum 127) =M005 M001 :BEU M002 Advantage: all program sections are :BEU contained in block.
Page 152 Executive Operations Parameter word for F flags Bit no. 11 10 no significance Bit address Byte address from 0 to 255 from 0 to 7 Parameter word for S flags Bit no. 15 14 12 11 0 Bit address Byte address from 0 to 4095 from 0 to 7 Parameter word for timers and counters Bit no.
Page 153 Executive Operations Example of DI operation In function block FB 1, STEP 5 operations are executed whose operation codes were transferred by a calling block as formal operands FW 10, FW 12 and FW 14. Which of the operation codes is executed is written by the calling block FW 16 as a consecutive number in flag word The result of the executed operation is then entered in ACCU 1 and is...
Page 154: Table 3-26 I/O Operations
Executive Operations I/O operations Table 3-26 I/O operations Operation Operand Function Disable process interrupt servicing (via IB 0) (not for system interrupts!) Enable process interrupt servicing (via IB 0) (not for system interrupts!) Disable addressing error Enable addressing error Disable command output: PIQ is no longer influenced by the operations S Q, R Q, = Q, T PY and T PW.
Page 155: Table 3-28 Meaning Of The Abbreviations In Uamw
Executive Operations SIM/LIM – set/read interrupt The interrupt mask "masks" interrupts in the interrupt condition code condition code mask (UAMW) word until the end of the cycle, i.e. all interrupts remain pending, but the program is not interrupted by them. Bit in the interrupt condition code mask = 0: interrupt disabled Bit in the interrupt condition code mask = 1: interrupt enabled Meaning of the bits in UAMW-H or ACCU-1-H:...
Page 156 Executive Operations Abbrev. Meaning Table 3-28 continued: Low word No block No data block Soft stop TLAF Transfer/load error Substitution error STUEB BSTACK overflow STUEU ISTACK overflow Power failure Timed interrupt (delayed interrupt, clock-controlled interrupt Timeout Addressing error PARE Parity error Cycle time error STOP Mode selector switched to STOP...
Page 157: Semaphore Operations
Semaphore Operations 3.5.5 Semaphore Operations If two or more CPUs in one programmable controller (see Chapter 10) require access to the same global memory area (peripherals, CPs, IPs), there is a danger that one CPU will overwrite the data of another CPU or that one CPU could read invalid intermediate data statuses of another CPU and misinterpret them.
Page 158: Fig. 3-8 Coordination Of Access To The Global Memory
Semaphore Operations Effect of SED/SEE The CPU that executes the operation SED xx (disable semaphore) accesses a specific byte in the coordinator (provided that no other CPU has access to that byte already). Once a CPU has reserved access, the other CPUs can no longer access the memory area protected by the semaphore (numbers 0 to 31).
Page 159 Semaphore Operations Before disabling or enabling a particular semaphore, the SED and SEE operations scan the status of the semaphore. The condition codes CC 0 and CC 1 are affected as follows: CC 1 CC 0 Evaluation Significance Semaphore was disabled by another CPU and cannot be disabled/enabled.
Page 160: Main Program
Semaphore Operations Application example for semaphores Tasks: Four CPUs are plugged into an S5-155U. They output status messages to a status signalling device via a common memory area of the O peripherals (OW 6). A CPU must output each status message for 10 seconds. Only after a 10 second output can a new message be output from the same CPU or a different CPU overwrite the first message.
Page 161 Semaphore Operations Semaphore application example continued: FB 1 F 10.0 =M001 If no message is active, :BEC KH 2222 generate message and FW 12 F 10.0 F 10.0 set "MESSAGE" flag. M001 :JU FB10 Call "REPORT" FB NAME :REPORT FB 10 NAME :REPORT F 10.1 If no semaphore is disabled,...
Page 162 Semaphore Operations Semaphore application example continued: FB 100 NAME :SEMADIS :SED 10 Disable semaphore no. 10 =M001 F 10.1 If the semaphore is disabled successfully, F 10.1 set "SEMAPHORE-DISABLED" flag. M001 :BE FB 110 NAME: MSGOUT FW12 Transmit a message OW 6 to the peripherals F 10.3...
Page 163: Operating Statuses And Program Execution Levels
Operating Statuses and Program Execution Levels Contents of Chapter 4 Introduction and Overview..........4 - 4 Program Execution Levels .
Page 164 4.5.4 Interrupt-Driven Program Execution ........4 - 45 PROCESS INTERRUPTS via input byte IB 0 .
Page 165 Operating Statuses and Program Execution Levels This chapter provides an overview of the operating statuses and program execution levels of the CPU 948. It informs you in detail about various types of start-up and the organization blocks associated with them, in which you can program your own sequences for various situations when restarting.
Page 166: Introduction And Overview
Introduction and Overview Introduction and Overview With the CPU 948, there are four operating statuses, as follows: • • START-UP mode • • RUN mode • • SOFT STOP mode • • HARD STOP mode In the START-UP and RUN modes, certain events can occur to which the system program must react.
Page 167: Table 4-1 Meaning Of The Leds "Run" , "Stop" And "Sysfault
Introduction and Overview Display of the modes by Various LEDs on the front panel of the CPU indicate its current mode. (LEDs) The following table shows the relationship between the STOP and RUN LEDs and the corresponding mode. These displays are supplemented by further LEDs (BASP, ADF, QVZ, ZYK, INIT).
Page 168 Introduction and Overview Signalling and error LEDs "BASP" LED This indicates whether the S5 bus signal BASP (disable command output) is active: in the single processor mode, BASP is deactivated by the CPU when it enters the status RUN and activated at the transition to the STOP mode.
Page 169: Program Execution Levels
Program Execution Levels Program Execution Levels Fig. 4-2 provides you with an overview of the program processing levels in the various modes. The explanations of the abbreviations are on the following page. Status Error levels Program execution levels Preparing for communication COMMUNICATION START-UP TRAF...
Page 170 Program Execution Levels Table 4-2 Program execution levels Level Meaning Priority Error levels WEFES/WEFEH Collision of timed interrupts Each error handling Cycle error routine has the highest Substitution error priority. If an error TRAF Transfer/load error occurs, the Addressing error corresponding error Timeout level is nested in...
Page 171 Program Execution Levels Nesting other levels When an event occurs, which requires higher priority processing, the current level is interrupted by the system program and the higher priority level is activated. This occurs in the following situations: • • at error levels: always at operation boundaries, •...
Page 172 Program Execution Levels Sub-levels The TIMED INTERRUPTS level contains several sub-levels to which a specific program (OB) is assigned. Within the TIMED INTERRUPTS level, the sub-levels have their own priority (refer to the following table). TIMED INTERRUPTS level Sub-level Priority Delayed interrupt cyclic timed interrupt, shortest period ascending...
Page 173: Fig. 4-3 Principle Of Changing Level And The Istack
Program Execution Levels Example of "Interrupt stack": WARM RESTART Stop switch STOP Depth 1 Depth 2 CYCLE START-UP Depth 3 CYCLE CYCLE Depth 4 ISTACK = Image of the interrupted levels Fig. 4-3 Principle of changing level and the ISTACK Example of "Interrupting a basic level with interruptability at block boundaries":...
Page 174: Stop Mode
STOP Mode STOP Mode The CPU 948 has two different STOP modes, the "hard" STOP and the "soft" STOP (= CPU capable of communication). 4.3.1 SOFT STOP The SOFT STOP mode has the following features: The CPU can communicate: the system program calls organization block OB 38 once after POWER UP (COMMUNICATION START-UP level in SOFT STOP) and then calls OB 39 (COMMUNICATION level in SOFT STOP).
Page 175 STOP Mode Monitoring the execution The execution time of OB 39 is monitored by the system program. If time of OB 39 execution takes longer than 2.55 seconds (fixed value), the system program detects a cycle time error; it then calls the error OB, OB 26, and then processes OB 39 again from the beginning.
Page 176: Fig. 4-4 Program Execution After Power Up
STOP Mode OB 38/OB 39 call Figures 4-4 and 4-5 illustrate the principle of the OB 38 and OB 39 calls. Initial status: RUN Initial status: SOFT STOP POWER DOWN/POWER UP POWER DOWN/POWER UP OB 38 OB 38 Communication Communication start-up start-up OB 39...
Page 177 STOP Mode LED displays The SOFT STOP status can be recognized by the LEDs on the front panel of the CPU as follows: Status STOP on (continuous or flashing light) SYSFAULT BASP on (except in test mode with multiprocessor mode or with PG function "force outputs") The STOP LED signals the possible causes of the current stop status, as follows:...
Page 178: Hard Stop
STOP Mode Exiting the SOFT STOP status The SOFT STOP status can be exited as follows: a) by selecting a restart (refer to Section 4.4), b) by an OVERALL RESET followed by a COLD RESTART. 4.3.2 HARD STOP If the system program can no longer be executed properly, the CPU changes to the HARD STOP mode to ensure a safe mode in this situation.
Page 179: Overall Reset
An OVERALL RESET is also requested if a CPU or system error occurs. You can recognize this error because the request occurs again following the OVERALL RESET. In this case, contact your local Siemens representative. Operator request With the steps outlined in the table, you can also request an OVERALL RESET (the operating elements are on the front panel of the CPU - Fig.
Page 180: Overall Reset
STOP Mode Performing an Regardless of whether you or the system program requested the OVERALL RESET OVERALL RESET, you perform the OVERALL RESET as follows (initial status: STOP LED flashing quickly): OVERALL RESET using control elements on the CPU Action Result Hold the reset switch in the An OVERALL RESET is...
Page 181: Start-Up Mode
START-UP Mode START-UP Mode The START-UP mode has the following features: Mode change START-UP is the transition from the STOP mode to the RUN mode. Start-up types The CPU 948 has the following start-up modes: COLD RESTART ( manual or automatic) WARM RESTART (manual or automatic) (You can select the type of start-up with operating elements and by assigning parameters in DX 0)
Page 182: Manual And Automatic Cold Restart
START-UP Mode 4.4.1 MANUAL and AUTOMATIC COLD RESTART When is a COLD RESTART A COLD RESTART is always permitted provided the system is not permitted? requesting an OVERALL RESET. When is a COLD RESTART A COLD RESTART is necessary after the following: necessary? OVERALL RESET, loading the user memory with the user program while the CPU...
Page 183: Manual And Automatic Warm Restart
START-UP Mode Aborting a cold restart You can abort an active COLD RESTART only by changing the mode selector to STOP or by switching off the power. If you abort a COLD RESTART you must repeat it. 4.4.2 MANUAL and AUTOMATIC WARM RESTART When is a WARM RESTART...
Page 184 START-UP Mode MANUAL WARM RESTART You trigger a MANUAL WARM RESTART as follows: • • using the control elements of the CPU: initial state: the reset switch is in the mid setting change the mode selector from STOP to RUN (refer to Fig. 4-1) •...
Page 185 START-UP Mode Note With a WARM RESTART note the following special situation: The CPU is currently processing an error OB (e.g. due to an addressing error ADF) and then changes to the STOP mode owing to POWER OFF, HALT, stop switch or PG-STP. Following this, a MANUAL or AUTOMATIC WARM RESTART is executed.
Page 186: Comparison Between Cold Restart And Warm Restart
START-UP Mode 4.4.3 Comparison between The following table contains a comparison of the start-up types COLD RESTART and COLD RESTART and WARM RESTART.. WARM RESTART Table 4-3 Characteristics of COLD RESTART and WARM RESTART COLD RESTART WARM RESTART Manual Mode selector from position STOP to RUN Mode selector from position STOP to triggering: and reset switch set to RESET position...
Page 187: Retentive Cold Restart
START-UP Mode COLD RESTART WARM RESTART Table 4-3 continued: System Set system parameters according to the DX 0 not evaluated program settings in DX 0 activities Call user interface OB 20 Call user interface OB 21/22 (continued): (if it exists) (if they exist) Synchronize start-up in multiprocessor Synchronize start-up in multiprocessor...
Page 188: Comparison Of Cold Restart And Retentive Cold Restart
START-UP Mode 4.4.5 Comparison of The following table shows the differences between a COLD COLD RESTART and RESTART and RETENTIVE COLD RESTART. RETENTIVE COLD RESTART Table 4-4 Differences between a cold restart and a RETENTIVE COLD RESTART COLD RESTART RETENTIVE COLD RESTART Manual Mode selector from position STOP to Mode selector from position STOP to...
Page 189: User Interfaces For Start-Up
START-UP Mode COLD RESTART RETENTIVE COLD RESTART System Table 4-4 continued: program Set system parameters according to default No evaluation of DX 0 activities in DX 0 (continued) Call user interface OB 20 Call user interface OB 21/22 (if it exists) (if it exists) Synchronize start-up in multiprocessor Synchronize start-up in multiprocessor...
Page 190 START-UP Mode OB 21 If the CPU performs a MANUAL COLD RESTART or RETENTIVE MANUAL COLD RESTART, the system program calls OB 21 once. Here, you can store a STEP 5 program which executes preliminary steps for a warm restart of the cyclic program. MANUAL WARM RESTART With a MANUAL WARM RESTART, the cyclic program is continued with the next statement following the point at which it was...
Page 191 START-UP Mode OB 22 When the CPU executes an AUTOMATIC WARM RESTART or AUTOMATIC RETENTIVE COLD RESTART, the system program calls OB 22 once. Here, you can store a STEP 5 program which executes preliminary steps (generally following a power failure) for a warm restart of cyclic program execution.
Page 192: Extended Automatic Warm Restart With The Cpu 948 (Hot Restart)
START-UP Mode 4.4.7 Extended AUTOMATIC The "HOT RESTART" mode specified in the IEC 1131 standard, part WARM RESTART with the 1 is also possible in the CPU 948. The "HOT RESTART" is a warm CPU 948 (HOT RESTART) restart controlled by a battery-backed clock (according to IEC 1131). The clock monitors the time between switching off and switching on the power supply for the CPU.
Page 193: Interruptions During Start-Up
START-UP Mode 4.4.8 Interruptions during A start-up program can be interrupted by the following: START-UP • • power failure in the central controller (NAU) or in the expansion unit (PEU), • • stop switch, stop command, HALT or PG-STP • • program errors or device faults (refer to Section 5.5). Basic rules for an interrupted The following basic rules apply to the start-up response of the START-UP...
Page 194 START-UP Mode Response of the CPU on the If the start-up execution is interrupted by a power failure or the PEU return of power after power signal, the response of the CPU when power returns depends on the failure or PEU signal set and interrupted mode.
Page 195: Run Mode
RUN Mode When the CPU has executed a START-UP (and only then) it changes to the RUN mode. This mode is characterized by the following features: Execution of the user program The user program in OB 1 is executed cyclically and additional interrupt-driven program sections can be nested in it.
Page 196: Cyclic Program Execution
4.5.1 Cyclic Program Execution With programmable controllers, cyclic program execution (program execution level CYCLE) is the main mode. Triggering If the CPU has completed the start-up program without errors, it then begins cyclic program execution. Principle The principle of cyclic program execution (system activities): From start-up Tr igger cycle m onitor ing tim e Update IPC input flags...
Page 197 User interface OB 1 During cyclic program execution, organization block OB 1 is called regularly as the user interface. The STEP 5 user program in OB 1 is processed from the beginning with the block calls you have programmed. After the system activities, the CPU starts again from the beginning with the first STEP 5 statement in OB 1.
Page 198: Interrupt-Driven Program Execution
4.5.2 Specifying Time and With time and interrupt-driven program execution, various types are Interrupt-Driven Program available which can at present only be used as alternatives (i.e. not Execution mixed). You decide which of the types of processing you want to use by setting the parameter in data block DX 0 (refer to Chapter 7).
Page 199: Time-Controlled Program Execution
4.5.3 Time-Controlled Program This type of program execution includes the delayed interrupt, the Execution time-controlled interrupt and cyclic timed interrupts. All these interrupts are time-controlled. Time-controlled program execution uses the TIMED INTERRUPTS level. Delayed interrupts Triggered once after a selected delay time in the millisecond range. Organization block OB 6 is called with this interrupt.
Page 200: Delayed Interrupt
Delayed interrupt With the delayed interrupt of the CPU 948, small time intervals with a resolution of 1 ms can be set. Once the selected time has elapsed, the system program calls OB 6 once. Resolution The delayed interrupt is generated by calling the special function organization block OB 153 (refer to Section 6.14).
Page 201: Clock-Controlled Interrupt
• • If you generate a new delayed interrupt, i.e. call OB 153 with new parameters, a previously set delayed interrupt is cancelled. A delayed interrupt currently being processed is continued. This means that only one delayed interrupt is valid at any one time. •...
Page 202 Interruptions Owing to the default, the TIMED INTERRUPTS layer has the highest priority of the basic layers (can be modified in DX 0). In time-controlled program execution, the execution of clock-controlled interrupts has the lowest priority. This can therefore be interrupted by the processing of a delayed interrupt or a cyclic timed interrupt.
Page 203: Cyclic Timed Interrupts
Cyclic timed interrupts On the CPU 948, you can process 9 different time-controlled programs, each being called at a different cyclic interval. Triggering The basic clock pulse for timed interrupt processing is set to 100 ms. Using a special parameter in data block DX 0, you can adjust this in 10 ms where: 01H ≤...
Page 204 User interfaces When a timed interrupt occurs, the corresponding organization block OB 10 to OB 18 is called as the user interface at the next block boundary (or operation boundary). For example, you would program the routine to be inserted in cyclic program execution every 100 ms in OB 10 (default).
Page 205: Table 4-6 Timed Interrupt Collision Ids: Meaning Of The Bits In Accu-1-L
Collision of timed interrupts In the CPU 948 there are two different types of collisions of timed interrupts: Type of error/cause ISTACK ID Reaction of the CPU Timed interrupt queue overflow: In the "ISTACK output" of The system program calls there are more than three the programmer, the error ID OB 33 as the user interface.
Page 206 Bit number Meaning Queue overflow in timed interrupt period 6 (OB 15 has been called again before the prior call was completely executed). Queue overflow in timed interrupt period 7 (OB 16 has been called again before the prior call was completely executed). Queue overflow in timed interrupt period 8 (OB 17 has been called again before the prior call was completely executed).
Page 207: Interrupt-Driven Program Execution
4.5.4 Interrupt-Driven Program Depending on the selected mode, two different types of interrupt-driven Execution program execution are possible with the CPU 948: • • PROCESS INTERRUPTS via input byte IB 0 (max. 8 interrupts), • • INTERRUPTS via signal lines of the S5 bus (max. 4 interrupts). PROCESS INTERRUPTS via To service process interrupts, the default "process interrupts via IB 0 = input byte IB 0...
Page 208 In the organization blocks OB 2 to OB 9, you program the part of your STEP 5 program to be executed when one of the process interrupts occurs indicated by a bit in input byte IB 0. If the corresponding OB is not loaded, program execution is not interrupted.
Page 209: Interrupts Via Signal Lines Of The S5 Bus
INTERRUPTS via signal Interrupt-driven program execution means that an S5 bus signal from lines of the S5 bus an I/O module with interrupt capability (e.g. digital inputs, IPs, CPs) causes the CPU to interrupt program execution and to process a specific section of program.
Page 210: Table 4-8 User Interfaces For Interrupts
Triggering The active state of an interrupt line on the S5 bus triggers the interrupt. The interrupt signal is level-triggered (low level). To acknowledge the interrupt, please refer to the operating instructions for the module which triggers the interrupt. User interfaces If an interrupt occurs, one of the OBs listed in the following table is OB 2 to OB 5 called as the user interface.
Page 211: Disabling Interrupt-Driven Processing
When an interrupt OB has been completely executed and there are further interrupts pending, the system program calls and processes the OB with the next lowest priority. The INTERRUPTS processing level is only exited when every active signal state (low level) of an interrupt line on the S5 bus has been dealt with and the corresponding OB has been completely processed.
Page 212: Reaction Time
• • Program the section that must not be interrupted in an interrupt OB Interrupts at operation boundaries and assign the highest priority to it. • • Use the special function OB 122. With this, you can disable interrupts and timed interrupts (refer to Section 6.3). •...
Page 213 Interrupt and Error Diagnostics Contents of Chapter 5 Frequent Errors in the User Program......... 5 - 4 Error Information .
Page 214: Interrupt And Error Diagnostics
Interrupt and Error Diagnostics This chapter explains how to avoid errors when planning and programming your STEP 5 programs. You will see what help you can get from the system program for diagnosing and reacting to errors and which blocks you can use to program reactions to errors.
Page 215: Frequent Errors In The User Program
Frequent Errors in the User Program Frequent Errors in the User Program The system program can detect effects of errors in the user program, faulty operation of the CPU, or errors in the system program processing. The following list describes errors that occur most frequently during the start-up of the user program.
Page 216: Error Information
Error Information Error Information If an error occurs during system start-up or during cyclic processing of your program, the sources of information described in this section can help you to find the problem. This includes: • • LEDs on the front panel of the CPU •...
Page 217 Error Information PG online function OUTPUT You can get information about the status of the control bits and the ISTACK contents of the interrupt stack (ISTACK) by using die PG online function OUTPUT ISTACK. When the CPU goes into the STOP mode, the system program enters all the information it requires for a warm restart in the ISTACK.
Page 218 Error Information In the first line, the information shown below is available: Information Meaning BLOCK NO Type and number of the block that called the faulty block BLOCK ADDR Absolute start address of the calling block in the program memory RETURN ADDR Absolute address of the first STEP 5 operation of this block in the user memory.
Page 219: Procedure For Error Analysis
Procedure for Error Analysis Procedure for Error Analysis If the CPU is in an abnormal stop mode, make use of all the information available to analyze the error, as follows: Step Action Check the status of the STOP and SYS FAULT LEDs and the error LEDs on the front panel.
Page 220: Control Bits And Interrupt Stack
Control Bits and Interrupt Stack Control Bits and Interrupt Stack You can use the online functions PLC INFO and OUTPUT ISTACK to analyze the following: operating status, characteristics of the CPU, characteristics of the user program, possible causes of errors and interruptions.
Page 221: Control Bits
Control Bits and Interrupt Stack 5.4.1 Control Bits When you display the ISTACK on your programmer, the status of the control bits is indicated on the first page (see Fig. 5-1). Note The ISTACK screen form shown in Fig. 5-1 reflects the PG software STEP 5/ST, Version 6.3 or STEP 5/MT Version 6.0 with the "Delta diskette CPU 948".
Page 222: Table 5-1 Meaning Of The Control Bits System Description
Control Bits and Interrupt Stack The following tables explain the meaning of the individual bits. Table 5-1 Meaning of the control bits SYSTEM DESCRIPTION SYSTEM DESCRIPTION Meaning E0VH Input byte IB 0 (process interrupts) exists, i.e. the digital input module addressed with ’0’ was plugged in during the last cold restart and the module acknowledged.
Page 223: Table 5-3 Meaning Of The Control Bits Start-Up Ids
Control Bits and Interrupt Stack STOP CAUSE (see RS 7) Meaning Table 5-2 continued: UPROG STOP mode caused by user program USYS STOP mode caused by system program (warm restart possible) UANL STOP mode caused by illegal start-up type AFEL STOP mode caused by errors in the start-up block SYSFHL STOP mode caused by system error (may be caused by user error, e.g.
Page 224: Table 5-4 Meaning Of The Control Bits Error Ids
Control Bits and Interrupt Stack Table 5-4 Meaning of the control bits ERROR IDS ERROR IDs Meaning QVZIN Timeout error in initialization PARIN Parity error in initialization BSTKF Wrong block ID BSTEF Wrong block delimiter UMCG Illegal memory card inserted MODUN Content of the memory card too large for the available internal user memory FE2S...
Page 225: Istack Content
Control Bits and Interrupt Stack 5.4.2 ISTACK Content If the CPU is in the stop state, you can display the content of the ISTACK on the screen after the control bit display by pressing the enter key. When the CPU goes into the STOP mode, the system program enters all the information it needs in this ISTACK for a warm restart.
Page 226: Table 5-5 Meaning Of The Istack Ids For Errors
Control Bits and Interrupt Stack Explanation of the ISTACK screen DEPTH Information level of the ISTACK when more than one error has occurred: DEPTH 01 = last cause of stop to occur DEPTH 02 = next to last cause of stop to occur ..
Page 227 Control Bits and Interrupt Stack Information about the error ISTACK ID Meaning Table 5-5 continued DB-NO. Number of the data block currently opened OB-NO. Block type and number of the last calling (depending on type block OB, PB ...) REL-SAC Relative STEP address counter: contains the relative address (related to the block start address) of the next...
Page 228: Table 5-6 Istack Ids Cause Of Interruption
Control Bits and Interrupt Stack CONDITION CODE see Section 3.5 CAUSE OF INTERR. The following abbreviations (ISTACK IDs) indicate the most important causes of interruptions. Table 5-6 ISTACK IDs CAUSE OF INTERRUPTION CAUSE OF INTERR. ISTACK Meaning (called error OB) Called block not loaded (OB 19) Opened data block not loaded (OB 19) TRAF...
Page 229: Warm Restart
Control Bits and Interrupt Stack CAUSE OF INTERR. ISTACK Meaning (called error OB) Table 5-6 continued: WEFEH Collision of timed interrupts caused by the hardware clock (OB 33): timed interrupt clock was masked (ignored) for too long I/Os not ready = power failure in expansion unit: After a statically pending PEU signal is removed (expansion unit is switched on), the system program always calls OB 22 (AUTOMATIC...
Page 230: Example Of Error Diagnosis Using The Istack
Control Bits and Interrupt Stack 5.4.3 Example of Error Diagnosis using the ISTACK Fig. 5-3 illustrates the structure of the ISTACK in conjunction with the interruptions that have occurred. OB 1 - The program execution level CYCLE ( ) is interrupted by an interrupt. - Following this, the program processing level interrupt is activated and OB 3 called.
Page 231: Error Handling Using Organization Blocks
Error Handling Using Organization Blocks Error Handling Using Organization Blocks When the system program detects an error, it calls the appropriate organization block to handle it. You can determine further operation of the CPU by programming the appropriate organization block. Therefore, the CPU can do one of the following: •...
Page 232 Error Handling Using Organization Blocks Cause of error Organization Reaction of CPU block called if OB is not programmed Table 5-7 continued: Load and transfer error (TRAF) OB 32 STOP Collision of timed interrupts: OB 33 a) queue overflow (control bit WEFES) STOP b) timed interrupt clock was masked (ignored) for too long none...
Page 233 Error Handling Using Organization Blocks Interruptions during After the system program calls the appropriate organization block, the processing of error user program in that block is processed. organization blocks If another error occurs while that organization block is being processed, the program is interrupted at the next operation boundary and the appropriate organization block is called, just as in cyclic program processing.
Page 234: Causes Of Error And Reactions Of The Cpu
Causes of Error and Reactions of the CPU Causes of Error and Reactions of the CPU Specific events can interrupt cyclic, time-controlled, or interrupt- driven program processing at operation boundaries when the CPU is in the RUN mode. During initialization and also in the RESTART mode, interruptions can stop the start-up program and put the CPU into the STOP mode.
Page 235: Ob 19: Calling A Logic Block That Is Not Loaded (Kb)
Causes of Error and Reactions of the CPU 5.6.1 OB 19: Calling a Logic If your program jumps to a block that does not exist, the system Block That Is Not Loaded program detects an error. This applies to all logic blocks and also for (KB) conditional and unconditional calls.
Page 236: Ob 23/24, Ob 28/29:Timeout Error (Qvz)
Causes of Error and Reactions of the CPU 5.6.3 OB 23/24, OB 28/29: A timeout error occurs when an addressable memory area does not Timeout Error (QVZ) respond to write or read accesses with the ready signal ("RDY") within a specific time after being addressed. This time is monitored by the hardware.
Page 237: Ob 25: Addressing Error (Adf)
Causes of Error and Reactions of the CPU OB 28 Cause of error Reaction to error Timeout error at input byte IB 0 If OB 28 is not loaded, the CPU (process interrupts) changes to the STOP mode. OB 29 Cause of error Reaction to error Timeout error of the distributed...
Page 238: Ob 26: Cycle Time Exceeded Error (Zyk)
Causes of Error and Reactions of the CPU When an addressing error occurs, the system program interrupts further processing of the user program and calls organization block OB 25. After running the program contained in OB 25, the program is resumed at the next operation.
Page 239: Ob 27: (Substitution Error Suf)
Causes of Error and Reactions of the CPU 5.6.6 OB 27: (Substitution If an operation with a formal operand is to be carried out in a function Error SUF) block, the CPU replaces (substitutes) this formal operand with the actual operand in the block when the block is called during user program processing.
Page 240: Ob 32: Load And Transfer Error (Traf)
Causes of Error and Reactions of the CPU Error address If a parity error or timeout occurs, the address that caused the error can be read out of the system data area (refer to Chapter 8): Contents Address PARE error address high E F046H PARE error address low E F047H...
Page 241: Ob 33: Collision Of Timed Interrupts Error (Wefes/Wefeh)
Causes of Error and Reactions of the CPU 5.6.9 OB 33: Collision of Timed Time-controlled program processing (timed interrupts) is handled by Interrupts Error organization blocks OB 6, OB 9 and OB 10 to OB 18. (WEFES/WEFEH) The following types of timed errors can occur on the CPU 948: Queue overflow Cause: Queue overflow servicing timed interrupts:...
Page 242 Causes of Error and Reactions of the CPU Reaction: The system program calls OB 33 as user interface, if this is loaded. Here, you can program the reaction to this state. If OB 33 is not loaded, the CPU continues processing the program. PG display with "OUTPUT ISTACK": The bit WEFEH is marked in the control bits.
Page 243: Ob 34: Error With G Db/Gx Dx (Fedbx)
Causes of Error and Reactions of the CPU 5.6.10 OB 34: Error with G DB/GX DX (FEDBX) Causes: • • with the operation G DB/GX DX, an illegal block number was specified (number of a reserved block, number > 255), •...
Page 244: Ob 36: Error In Self-Test
Causes of Error and Reactions of the CPU Structure of the error information in ACCU 1 24 23 18 15 ACCU 1 Error number 1 Error number 2 Error number 3 = ’0’, means no error entry = ’1’, means one or more errors entered = ’0’, means no error overflow (maximum three entries) = ‘1‘, means error overflow (more than three entries) = ’0’, means no BREAK on the interface...
Page 245: Self-Test
Self-Test Self-Test 5.7.1 Overview The CPU 948 contains integrated self-test routines in the system program. Activating/deactivating You can activate or deactivate the functions of the self-test using bits in system data RS 137. Time slice To reduce the cycle load caused by the self-test in the RUN mode, only part of the self-test is carried out within a cycle (time slice).
Page 246: Description Of The Test Functions
Self-Test 5.7.2 Description of the Test Functions Testing the user memory (During OVERALL RESET, without time slice) The user memory is tested during an OVERALL RESET. This test checks the user memory, the byte areas, the flags and process images. During the test, the whole area (including the byte areas) are written with a test pattern and then checked to make sure that they match.
Page 247 Self-Test Testing cycle time monitoring (During START-UP, without time slice) With this function, the cycle time monitoring is checked during the start-up phase. The cycle monitoring time is set to the minimum value (20 ms) and then a program loop started until the cycle error occurs. Testing the address lines (Cyclically in RUN mode, with time slice) In this test, wire breaks and short circuits on the address lines are...
Page 248: Settings
Self-Test 5.7.3 Settings Calculating and setting the The processing time for the self-functions is distributed on time slices number of time slices which are called once per cycle. The number of time slices can be selected. This means that you can increase the time required for the self-test functions per cycle.
Page 249: Error Handling
Self-Test Assignment of system data word RS 137 Test function Bit no. Check the code of the system program Check the code of the STEP 5 logic blocks in the user memory Check the address lines Check the clock Check the BASP signal Check the cycle time monitoring Test the user memory The bit numbers not listed in the table are not used.
Page 250 Self-Test Error information Testing the user memory System data word Error information RS 75 error no. 640CH testing the word memory error no. 650CH testing the byte memory RS 76 test pattern in which the error occurred RS 77 incorrect address, high RS 78 incorrect address, low Testing the BASP signal...
Page 251 Self-Test Testing the address lines System data word Error information RS 75 error no. 630BH RS 76 FFFFH RS 77 incorrect address, high RS 78 incorrect address, low Testing the system program code System data word Error information RS 75 error no.
Page 252: Integrated Special Functions
Integrated Special Functions Contents of Chapter 6 Introduction............. 6 - 4 OB121: Set/Read System Time .
Page 253 6.17 OB 181: Test Data Blocks (DB/DX) ........6 - 57 6.18 OB 182: Copy Data Area .
Page 254 Integrated Special Functions The following chapter describes the special functions integrated in the system program, where you can use these functions and how to call and assign parameters to the special function OBs. You will also learn how to recognize errors in the execution of a special function and possible ways of handling them in the program.
Page 255: Introduction
Introduction Introduction The operating system of the CPU 948 provides you with special functions which you can call if necessary with a conditional (JC OB x) or an unconditional (JU OB x) block call. Organization blocks OB 100 to 255 are reserved for these special functions. These functions are known as integrated special functions, since they are a fixed part of the system program.
Page 256 Introduction Interfaces The following are available as interfaces to the special functions: • • Conditional/unconditional block call JC .. / JU .. Block call • • Parameters for defaults via ACCU 1 and possibly ACCU 2 and/or Parameters memory locations In the following description of the individual special functions, all the data required by the CPU to execute the special function correctly are listed under the term parameters.
Page 257: Error Handling
Introduction Error handling An error occurring in the execution of the active special function triggers a special error reaction in the system program. In terms of this error reaction by the system program, two groups of special functions can be distinguished. •...
Page 258: Ob 121: Set/Read System Time
OB 121: Set/Read System Time OB 121: Set/Read System Time Function With OB121 you can set or read the system time (date and time). This function is compatible with the CPU 946/947. Parameters 1. Data field Four words in the word-oriented memory area. With the "set system time"...
Page 259: Possible Errors
OB 121: Set/Read System Time Weekday: 0 to 6 for Mon to Sun Days x 1: 0 to 9 Days x 10: 0 to 3 Month x 1: 0 to 9 Month x 10: 0 to 1 Year x 1: 0 to 9 Year x 10: 0 to 9...
Page 260 OB 121: Set/Read System Time Examples Programming example for "set system time" FB 13 is programmed for the "set system time" function. The new values are transferred in data block DB 10 (data word DW 0 to DW 3). STEP 5 program: FB13 NAME :CLKWR...
Page 261 OB 121: Set/Read System Time Programming example for "read system time" FB 14 is programmed for the "read system time" function. The current values should be stored in data block DB 11 (data word DW 0 to DW 3). STEP 5 program: FB14 NAME :CLKRD...
Page 262: Ob 122: "Disable Interrupts" On/Off
OB 122: "Disable Interrupts" On/Off OB 122: "Disable Interrupts" On/Off A STEP 5 program can be interrupted at block boundaries or operation boundaries by programs at an execution level with a higher priority. The program execution levels with higher priority include the following: •...
Page 263: Table 6-3 Error Ids Of Ob 122 In Accu-1-L
OB 122: "Disable Interrupts" On/Off Result After correct and error-free processing, the system program enters the value ’0’ in ACCU-1-L. Note By calling OB 122, the RLO (undefined) is influenced. The BR register is not modified. To disable and enable processing interrupts, you can also use the STEP 5 operations IA and RA instead of OB 122.
Page 264: Ob 124: Delete Step 5 Blocks
OB 124: Delete STEP 5 Blocks OB 124: Delete STEP 5 Blocks Function With OB 24, you can delete any STEP 5 blocks (logic and data blocks) in the user memory. The deleted block is removed from the address list in DB 0. The gap in memory resulting from deleting a block is used again when new blocks are loaded.
Page 265 OB 124: Delete STEP 5 Blocks Possible errors and warnings If an error or warning occurs, the system program stops processing OB 124 and continues program execution at the next STEP 5 operation. It also sets the RLO to ’1’ and writes an ID to ACCU-1-LL (refer to Table 6-5).
Page 266: Table 6-5 Result Ids Of Ob 124 In Accu-1-Ll
OB 124: Delete STEP 5 Blocks IDs in ACCU-1-LL In ACCU-1-LL, the system program stores IDs about the processing result, with which the cause of a warning or error is specified in more detail. Bit no. Cause of error/warning The following group bits are fixed: Bit no.
Page 267: Ob 125: Generate Step 5 Blocks
OB 125: Generate STEP 5 Blocks OB 125: Generate STEP 5 Blocks Function With OB 125, you can generate any STEP 5 blocks (logic and data blocks) in the user memory. Generating logic blocks should, however, be left to specialists. The specified block is set up in the internal RAM with a block header and block body and entered in DB 0.
Page 268 OB 125: Generate STEP 5 Blocks Possible errors and warnings If an error occurs, the system program stops processing OB 125 and continues program execution at the next STEP 5 operation. It also sets the RLO to ’1’ and writes an ID to ACCU-1-LL (refer to Table 6-7). If the function is aborted with a warning, it may be possible to achieve correct execution of OB 125 by re-calling the special function (possibly several times).
Page 269: Table 6-7 Result Ids Of Ob 125 In Accu-1-Ll
OB 125: Generate STEP 5 Blocks IDs in ACCU-1LL In ACCU-1-LL, the system program stores IDs about the processing result, with which the cause of a warning or error is specified in more detail. Bit no. Cause of error/warning The following group bits are fixed: Bit no.
Page 270: Ob 126: Define, Transfer Process Images
OB 126: Define, Transfer Process Images OB 126: Define, Transfer Process Images Each time the cycle is run through, the system program updates the process image of the digital inputs and outputs and IPC flags. The inputs, outputs and IPC flags included in the process image are stored in system data block DB 1 (refer to Chapter 10).
Page 271: Block Number
OB 126: Define, Transfer Process Images Address list number Number of the address list for the additionally defined process image; permitted values: 1 to 4 Block type Type of data block containing the address list; permitted values: 1 = DB 2 = DX Block number Number of the data block containing the address list;...
Page 272: Table 6-8 Result Ids Of Ob 125 In Accu-1-Ll
OB 126: Define, Transfer Process Images Result After correct and error-free processing, the system program sets the RLO to ’0’ and enters a ’1’ in ACCU-1-LL. Note When processing OB 126, user interrupts are disabled: no interrupts come through. Calling OB 126 changes the contents of ACCU 1 to ACCU 4. The BR register is retained.
Page 273 OB 126: Define, Transfer Process Images Examples Creating the address list in DB 5 Using the function keys <input>, <scr form>, "block: DB 5" program a data block DB 5 on the PG with the following parameters: Digital inputs: 1, 2, Digital outputs: IPC input flags: 5, 6, 7,...
Page 274 OB 126: Define, Transfer Process Images Output the process image of the outputs The following STEP 5 program sequence can be located in any program execution level (in OB 1, in a timed interrupt OB or in a process interrupt OB etc.) and causes the process image of all outputs in address list 1 to be output.
Page 275: Ob 129: Battery State
OB 129: Battery State OB 129: Battery State Function With OB 129, you can check the state of the back-up battery with a STEP 5 program (OB 129 scans the BAU signal). Depending on the result, you could, for example, set a fault indicator (lamp). How the BAU signal is The power supply contains two back-up batteries, a lithium cell (MB formed...
Page 276: Ob 131: Delete Accus 1, 2, 3 And 4
OB 131: Delete ACCUs 1, 2, 3 and 4 Example With the following sequence of operations, you can check whether or not the battery is OK and if it is not, you can energize a lamp: OB 129 =BATL RLO = 1 -> battery run down :BEU BATL :SU 22.5...
Page 277: Ob 132/133: Roll-Up Accu/Roll-Down Accu
OB 132/133: Roll-Up ACCU/Roll-Down ACCU OB 132/133: Roll-Up ACCU/Roll-Down ACCU Function OB 132 and OB 133 roll the ACCU contents up or down: • • OB 132 (roll up) moves the contents of ACCU 4 to ACCU1, the contents of ACCU 1 to ACCU 2, the contents of ACCU 2 to ACCU 3 etc.
Page 278 OB 132/133: Roll-Up ACCU/Roll-Down ACCU Shift Accu contents <ACCU 4> ACCU 4 <ACCU 3> <ACCU 3> <ACCU 2> ACCU 3 OB 132 ACCU 2 <ACCU 1> <ACCU 2> <ACCU 4> ACCU 1 <ACCU 1> before after Fig. 6-1 Effect of the "roll-up" function Shift Accu contents <ACCU 4>...
Page 279: 6.10 Ob 141: "Disable Single Cyclic Timed Interrupts" On/Off
OB 141: "Disable Single Cyclic Timed Interrupts" On/Off 6.10 OB 141: "Disable Single Cyclic Timed Interrupts" On/Off Using OB 141, you can prevent certain cyclic timed interrupt OBs (timed interrupts at fixed intervals ) from being called at one or more consecutive block or operation boundaries.
Page 280 OB 141: "Disable Single Cyclic Timed Interrupts" On/Off 2. ACCUs 2a) ACCU-2-L Function no., Permitted values: 1, 2 or 3 where: The contents of ACCU 1 are loaded in the control word. All the bits marked ’1’ in the mask in ACCU 1 are set to ’1’...
Page 281: Table 6-9 Error Ids Of Ob 141 In Accu-1-L
OB 141: "Disable Single Cyclic Timed Interrupts" On/Off Possible errors If an error occurs, the system program sets the RLO to ’1’. The errors listed in the following table can occur. If an error occurs, the system program enters the error ID listed below in ACCU-1-L. Table 6-9 Error IDs of OB 141 in ACCU-1-L Meaning...
Page 282: 6.11 Ob 142: "Delay All Interrupts" On/Off
OB 142: "Delay All Interrupts" On/Off 6.11 OB 142: "Delay All Interrupts" On/Off A STEP 5 program can be interrupted at block or operation boundaries by programs with a higher priority. The process interrupts and all timed interrupts belong to these higher priority program execution levels.
Page 283 OB 142: "Delay All Interrupts" On/Off The bits in the control word have the following meaning: Bit no. Type of interrupt 0 = ’1’ Cyclic timed interrupts, fixed period 1 = ’1’ Clock-controlled interrupt 2 = ’1’ Process interrupts 3 = ’1’ Delayed interrupt 4 to 15 Reserved: these bits must be ’0’...
Page 284: Table 6-10 Error Ids Of Ob 142 In Accu-1-L
OB 142: "Delay All Interrupts" On/Off Result After correct and error-free processing the system program sets the RLO to ’0’. Calling OB 142 has the following results: Contents of ACCU 1 Funct. no. in ACCU-2-L before after control word control word mask control word mask...
Page 285: 6.12 Ob 143: "Delay Single Cyclic Timed Interrupts" On/Off
OB 143: "Delay Single Cyclic Timed Interrupts" On/Off 6.12 OB 143: "Delay Single Cyclic Timed Interrupts" On/Off Using OB 143, you can prevent certain cyclic timed interrupt OBs (timed interrupt OBs with a fixed period) from being called at one or more consecutive block or operation boundaries.
Page 286 OB 143: "Delay Single Cyclic Timed Interrupts" On/Off 2. ACCUs 2a) ACCU-2-L Function no., Permitted values: 1, 2 or 3 where: The contents of ACCU 1 are loaded in the control word. All the bits marked ’1’ in the mask in ACCU 1 are set to ’1’...
Page 287: Table 6-11 Error Ids Of Ob 143 In Accu-1-L
OB 143: "Delay Single Cyclic Timed Interrupts" On/Off Possible errors If an error occurs, the system program sets the RLO to ’1’. The errors listed in the following table can occur. If an error occurs, the system program enters the error ID listed below in ACCU-1-L. Table 6-11 Error IDs of OB 143 in ACCU-1-L Meaning...
Page 288: 6.13 Ob 150: Set/Read System Time
OB 150: Set/Read System Time 6.13 OB 150: Set/Read System Time • • The system time is backed up by the battery in the PLC rack. If the Features of the system time time is set, it therefore remains correct even following a power failure.
Page 289 OB 150: Set/Read System Time 1b) Format of the data field when reading the system time Bit no. word 1 Seconds 1/100 seconds word 2 Format Hours Minutes word 3 Day of month Weekday word 4 Year Month The time parameters have the following meaning, range of values and representation: Parameter Permitted range of values...
Page 290: Ob 150: Set/Read System Time
OB 150: Set/Read System Time 2. ACCUs 2a) ACCU-2-L ACCU-2-L contains information about the required function and the data field used. It must have the following structure: Bit no. Function no. Address area type Data block no. Parameters in ACCU-2-L Function no., Permitted values: 1 = set system time...
Page 291: Table 6-12 Error Ids Of Ob 150 In Accu-1-L
OB 150: Set/Read System Time Table 6-12 Error IDs of OB 150 in ACCU-1-L Meaning 9601H Data block not loaded 960FH Multiple call for the block 9611H Illegal function no. 9612H Address area type illegal 9613H Data block number illegal 9614H "Number of first data field word"...
Page 292 OB 150: Set/Read System Time Set system time" " (continued) STEP 5 operations in OB 1 for calling OB 150: 1 1 0 A Values for ACCU-2-L: DB no. = 10 Address area type = 1 for "data field in DB" Function no.
Page 293: 6.14 Ob 151: Set/Read Time For Clock-Controlled Interrupt
OB 151: Set/Read Time for Clock-Controlled Interrupt 6.14 OB 151: Set/Read Time for Clock-Controlled Interrupt Function By calling OB 151 you can do the following: • • cause the CPU 948 to activate the clock-controlled interrupt ("timed job" - OB 9, refer to Section 4.5.3) at a selected time: - every minute - every hour - every day...
Page 294 OB 151: Set/Read Time for Clock-Controlled Interrupt The parameters have the following meaning, range of values and representation: Parameter Permitted range of values Value in Job type 0 to 7 where: BCD format 0: cancel job or no job active 1: every minute 2: every hour 3: every day...
Page 295 OB 151: Set/Read Time for Clock-Controlled Interrupt 2. ACCUs 2a) ACCU-2-L ACCU-2-L contains information about the required function and the data field used. It must have the following structure: Bit no. Function no. Address area type Data block no. Parameters in ACCU-2-L Function no., Permitted values: 1 = generate job...
Page 296: Table 6-13 Error Ids Of Ob 151 In Accu-1-L
OB 151: Set/Read Time for Clock-Controlled Interrupt Note If, when reading out the timed job, the job type is ’0’ and all the remaining parameters are ’F’ or ’FF’ (hex) in the data field, no timed job is active. This status can occur in the following situations: a) there was a COLD RESTART without a timed job being generated b) when a "one-time"...
Page 297 OB 151: Set/Read Time for Clock-Controlled Interrupt Points to note with the time Regardless of when a clock-controlled interrupt (timed job) is to be parameters triggered, the individual time parameters must be specified in certain combinations. Depending on the selected time for the clock-controlled interrupt, certain parameters must be specified, while others are not evaluated by the system program.
Page 298 OB 151: Set/Read Time for Clock-Controlled Interrupt Examples Various timed jobs (in 24 hour format): 1. "Job at 29th second of every minute" (12:44:29, 12:45:29 etc.): You must specify: Job type 1 (Function no. in ACCU-2-L = 1) Seconds 2. "Job every hour at xx:14:15": You must specify: Job type 2 (Function no.
Page 299 OB 151: Set/Read Time for Clock-Controlled Interrupt Various timed jobs (in 24 hour format), continued 7. "Job once on the 31.12.1999 at 23:55:00": You must specify: Job type 7 (Function no. in ACCU-2-L = 1) Seconds Minutes Format/hour = Day of month= Month Year 8.
Page 300: 6.15 Ob 153: Set/Read Time For Delayed Interrupt
OB 153: Set/Read Time for Delayed Interrupt 6.15 OB 153: Set/Read Time for Delayed Interrupt Using OB 153, you can transfer so-called "delay jobs" to the system program. After a specified delay time "a delayed interrupt" is then processed (refer to OB 6, Section 4.5.3). Function By calling OB 153, you can do the following: •...
Page 301 OB 153: Set/Read Time for Delayed Interrupt Note If a previously defined delay time is not yet elapsed when a further delay time is defined, the previously defined time is lost and the new delay time started. Result After correct processing of OB 153, the RLO, the condition code bits OR, ERAB and OS = 0.
Page 302 OB 153: Set/Read Time for Delayed Interrupt Stop delay time (cancel job) STEP 5 operations for calling OB 153: KF +2 Value for ACCU-1-L: function no. = 2 for "stop delay time" OB 153 Call OB 153 Read out remaining time of a delay job: STEP 5 operations for calling OB 153: KF +3 Value for ACCU-1-L: function no.
Page 303: 6.16 Ob 180: Variable Data Block Access
OB 180: Variable Data Block Access 6.16 OB 180: Variable Data Block Access Using OB 180 You can use OB 180 when working with data blocks that are longer than 261 words (incl. 5 words header). Using OB 180, you can shift an "access window" of 256 data words in steps of 16 words over a data block (at paragraph addresses).
Page 304 OB 180: Variable Data Block Access Possible errors The errors listed in the following table can occur. If an error does occur, the system program sets the RLO to ’1’ and enters the error IDs listed in the table in ACCU 1. The other bit and word codes are cleared.
Page 305 OB 180: Variable Data Block Access Example You want the data block start address (DBA = 4152H in DB 17, length = 256 DW) to be shifted by 32 data words relative to the end of the block. open DB 17 shift value as constant call OB 180: shift access window After OB 180 has been called, the data word, for example, at address 4...
Page 306: Fig. 6-3 Shifting The Db Start Address
OB 180: Variable Data Block Access Example continued: DB 17 Address 4 151BH 5 words block header 4 151FH 4 1520H "00" (4152H) 4 1530H "16" 4 1540H DW 0 "32" (4154H) "33" DW 1 4 1541H "34" DW 2 4 1542H "35"...
Page 307: Ob 181: Test Data Blocks (Db/Dx)
OB 181: Test Data Blocks (DB/DX) 6.17 OB 181: Test Data Blocks (DB/DX) With the special function organization block OB 181, you can test data blocks as follows: • • whether or not a particular DB or DX data block exists, •...
Page 308: Table 6-17 Error Codes Of Ob 181 And Their Scans
OB 181: Test Data Blocks (DB/DX) Result If the function is executed without any error and if the block exists on the CPU, the system program transfers the following values: - ACCU-1-L: Address of the 1st data word (DW 0), 20-bit address, - ACCU-2-L: Length of the data block in words (without...
Page 309: 6.18 Ob 182: Copy Data Area
OB 182: Copy Data Area 6.18 OB 182: Copy Data Area Function OB 182 copies a data area of variable length from one data block to another. The source and destination blocks can be DBs or DXs. The start of the area in the source and destination blocks can be freely selected.
Page 310 OB 182: Copy Data Area The parameters have the following significance and range of values : Parameter Permitted range of values Data block type (source and destination) 1 = DB 2 = DX Data block no. (source and destination) 3 to 255 No.
Page 311: Table 6-18 Error Ids Of Ob 182 In Accu-1-L
OB 182: Copy Data Area 2b) ACCU-1-L Number of the 1st data field word, possible values (depending on the address area type: DB, DX: 0 to 2038 F flags: 0 to 246 (= No. of flag byte ’x ’) S flags 0 to 4086 (= No.
Page 312: 6.19 Ob 202 To 205: Multiprocessor Communication
OB 202 to 205: Multiprocessor Communication 6.19 OB 202 to 205: Multiprocessor Communication A detailed description of these special function organization blocks can be found in Chapter 10. The special function organization blocks OB 200 and OB 202 to OB 205 allow data transfer between the individual CPUs using the coordinator COR C in multiprocessor operation.
Page 313: 6.20 Ob 222: Restart Cycle Monitoring Time
OB 222: Restart Cycle Monitoring Time 6.20 OB 222: Restart Cycle Monitoring Time The special function OB 222 causes the cycle monitoring time to be restarted, i.e. the timer for monitoring is started from the beginning. By calling this special function, the maximum permitted cycle time for the current cycle is extended by the value selected at the time of the call.
Page 314: 6.21 Ob 223: Compare Start-Up Modes
OB 223: Compare Start-Up Modes 6.21 OB 223: Compare Start-Up Modes Function By calling OB 223, you can check whether the start-up modes of all CPUs involved in multiprocessor operation are the same and able to execute a programmed reaction to errors. Parameters none Result...
Page 315: 6.22 Ob 254/255: Copy/Duplicate Data Blocks
OB 254/255: Copy/Duplicate Data Blocks 6.22 OB 254/255: Copy/Duplicate Data Blocks With the special functions OB 254/255, you copy individual data blocks from a memory card to the user memory or duplicate individual data blocks within the user memory. The special function OB 254 and OB 255 work identically, with OB 254 exclusively for DX data blocks and OB 255 for DB data blocks.
Page 316 OB 254/255: Copy/Duplicate Data Blocks Parameters 1. ACCU-1-LL Number of the block to be copied. The following block numbers are possible: Block type Block number DB (OB 255) 3 to 255 DX (OB 254) 3 to 255 2. ACCU-1-LH ACCU-1-LH must be zero. Duplicating Function A data block is duplicated within the user memory and it is assigned a...
Page 317 OB 254/255: Copy/Duplicate Data Blocks Result following copying After the function has been executed correctly and error-free, the and duplicating system program sets the RLO to ’0’ and clears the condition code bits CC 1 and CC 0. Calling OB 254/255 changes the contents of ACCU 1 to ACCU 4. The BR register is retained.
Page 318: Table 6-21 Result Ids For Ob 254/255 In Accu-1-Ll
OB 254/255: Copy/Duplicate Data Blocks IDs in ACCU-1-LL The system program sets IDs in ACCU-1-LL which specify the causes of a warning or error in more detail. Bit no. Cause of error/warning The following group codes apply: Bit no. 7 (W) = 1:warning Bit no.
Page 319: Contents Of Chapter
Extended Data Block DX 0 Contents of Chapter 7 Application ............. 7 - 4 Structure of DX 0 .
Page 320 Extended Data Block DX 0 The following chapter explains how to use the data block DX 0 and how it is structured. You will find information about the meaning of the various DX 0 parameters and will learn how to create and how to assign parameters for a DX 0 data block based on examples.
Page 321 Application Application You can adapt certain system program functions to meet your own requirements by selecting alternative defaults in DX 0 compared to the standard defaults (marked in the parameter table by "D"). The defaults of the system program (D) are automatically set during each COLD RESTART and DX 0 is then evaluated.
Page 322 Structure of DX 0 Structure of DX 0 DX 0 consists of three parts: • • the start ID for DX 0 (DW 0, 1 and 2) , • • several fields of different lengths (depending on the number of parameters) •...
Page 323 Structure of DX 0 Formal structure Bit no. ASCII chars: Field ID 1 Field length 1 Par ameter Field 1 Par ameter Par ameter Field ID 2 Field length 2 Field 2 Par ameter Field ID n Field length n Par ameter Field n Par ameter...
Page 324 Structure of DX 0 7.2.1 Example of Input in DX 0 Start ID DW 0: KH = 4D41 DW 1: KH = 534B DW 2: KH = 5830 Field ID/length DW 3: KH = 0101 Field 1 Parameters (occupies 1 DW) DW 4: KH = 1001 Field ID/length...
Page 325: Table 7-1 Dx 0 Parameters And Their Meaning
Parameters for DX 0 Parameters for DX 0 Table 7-1 DX 0 parameters and their meaning Field ID/length Parameters Meaning 1st/2nd word Modes 01xx 1000 D Interrupts at block boundaries (CPU 946/947: 150U mode) 1001 Interrupts at operation boundaries (CPU 946/947: 155U mode) Start-up program execution 02xx 1000...
Page 326 Parameters for DX 0 Field ID/length Parameters Meaning 1st/2nd word Table 7-1 continued: 05xx Interrupt servicing: timed interrupts (cont.) 2000 00yy Basic clock rate for timed interrupt servicing: Basic clock rate = (yy 10 ms) Permitted values: 01H to FFH D yy = 0A (100 ms) 3000 D Clock rate distribution according to interval 1 (1, 2, 5, 10)
Page 327 Parameters for DX 0 • • As standard, the timers T 0 to T 255 are updated. Updating the timers • • If you enter the value "0" in DX 0, no timers are updated, even if they are included in the program. There is then also no error message output.
Page 328 Parameters for DX 0 You can modify these priorities for the following program execution levels individually in DX 0, by specifying the priority value from ’1’ to ’5’ (the value ’1’ means highest priority): • • timed interrupts • • system interrupt INT X (X = A, B, C or D), •...
Page 329: Examples Of Parameter Assignment
Examples of Parameter Assignment Examples of Parameter Assignment 7.4.1 STEP 5 Programming Example A: You want to use three CPUs in the multiprocessor mode: CPU A, B and C. CPU A and B work closely with each other, often exchange data and execute a complicated start-up program.
Page 330 Examples of Parameter Assignment Example B: The parameter assignment for DX 0 shown below achieves the following: - the mode "interrupts at operation boundaries" is set, - the timer updating is switched off, - the cycle time is set to 2.5 seconds, - the level priority of timed interrupts is set to ’2’...
Page 331: Parameter Assignment Using The Pg Screen Form
Examples of Parameter Assignment 7.4.2 Parameter Assignment With the PG system software, screen forms are available for assigning using the PG Screen Form parameters in DX 0 for the CPU 948. The PG software automatically generates data block DX 0 according to the default parameters (values in bold face)and parameters you have specified.
Page 332 Examples of Parameter Assignment If you move on to the second screen form (Fig. 7-3) you will find the following parameters: - Time interrupts, - Hardware process interrupts, - Process interrupts input byte 0. DX 0 - parameter assignment (S5-155U CPU 948) DX 0 Time interrupts: Time interrupt servicing:...
Page 333 Examples of Parameter Assignment Flow chart for completing the DX 0 screen forms Are there parameters to be changed in the 1st screen form? Repeat the following procedure until you have made all the necessary changes in the form: - Select the input field: Position the cursor on the parameter field.
Page 334 Examples of Parameter Assignment Continuation of the example Complete the screen form as follows to obtain this response: First DX 0 screen form: • • For the MODE parameter, select "interruptability at operation boundaries" with function key F3. • • For the parameter NUMBER OF TIMER CELLS first press function key F3 and then type in the number 0 (= timer).
Page 335: Memory Assignment And Memory Organization
Memory Assignment and Memory Organization Contents of Chapter 8 Structure of the Memory Area ..........8 - 4 Memory Assignment in the CPU 948 .
Page 336 Memory Assignment and Memory Organization You can use this chapter as a reference section to check on the organization of the CPU 948 memory. The chapter also includes important information contained in some of the system data words. CPU 948 Programming Guide 8 - 3 C79000-B8576-C856-03...
Page 337: Structure Of The Memory Area
Structure of the Memory Area Structure of the Memory Area The memory of the CPU 948 is essentially divided into the following areas: Table 8-1 Structure of the memory area Memory area Data width Location User memory for: OBs, FBs, FXs, PBs, SBs, DBs, DXs 16 bits Serial communications interface area: RI, RJ...
Page 338: Memory Assignment In The Cpu 948
Memory Assignment in the CPU 948 Memory Assignment in the CPU 948 With the CPU 948, there are two possible user memories (RAM) available: • • the CPU 948-1 with 640 Kbytes of user memory • • the CPU 948-2 with 1664 Kbytes of user memory. Fig.
Page 339 Memory Assignment in the CPU 948 8.2.1 Memory Assignment for the System RAM Bit no.: Address: D 0000H System program and system data E 9FFFH E A000H S flags E AFFFH E B000H System program data E DEAFH E DEB1H BSTACK (60 entries) E DF6FH Reserved...
Page 340 Memory Assignment in the CPU 948 Bit no.: Address: E F000H RS Area (System Data, 256 Words) Reserved E F200H RT Area (Extended System Data, 256 Words) Reserved E F400H RI Area (Serial Comm. Interface, 256 Words) Reserved E F600H RJ Area (Extended Serial Comm.
Page 341: Memory Assignment For The Peripherals
Memory Assignment in the CPU 948 8.2.2 Memory Assignment for the Peripherals Bit no.: Address: F 0000H Unassigned Peripheral Address Space (52K Words) F D000H reserved F F000H Digital Peripherals (with PI, 128 I/128 Q) P area F F080H Analog Peripherals (without PI, 128 I/128 Q) F F100H Extended Peripherals...
Page 342 Memory Assignment in the CPU 948 Address Areas for Peripherals and Programming Them Area Referenced with Parameter (absolute address) L IB / T IB to 127 E FE00 L IW / T IW to 126 (Process image L ID / T ID to 124 input) E FE7F...
Page 343: User Memory Organization In The Cpu 948
User Memory Organization in the CPU 948 User Memory Organization in the CPU 948 Depending on the version of the CPU 948 used, the user memory occupies the memory area from 0 0000H to C FFFFH. When you load the individual blocks of your program, they are stored in the memory in random order (with addresses in ascending order).
Page 344: Fig. 8-5 Example: Location Of Blocks In Memory
User Memory Organization in the CPU 948 Example Block List in DB 0 Memory Bit no. Bit no. Header 1 xxxx0H Start Block 1 Body 1 Filler Block Ascending Header 2 Addresses xxxx0H Body 2 Start Block n Header n xxxx0H Body n = Paragraph addresses (16 word boundary)
Page 345 User Memory Organization in the CPU 948 8.3.1 Block Headers in Each block in the memory begins with a header that is five words User Memory long. The block header is divided as follows: 1st word: Block start ID: 7070H 2nd word: High byte = Block type Bit no.
Page 346: Block Address List In Data Block Db 0
User Memory Organization in the CPU 948 8.3.2 Block Address List in Data block DB 0 is located in the system RAM of the CPU (beginning Data Block DB 0 at address E E200H). It contains a list with the start addresses of all blocks in the user memory of the CPU.
Page 347: Ri/Rj Area
User Memory Organization in the CPU 948 Example of how to obtain a block address program blocks The block start addresses of the are located in DB 0 and begin at address E E400H. The start address of PB 22 can therefore be read out by accessing memory at address E E416H (= start address of the PB + 16H).
Page 348: Rs/Rt Area
RS/RT Area 8.3.4 RS/RT Area The RS and RT areas contain information for the system programmer and system internal data. The RS area is an area that is 256 words long in the internal system RAM of the CPU. RS occupies addresses E F000H to E F0FFH. Caution You should only write to system data words RS 60 to RS 63: All other system data should only be read:...
Page 349: Table 8-2 Assignment Of The Rs Area
RS/RT Area Using the online function SYSTEM PARAMETERS, you can obtain the information contained in some of the system data (about the internal structure of the CPU, the software release, the CPU identifier etc.) Assignment of the RS area Table 8-2 Assignment of the RS area Name Address...
Page 350 RS/RT Area Name Address Table 8-2 continued: System message, function number E F04BH System message, parameter1 E F04CH System message, parameter 2 E F04DH System message, parameter 3 E F04EH 79 to 95 System program Current time of day (seconds) E F060H Current time of day (hours) E F061H...
Page 351: Bit Assignment Of The System Data Words
Bit Assignment of the System Data Words 8.3.5 Bit Assignment of the System Data Words System data RS 0 Input byte IB 0 Image table (external process interrupts) Address E F000H Table 8-3 Bits in RS 0 (image of IB 0) High byte Bit no.
Page 352: Table 8-4 Bits Of Rs 1 (Current Process Interrupts)
Bit Assignment of the System Data Words System data RS 1 Condition code of external process interrupts currently in processing queue Address: E F001H Table 8-4 Bits of RS 1 (current process interrupts) High byte Bit no. Assignment All the bits have the value ’0’ Low byte Bit = ’1’: edge I 0.7 Bit = ’1’: edge I 0.6...
Page 353: Table 8-5 Bits Of Rs 5 (Cycle Time)
Bit Assignment of the System Data Words System data RS 5 Current cycle time Address: E F005H Table 8-5 Bits of RS 5 (cycle time) High byte and low byte Bit no. Assignment The entered binary value * 10 msec. equals the cycle time of the cycle processed last Example Bit no.
Page 354: Table 8-6 Bits Of Rs 7 (Plc Stop Ids)
Bit Assignment of the System Data Words System data RS 7 Programmable controller STOP mode IDs (ISTACK) Address: E F007H Table 8-6 Bits of RS 7 (PLC stop IDs) High byte Bit no. Assignment Reserved Faulty ISTACK level Illegal start-up type (UANL) Interruption in stop loop Illegal call of system block (SYSFHL) Error in start-up block (AFEL)
Page 355: Table 8-7 Bits Of Rs 8 (Start And Start-Up Ids)
Bit Assignment of the System Data Words System data RS 8 Start and restart IDs (ISTACK) Address: E F008H Table 8-7 Bits of RS 8 (start and start-up IDs) High byte Bit no. Assignment Default: MANUAL COLD RESTART/ WARM RESTART (MSEG) Default: AUTOMATIC COLD RESTART (ANEG) Default: AUTOMATIC WARM...
Page 356: Table 8-8 Bits Of Rs 16 (Error Area Output Bytes 0 To 15)
Bit Assignment of the System Data Words System data words Error areas RS 16 to RS 47 RS xx Address(es) Error area RS 16 E F010 Output bytes 0 to 15 RS 17 to E F011 to Output bytes 16 to 127 RS 23 E F017 RS 24 to...
Page 357 Bit Assignment of the System Data Words Example of RS 16 The content of system data register RS 16 "8020" hexadecimal or "1000 0000 0010 0000" binary. The process image for output bytes 0 and 10 has not been updated correctly. System data RS 50 PAFE byte for "backplane bus functions"...
Page 358 Bit Assignment of the System Data Words System data words System message RS 75 to RS 78 The entries in system data words RS 75 to RS 78 refer to the error that occurred last. The message consists of four system data words with the following structure: RS 75 Error number...
Page 359: Table 8-9 Rs 75: General Errors
Bit Assignment of the System Data Words General errors Table 8-9 RS 75: general errors Error Parameter Meaning number type Block called is not loaded Addressing error Cycle time error Substitution error Timeout distributed peripherals Timeout user memory Load/transfer error with data blocks and extended data blocks Bracket counter overflow Data block to be opened does not exist...
Page 360 Bit Assignment of the System Data Words Error Parameter Meaning number type Table 8-9 continued: AUTOMATIC WARM RESTART not possible; COLD RESTART required Illegal start-up type Load/transfer error during block transfer operation (incorrect memory area boundaries with TNW, TXB, TXW) Illegal length for G DB/GX DX DB/DX already exists for G DB/GX DX Memory space insufficient for G DB/GX DX...
Page 361: Table 8-11 Rs 75: Error Codes Of The Self Test Functions
Bit Assignment of the System Data Words Error Parameter Meaning number type Table 8-10 continued Peripheral entered in DB 1 is not plugged in Offset too big (parameter error) Too many offsets Error codes of the self test functions Table 8-11 RS 75: error codes of the self test functions Error Parameter...
Page 362: Table 8-12 Rs 76 To Rs 78: Parameter Types
Bit Assignment of the System Data Words Structure of the parameter field (RS 76 to RS 78) Table 8-12 RS 76 to RS 78: Parameter types Parameter Structure of the parameter field type No parameter; parameter 1, 2, 3 = 0 Parameter 1: block type/block number (IDs from block header) Parameter 2: operation that caused an interruption Parameter 1: interface module number (IM 302) (distributed periphery)
Page 363 Bit Assignment of the System Data Words Parameter Structure of the parameter field type Table 8-12 continued: Parameter 1 The following bits are set depending on the error: Bit no. 0 = 1: QVZ in initialization Bit no. 1 = 1: PARE in initialization Bit no.
Page 364 Bit Assignment of the System Data Words Example of a system message RS 75 E F04BH RS 76 7804H E F04CH RS 77 0064H E F04DH RS 78 0078H E F04EH RS 75, error number = 21H:The error occurred in the STEP 5 user program when generating a DB/DX.
Page 365: Table 8-13 Structure Of Rs 96 (Real-Time Clock: Seconds, 1/100 Seconds)
Bit Assignment of the System Data Words System data words Real-time clock RS 96 to RS 99 The current date and time of day are kept in system data areas RS 96 to RS 99 and can if necessary be read out from these locations. RS 96 Seconds 1/10, 1/100 seconds E F060H...
Page 366: Table 8-14 Structure Of Rs 97 (Real-Time Clock: Hours, Minutes)
Bit Assignment of the System Data Words RS 97 Hours and minutes (address: E F061H): Table 8-14 Structure of RS 97 (real-time clock: hours, minutes) High byte Bit no. Assignment 0 = 12 hour format, 1 = 24 hour format 0 = AM, 1= PM Hours, tens, permitted: 00/01H with 12 hour format, 00/02H with 24 hour format...
Page 367: Table 8-16 Structure Of Rs 99 (Real-Time Clock: Year, Month)
Bit Assignment of the System Data Words RS 99 Current year and month (address: E F063H): Table 8-16 Structure of RS 99 (real-time clock: year, month) High byte Bit no. Assignment Year, tens, permitted: 00H to 09H Year, units, permitted: 00H to 09H Low byte Month, tens, permitted: 00/01H...
Page 368 Bit Assignment of the System Data Words System data RS 120 Software protection System data RS 120 controls the system function "software protection". With this function, you can prevent blocks being read, overwritten or deleted by the PG (e.g. by unauthorized personnel) by specifying a password.
Page 369 Bit Assignment of the System Data Words When is the software A password can be specified at any time. Once it has been specified, protection software protection is, however, only active at certain times, as shown activated/deactivated? below: • • in the SOFT STOP mode: once after calling OB 38 cyclically before calling OB 39 •...
Page 370: Table 8-18 Assignment Of Rs 120 (Software Protection) When Reading
Bit Assignment of the System Data Words Reading system data RS 120 By reading out system data RS 120, you can find out whether a "job" was executed by writing the system data. The system program enters a result code here. Assignment of the system data when reading After calling the software protection function, you can evaluate the result code to find out whether the job was successful.
Page 371 Bit Assignment of the System Data Words Valid result codes Value Explanations 0000H No error 4x01H The maximum number of delete attempts has been exceeded. The counter can only be reset with a cold restart. 4x02H Illegal password (0000H or 3FFFH) 4x04H You have attempted to specify a new password while the password protection was active (x = number of attempts to delete)
Page 372 Bit Assignment of the System Data Words Examples of writing and reading RS 120 Activating the software protection in the start-up blocks: (If you activate the protection in the program, it is best to activate it in a start-up OB (OB 20, OB 21, OB 22, OB 38).) KH C0AF KH = bit pattern "specify password"...
Page 373 Bit Assignment of the System Data Words System data words For self-test function RS 136 to RS 137 The system data words RS 136 to RS 137 are used for the self-test. RS 136 Number of time slices (address: E F088H) RS 137 Control bits (address: E F089H) Using the control bits, the individual self-test functions can be...
Page 374: Table 8-20 Bits Of Rs 253 (List Of Interface Modules Plugged In)
Bit Assignment of the System Data Words System data RS 139 Cycle time used when retriggering Address E F08AH This system data word contains the time used for the cycle since the last system checkpoint (at the beginning of OB 1) to the next retriggering with OB 222 (if OB 222 is called more than once within the cycle, the time to the last retriggering).
Page 375: Addressable System Data Area
Addressable System Data Area 8.3.6 Addressable System Data The system program uses the memory area from E 8200H to Area E DEF0H as an addressable system data area. PLC identification field At the start of this area there is an information field of 12 words in which an identifier of the PLC is entered.
Page 376 Addressable System Data Area System parameters System parameters in the memory area beginning with the address E 8210H: Word Start add. interface module input E 8210H Start add. interface module output E 8211H Start add. process image input table E 8212H Start add.
Page 377 Addressable System Data Area Word 19 and word 21 Structure of words 19 and 21: Word 19 Bit no. High byte Slot ID CPU 4 Slot ID CPU 3 Slot ID CPU 2 Slot ID CPU 1 Low byte CPU type: 0010 = CPU 948 (only valid in conjunction with the CPU ID) CPU-ID 2:...
Page 378 Addressable System Data Area Word 21 Bit no. High byte reserved Bit no. Low byte Release of the PG interface software in the form "xyH" Example: 13H corresponds to release "V1.3" CPU 948 Programming Guide 8 - 45 C79000-B8576-C856-03...
Page 379: Memory Access Using Absolute Addresses
Memory Access Using Absolute Addresses Contents of Chapter 9 Introduction............. 9 - 4 Memory Access via Addresses in ACCU 1 .
Page 380 Memory Access Using Absolute Addresses This chapter explains how to use STEP 5 operations and special STEP 5 registers to address data in certain memory areas using absolute addresses. CPU 948 Programming Guide 9 - 3 C79000-B8576-C856-03...
Page 381: Local Memory
Introduction Introduction The STEP 5 programming language contains operations with which you can access the entire memory area. These operations belong to the "system operations". The operations described in this chapter work with 20-bit absolute addresses. Consequently, they are dependent on the memory size and type, the peripherals, CPs, and IPs of your programmable controller.
Page 382: Fig. 9-1 Global And Local Memory
Introduction The local memory is internal and is available in each CPU (acc. to the number of CPUs plugged) 0 0000H The global memory is external and is available via the S5 bus. It exists as a common memory area shared by all CPUs in one PLC.
Page 383: Memory Access
Introduction Memory access Using absolute addresses, you can access the following local or global memory areas with the operations indicated (refer to Fig. 9-2). Access to the local and global You can access both the local and global areas: area •...
Page 384: Fig. 9-2 Access To Local Or Global Areas Using Absolute Addresses
Introduction access possible access not possible Access in multiprocessor mode can lead to errors a) LIR, TIR, LDI, TDI, TNW, TXB TXW b) LRW, TRW, LRD, TRD c) LY GB, LY GW, LY GD, d) LW GW, LW GD, TY GB, TY GW, TY GD, (TSG) TW GW, TW GD, (TSG) e) LY CB, LY CW, LY CD, f) LW CW, LW CD,...
Page 385: Table 9-1 Operations For Indirect Memory Access Using Registers
Memory Access via Address in ACCU 1 Memory Access via Address in ACCU 1 Application The operations listed in this section are suitable primarily for access to data blocks and other operand areas. You should, however, not access blocks containing STEP 5 programs (OBs, FBs, PBs and SBs) with these operations.
Page 386: Lir/Tir: Loading To Or Transferring From A 16-Bit Memory Area Indirectly
Memory Access via Address in ACCU 1 9.2.1 LIR/TIR: Loading to or The following table shows which register numbers you can use with Transferring from a 16-Bit the CPU 948 for the LIR and TIR operations and how these are Memory Area Indirectly assigned.
Page 387: Fig. 9-3 Lir/Tir With 16-Bit Memory Areas (Word-Oriented)
Memory Access via Address in ACCU 1 addressed Register n memory location ACCU 1 LIR n addressed Register n memory location ACCU 1 TIR n Fig. 9-3 LIR/TIR with 16-bit memory areas (word-oriented) addressed Register n memory location ACCU 1 LIR n addressed Register n...
Page 388 Memory Access via Address in ACCU 1 Registers 0 to 3 and 9 to 12: During program processing, the accumulators are used as buffers for ACCUs 1, 2, 3 and 4 the CPU. The TIR operation transfers the contents of the accumulators into absolutely addressed memory registers.
Page 389: Fig. 9-5 Using The Dba Register
Memory Access via Address in ACCU 1 The DBA register changes if one of the following occurs: • • Another data block is opened, • • the program returns to a higher order block after a new data block is opened in the called block (refer to Section 2.4.3). Example Effect of the "CX DX 17"...
Page 390 Memory Access via Address in ACCU 1 Register 8: In addition to the DBA register, a DBL register is loaded every time a DBL = Data Block Length data block is called. It contains the length (in words) of the data block called, without the block header.
Page 391: Fig. 9-6 Using The Dbl Register
Memory Access via Address in ACCU 1 Example "CX DX 17" Effect of the operation on the DBL: D X 1 7 A d d r e s s e s 4 1 5 1 B H 5 w o r d s 4 1 5 1 C H B l o c k h e a d e r 4 1 5 1 D H...
Page 392 Memory Access via Address in ACCU 1 9.2.2 Examples of Access to DW > 255 Example 1: The content of data word DW 300 in DB 100 is read and transferred to flag word FW 100 (by changing the STEP 5 operation shown in bold face, it can also be used to read other data blocks (DB or DX)).
Page 393 Memory Access via Address in ACCU 1 Example 2 continued: Flag assignment: FW 10: Bits 4 to 19 of the start address of the DB/DX (points to DW 0) FW 12: Length of the DB/DX (number of data words) FD 14: Address of the last data word in the DB/DX + 1 (physical address) SEGMENT 1 0000...
Page 394: Ldi/Tdi: Loading To Or Transferring From A 32-Bit Memory Area Indirectly
Memory Access via Address in ACCU 1 9.2.3 LDI/TDI: Loading to or The following table shows which register names you can use on the Transferring from a 32-Bit CPU 948 for the LDI and TDI operations and how these are assigned. Memory Area Indirectly Table 9-3 32-bit register for LDI/TDI...
Page 395 Memory Access via Address in ACCU 1 SA Register: On completion of the operation, the 20-bit absolute address of the SAC = STEP Address operation to be processed next is entered in the SA register. Counter BA Register: During program processing of the STEP 5 user program, a 20-bit Block Start Address absolute address is entered in the BA register.
Page 396: Transferring Memory Blocks
Transferring Memory Blocks Transferring Memory Blocks Application With the operations explained in this section, you can re-store data areas with a length of up to 255 words located in certain address areas. Operations Table 9-4 Operations for field transfer Operation Operand Function 0 to 255...
Page 397 Transferring Memory Blocks Addresses Memory area Table 9-5 continued: System RAM: E 8000H to E 9FFFH System data, 16 bits E B000H to E FBFFH System data (RI/RS, timers, counters etc.), 16 bits E A000H to E AFFFH S flags, 8 bits, low byte in 16-bit word (High byte not defined) E FC00H to E FFFFH Flags, process image, 8 bits...
Page 398: Fig. 9-7 Transferring Memory Fields
Transferring Memory Blocks ADF during execution If an addressing error (ADF) occurs once or more than once during the transfer, all the part fields are first transferred and then OB 25 is called before the next operation is executed. Example TXB and TXW between 8 and 16-bit memory areas: Ascending Ascending...
Page 399: Operations With The Base Address Register (Br Register)
Operations with the Base Address Register (BR Register) Operations with the Base Address Register (BR Register) Application The base address register (20 bits) allows you to calculate addresses and use indirect register load and transfer operations without using the ACCUs. The memory location whose absolute address is calculated as the sum of the BR register content plus a constant is accessed.
Page 400: Operations For Transfer Between Registers
Operations with the Base Address Register (BR Register) 9.4.1 Operations for Transfer between Registers Application You can use the operations described in this section for the fast exchange of values between the registers ACCU 1 (32 bits), step address counter (SAC - 20 bits) and BR register (20 bits). Operations Table 9-7 Register-register operations...
Page 401: Accessing The Local Memory
Operations with the Base Address Register (BR Register) 20 19 20 19 ... . ACCU 1 ACCU 1 MAS, MAB MSA, MBA Fig. 9-8 Transfer operations from one register to another 9.4.2 Accessing the Local Memory...
Page 402: Accessing The Global Memory
Operations with the Base Address Register (BR Register) Operation Operand Description Table 9-8 continued: Constant add the specified constant to content (-32768 to of the BR register and transfer the +32767) content of ACCU 1 to the double word addressed in this way ACCU 2 = ACCU 1 Error reaction...
Page 403 Operations with the Base Address Register (BR Register) Sequence The location used is the low byte of the word addressed by the BR register plus the constant. If the content of the low byte is ’0’, the TSG operation enters the slot ID in the location. Testing (reading) and possible occupation of the location (writing) form a program unit that cannot be interrupted.
Page 404: Table 9-9 Operations For Access To The Global Memory Organized
Operations with the Base Address Register (BR Register) Load and transfer operations on the Table 9-9 Operations for access to the global memory organized global memory organized in bytes in bytes Operation Operand Description LY GB -32768 to add the specified constant to content +32767 of the BR register and load the byte addressed in this way in ACCU-1-LL...
Page 405 Operations with the Base Address Register (BR Register) If the absolute addresses are not in the range shown, the CPU detects a load/transfer error (TRAF) and calls OB 32. If OB 32 is not loaded, the CPU changes to the STOP mode with the error code TRAF (ISTACK).
Page 406: Accessing The Dual-Port Ram Memory
Operations with the Base Address Register (BR Register) 9.4.4 Accessing the Dual-Port RAM Memory Application With the following operations, you can access pages organized as bytes or words using an absolute memory address. The absolute address is the sum of the BR register content and the constant contained in the operation (-32768 to 32767).
Page 407 Operations with the Base Address Register (BR Register) Opening a dual-port RAM page Operation Parameter Description Open the dual-port RAM page whose number is located in ACCU-1-L , permissible values: 0 to 255 The dual-port RAM page number must be between 0 and 255. If it is not, the CPU detects a substitution error (SUF) and calls OB 27.
Page 408: Table 9-11 Operations For Access To Pages Organized In Bytes
Operations with the Base Address Register (BR Register) Result You can evaluate the result of the TSC operation using condition codes CC 0 and CC 1: CC 1 CC 0 Description The "occupied" register contains ’0’. The CPU enters its own slot ID. The slot ID of the CPU is already entered in the "occupied"...
Page 409 Operations with the Base Address Register (BR Register) Operation Operand Description Table 9-11 continued: TY CB -32768 to add the specified constant to content +32767 of the BR register and transfer the content of ACCU-1-LL to the byte addressed in this way in the open page add the specified constant to content TY CW -32768 to...
Page 410: Table 9-12 Operations For Access To Pages Organized As Words
Operations with the Base Address Register (BR Register) Load and transfer operations for the dual-port RAM memory Table 9-12 Operations for access to pages organized as words organized in words Operation Operand Description LW CW -32768 to add the specified constant to content +32767 of the BR register and load the word addressed in this way in the open page...
Page 411: Multiprocessor Mode And Communication In The S5-155U
Multiprocessor Mode and Communication in the S5-155U Contents of Chapter 10 10.1 Multiprocessor Mode ........... . 10 - 4 10.1.1 When to use the Multiprocessor Mode .
Page 412 10.5 SEND Function (OB 202) ..........10 - 40 10.5.1 Function.
Page 413 Multiprocessor Mode and Communication in the S5-155U At the beginning of this chapter, you will see when you can use the multiprocessor mode and which data exchange is possible in this mode. The chapter provides you with information about programming for multiprocessor operation (Section 10.1).
Page 414: 10.1 Multiprocessor Mode
Multiprocessor Mode 10.1 Multiprocessor Mode Definitions of terms The S5-155U is set up for multiprocessor operation as soon as you plug in a coordinator module, regardless of how many CPUs or CP/IPs are plugged in. The CPUs must be plugged in without any gaps between them.
Page 415: Exchanging Data Via Ipc Flags
Multiprocessor Mode 10.1.3 Exchanging Data via IPC Interprocessor communication (IPC) flags are available for cyclic Flags exchange of binary data. They are used mainly for transmitting information byte by byte. Data is transferred as follows: ↔ CPU(s) CPU(s) ↔ CPU(s) Communications processor(s) The system program transfers IPC flags once per cycle.
Page 416: Fig. 10-1 Transferring Ipc Flags In The Multiprocessor Mode
Multiprocessor Mode Example CPU 1 Coordinator IPC output flags: Write FY 96 to FY 119 IPC input flags: Enabled area Read FY 120 to FY 125 per jumpers: IPC flag bytes FY 96 to FY 127 CPU 2 IPC output flags: Write FY 120 to FY 125 IPC input flags:...
Page 417 Multiprocessor Mode Data exchange between If you want to exchange data between one CPU and one CP, you must CPUs and communication enable the necessary number of IPC flags on the CP. You have 256 processors bytes available that you can divide into groups of 32 bytes. If you want to transfer data from one CPU to several CPs, the areas you enable in the CPs and the coordinator must not overlap, otherwise the same address is assigned twice.
Page 418: Exchanging Data Via Handling Blocks
Multiprocessor Mode Transmitting IPC flags in At the end of each program cycle, along with the updating of the multiprocessor operation process image, the CPU transmits the IPC flags specified in DB 1 when the coordinator signals the CPU that it can access the S5 bus. The coordinator allocates the bus enable signal to each CPU in sequence.
Page 419: What Needs To Be Programmed For The Multiprocessor Mode
Multiprocessor Mode 10.1.5 • • To allow the coordinator to coordinate access by the individual What needs to be Programmed for the CPUs to the I/O area, you must program data block DB 1. Even Multiprocessor Mode? if the CPU does not use I/Os or the IPC flags, a (empty) DB 1 must exist (for more information refer to Section 10.1.6) •...
Page 420 Multiprocessor Mode 3. Enter the values by pressing the enter key on the PG. The PG then generates DB 1. 4. Transfer DB 1 to the CPU. Note Entry of the timer field length is ignored! This parameter must be specified in DX 0 (see Chapter 7).
Page 421 Multiprocessor Mode 2. Type in the individual operand areas (from data word 3 onwards). Before each operand area, you must specify an ID. The possible ID words are as follows: ID word for digital inputs KH = DE00 ID word for digital outputs KH = DA00 ID word for IPC input flags KH = CE00...
Page 422 Multiprocessor Mode Entering DB 1 The system program adopts DB 1 during a cold restart. The system program checks to see if the inputs and outputs or IPC flags indicated in DB 1 exist in their corresponding modules. If they are not present there, a DB 1 error causes the CPU to go into the STOP mode and the STOP LED flashes slowly.
Page 423: Starting Up In The Multiprocessor Mode
Multiprocessor Mode 10.1.7 Starting up in the You can start the coordinator for multiprocessing in one of the Multiprocessor Mode following ways: Initial status: The RUN/STOP switch of each CPU is in the RUN position. The RUN/STOP switch on the coordinator is in the STOP position. Handling: Move the RUN/STOP switch on the coordinator from STOP to RUN.
Page 424: Test Mode
Multiprocessor Mode Power failure/return of power When power is shut off and then restored, the coordinator starts automatically. In this case, all CPUs execute an AUTOMATIC WARM RESTART or an AUTOMATIC COLD RESTART, depending on the setting in DX 0 (see Chapter 7). The start-up of the individual CPUs in multiprocessor operation is synchronized.
Page 425: 10.2 Multiprocessor Communication
10.2 Multiprocessor Communication Definition Multiprocessor communication means the exchange of larger amounts of data (data blocks) between CPUs operating in the multiprocessor mode. The COR C is necessary for multiprocessor communication. 10.2.1 Introduction To transfer data blocks, or to be more precise, blocks of data with a maximum length of 64 bytes (= 32 data words), you can use the following special functions that are integrated in the CPU: •...
Page 426: How The Transmitter And Receiver Are Identified
The data block in the receiving CPU can be longer or shorter than the data block to be sent. It is, however, important that the data words transferred by the SEND function exist in the receiving block; otherwise the RECEIVE function signals an error. Example: Data to be Data...
Page 427: Why Data Is Buffered
10.2.3 Why Data is Buffered Generally, the multiprocessor mode is used to distribute tasks on several CPUs. Since the tasks are not identical and the performance of the CPUs involved can be different, the program execution of the individual CPs in the multiprocessor mode is always asynchronous. This means that the data sent by a CPU cannot always be received immediately by another CPU.
Page 428: How The Buffer Is Processed And Managed
10.2.4 How the Buffer is Processed and Managed Principle The buffer is based on the FIFO principle (first in - first out, queue principle). The data is received in the order in which it is sent. This applies to each individual link (identified by the transmitting and receiving CPU) and is independent of other links.
Page 429: Fig. 10-5 Example Of The Occupation Of The Cor Buffer
Example Occupation of the buffer by a link The link between CPU 3 and CPU 2 is initialized. The link is assigned seven memory fields in the buffer of the coordinator. Following this, the data transfer shown below would be possible. Transmitting capacity (no.
Page 430 Summary Buffering data on the coordinator COR 923C allows the asynchronous operation of transmitting and receiving CPUs and compensates for their different processing speeds. Since the capacity of the buffer is limited, the receiver should check "often" and "regularly" whether there are data in the buffer (RECEIVE TEST function, receiving capacity >...
Page 431: System Start-Up
10.2.5 System Start-Up If you require multiprocessor communication, then all CPUs involved must go through the same STOP-RUN transition (= RESTART), i.e. all the CPUs go through a COLD RESTART or all CPUs go through a WARM RESTART. You must make sure that the restart of at least all the CPUs involved in the communication is uniform (see Section 10.1.7), in the following ways: •...
Page 432: Calling Communication Obs
10.2.6 Calling Communication OBs Proceed as follows: 1. Call the INITIALIZE function only in the cold restart organization block OB 20 on one CPU. 2. Call the SEND, SEND TEST, RECEIVE, RECEIVE TEST functions either only within the cyclic program or only within the time-driven program.
Page 433: How To Assign Parameters To Communication Obs
Results bits The results bits (CC 1/CC 0, RLO etc.) are influenced by the communication OBs. For more detailed information refer to Section 10.2.8. • • CPU 922, CPU 928, Changes in the ACCUs CPU 928B: The contents of ACCU 1 to ACCU 4 and the contents of the registers are not affected by the communication OBs.
Page 434: How To Evaluate The Output Parameters
Call parameters For all communication OBs the number of the first flag byte in the data field (= pointer to data field) in ACCU-1-L is transferred as the call parameter. Permitted values are 0 to 246. Example Data field with parameters for the RECEIVE function (OB 204) FY x + 0: transmitting CPU input parameter...
Page 435: Table 10-1 Condition Codes Of The Communication Obs
Table 10-1 Condition codes of the communication OBs Condition codes Evaluation Meaning CC 1 CC 0 Function executed completely and correctly Function aborted, pointer to data field illegal (>246) Function aborted owing to an initialization conflict JC= and Function aborted owing to an error (error number 1 to 9) JC= and...
Page 436: Table 10-2 Code Byte For The Communication Obs/Number Groups
The first byte in the field of the output parameters (condition code byte) also indicates whether or not a function has been correctly and completely executed. This byte contains detailed information about the cause of termination of a function. Assuming that at least the pointer to the data field contains a correct value, this byte is always relevant.
Page 437: Table 10-3 Condition Code Byte: Initialization Conflict Numbers
Example The SEND function indicates an error and is not executed. If you then make program and/or parameter modifications and the SEND function again indicates an error with a higher number than previously, you can assume that you have corrected one of several errors. Initialization conflict An initialization conflict can only occur with the INITIALIZATION function.
Page 438: Table 10-4 Condition Code Byte: Error Numbers
Cond. Significance code byte Table 10-3 continued: The assignment list in the data block is not correctly structured. The sum of the assigned memory fields is greater than 48. Errors If an error occurs, you must change the program/parameters. Error numbers (evaluation of the condition code byte as a byte): Table 10-4 Condition code byte: Error numbers Cond.
Page 439 Cond. Significance code byte Table 10-4 continued: The management data (queue management) of the selected links are incorrect; set up the buffer in the coordinator 923C again using the INITIALIZE function (SEND, RECEIVE, SEND TEST, RECEIVE TEST). The parameter "block ID" (SEND) or the block ID provided by the sender (RECEIVE) is illegal.
Page 440: Table 10-5 Condition Code Bytes: Warning Numbers
Warning The function could not be executed; the function call must be repeated, e.g. in the next cycle. Warning numbers (evaluation of the condition code byte as a byte): Table 10-5 Condition code bytes: Warning numbers Cond. Significance code byte The SEND function cannot transfer data, since the transmitting capacity was already zero when the function was called.
Page 441: 10.3 Runtimes Of The Communication Obs
10.3 Runtimes of the Communication OBs The "runtime" is the processing time of the special function organization blocks; the time from calling a block to its termination can be much greater if it is interrupted by higher priority activities (e.g. updating timers, etc.). Table 10-6 Runtimes of the communication OBs Special function OB...
Page 442 Transfer time An important factor of a link (e.g. from CPU 1 to CPU 2) is the total data transfer time. This is made up of the following components: • • time required to send (see runtime), • • length of time the data are buffered (on the COR 923C coordinator) •...
Page 443: Initialize Function (Ob 200)
INITIALIZE Function (OB 200) 10.4 INITIALIZE Function (OB 200) 10.4.1 Function To transfer data from one CPU to another CPU, the data must be temporarily buffered. The INITIALIZE function sets up a buffer on the COR 923C coordinator. The memory is initialized in fields with a fixed length of 32 words. Each memory field accepts one data field with a length between 1 data word and 32 data words.
Page 444 INITIALIZE Function (OB 200) If you are using four CPUs, there are twelve links: CPU 1 CPU 2 CPU 4 CPU 3 The INITIALIZE function specifies how the total of 48 available memory fields are assigned to the maximum twelve links. This means that each possible link, specified by the parameters "transmitting CPU"...
Page 445: Call Parameters
INITIALIZE Function (OB 200) 10.4.2 Call Parameters Structure of the (parameter) Before calling OB 200, you must supply the input parameters in the data field data field. OB 200 requires eight F flag bytes in the data field for input and output parameters: FY x + 0: Mode (automatic/...
Page 446 INITIALIZE Function (OB 200) Block ID, block number, The parameters are only relevant if you select the "manual" mode. address assignment list You must then create an assignment list in a data block in which the 48 available memory fields (or less) are assigned to the maximum 12 links.
Page 447 INITIALIZE Function (OB 200) Assignment list With the assignment list, you specify how many of the existing 48 memory fields are to be assigned to the links. The list is not changed by the system program. It has the following structure.
Page 448: Output Parameters
INITIALIZE Function (OB 200) Example You have three CPUs in your rack, CPU 2 sends a lot of data to the other two CPUs. The other two CPUs, however, only send a small amount of data no data back to CPU 2 as acknowledgements in a logical handshake. There is exchange CPU 1 and CPU 3 between...
Page 449 INITIALIZE Function (OB 200) Errors The "error" number group cannot occur with the INITIALIZE function. Warning The "warning" number group cannot occur with the INITIALIZE function. Total capacity This parameter specifies how many of the 48 available memory fields are assigned to links. In the "automatic"...
Page 450: Send Function (Ob 202)
SEND Function (OB 202) 10.5 SEND Function (OB 202) 10.5.1 Function The SEND function transfers a data field to the buffer of the COR 923C coordinator. It also indicates how many data fields can still be sent or buffered. 10.5.2 Call Parameters Structure of the (parameter) Before calling OB 202 you must specify the input parameters in the data...
Page 451 SEND Function (OB 202) Block ID ID = 1: DB data block ID = 2: DX data block ID = 0 or 3 to 255: illegal, causes an error message Block number The block number, along with the block ID and the field number specifies the area from which the data to be sent is taken (and where it is to be stored in the receiving CPU).
Page 452: Output Parameters
SEND Function (OB 202) The following situations are possible: • • DB is longer than source area: If the data block is sufficiently long, you obtain a 32-word long area per field as shown in the table above. • • DB is too short: If the end of the data block is within the selected field, in the last field an area with a length between 1 and 32 words will be transferred.
Page 453 SEND Function (OB 202) Errors When the SEND function is called, the following error numbers (evaluation of the condition code byte) can occur: Condition Significance code byte The parameter "receiving CPU" is illegal. The following errors are possible: - The number of the receiving CPU is greater than 4, - The number of the receiving CPU is less than 1, - The number of the receiving CPU is the same as the CPU’s own number.
Page 454 SEND Function (OB 202) Warning The function could be executed; the function call must be repeated, e.g. in the next cycle. The following warning numbers (evaluation of the condition code byte) can occur: Condition Significance code byte The SEND function cannot transfer data, since the transmitting capacity was already zero when the function was called.
Page 455: Send Test Function (Ob 203)
SEND TEST Function (OB 203) 10.6 SEND TEST Function (OB 203) 10.6.1 Function The SEND TEST function determines the number of free memory fields in the buffer of the COR 923C coordinator. Depending on this number m, the SEND function can be called m times to transfer m data fields.
Page 456 SEND TEST Function (OB 203) Initialization conflict Has no significance for the SEND TEST function. Errors When calling the SEND TEST function, the following error numbers (evaluation of the condition code byte) can occur: Condition Significance code byte The parameter "receiving CPU" is illegal. The following errors are possible: - The number of the receiving CPU is greater than 4, - The number of the receiving CPU is less than 1,...
Page 457: Receive Function (Ob 204)
RECEIVE Function (OB 204) 10.7 RECEIVE Function (OB 204) 10.7.1 Function The RECEIVE function takes a data field from the buffer of the COR 923C coordinator. It also indicates how many data fields are still buffered and can still be received. The RECEIVE function should be called in a loop until all the buffered data fields have been received.
Page 458: Output Parameters
RECEIVE Function (OB 204) 10.7.4 Output Parameters Condition code byte This byte informs you whether the RECEIVE function was executed correctly and completely. Initialization conflict Has no significance with the RECEIVE function. Errors When calling the RECEIVE function the following error numbers (evaluation of the condition code byte) can occur: Condition Significance...
Page 459 RECEIVE Function (OB 204) Condition Significance code byte Error numbers continued: The block number supplied by the transmitter is illegal, since it is a data block with a special significance. The following errors are possible: - If the block ID = 1 : DB 0, DB 1 - If the block ID = 2 : DX 0 The block number provided by the transmitter is incorrect.
Page 460 RECEIVE Function (OB 204) Block ID: ID = 1: DB data block ID = 2: DX data block ID = 0 or 3 to 255: illegal, causes an error message Block number Block number of the DB/DX in which the received data are stored (and from which they are taken by the SEND function in the transmitting CPU).
Page 461: Receive Test Function (Ob 205)
RECEIVE TEST Function (OB 205) 10.8 RECEIVE TEST Function (OB 205) 10.8.1 Function The RECEIVE TEST function determines the number of occupied memory fields in the buffer of the COR 923C coordinator. Depending on this number m, the RECEIVE function can be called m times to receive m data fields.
Page 462 RECEIVE TEST Function (OB 205) Errors When calling the RECEIVE TEST function, the following error numbers (evaluation of the condition code byte) can occur: Condition Significance code byte The parameter "transmitting CPU" is illegal. The following errors are possible: - The number of the transmitting CPU is greater than 4, - The number of the transmitting CPU is less than 1, - The number of the transmitting CPU is the same as...
Page 463: 10.9 Applications
Applications 10.9 Applications Based on examples, this section explains how to program multiprocessor communication. Note If you use the function blocks listed below and service interrupts on your CPU (e.g. with OB 2) remember to save the "scratchpad flags" at the start of interrupt servicing and to write them back when the interrupt is completed.
Page 464: Programming Function Blocks
Applications Note The following examples of applications involve finished applications that you can program by copying them. Programming function blocks FB 200: initializing the links FB 200 INITIAL AUMA INIC NUMC TCAP TNAS STAS Parameter Significance Parameter Data Parameter name type type field...
Page 465 Applications FB 200 continued FB 200 LEN=45 SEGMENT 1 0000 NAME:INITIAL DECL :AUMA I/Q/D/B/T/C: I BI/BY/W/D: BY DECL :NUMC I/Q/D/B/T/C: I BI/BY/W/D: BY DECL :TNAS I/Q/D/B/T/C: I BI/BY/W/D: W DECL :STAS I/Q/D/B/T/C: I BI/BY/W/D: W DECL :INIC I/Q/D/B/T/C: Q BI/BY/W/D: BY DECL :TCAP I/Q/D/B/T/C: Q...
Page 466 Applications FB 202: Sending a data field FB 202 SEND RCPU ERWA TNDB TCAP FINO Parameter Significance Parameter Data Parameter name type type field RCPU Receiving CPU FY 246 TNDB Type (H byte) and number (L byte) FW 247 of the source data block FINO Field number FY 249...
Page 467 Applications FB 203: Testing the transmitting capacity FB 203 SEND-TST RCPU ERRO TCAP Parameter Significance Parameter Data Parameter name type type field RCPU Receiving CPU FY 246 ERRO Error FY 248 TCAP Transmitting capacity FY 249 FB 203 LEN=30 SEGMENT 1 0000 NAME:SEND-TST DECL :RCPU...
Page 468 Applications FB 204: Receiving a data field FB 204 RECEIVE TCPU ERWA RCAP TNDB STAA ENDA Parameter Significance Parameter Data Parameter name type type field TCPU Transmitting CPU FY 246 ERWA Error/warning FY 248 RCAP Receiving capacity FY 249 TNDB Type (H byte) and number (L byte) of the FW 250 destination data block...
Page 469 Applications FB 204 continued: FB 204 LEN=45 SEGMENT 1 0000 NAME:RECEIVE DECL :TCPU I/Q/D/B/T/C: I BI/BY/W/D: BY DECL :ERWA I/Q/D/B/T/C: Q BI/BY/W/D: BY DECL :RCAP I/Q/D/B/T/C: Q BI/BY/W/D: BY DECL :TNDB I/Q/D/B/T/C: Q BI/BY/W/D: W DECL :STAA I/Q/D/B/T/C: Q BI/BY/W/D: W DECL :ENDA I/Q/D/B/T/C: Q BI/BY/W/D: W...
Page 470: Transferring Data Blocks
Applications FB 205 continued: FB 205 LEN=30 SEGMENT 1 0000 NAME:RECV-TST DECL :TCPU I/Q/D/B/T/C: I BI/BY/W/D: BY DECL :ERRO I/Q/D/B/T/C: Q BI/BY/W/D: BY DECL :RCAP I/Q/D/B/T/C: Q BI/BY/W/D: BY 000E =TCPU Transmitting CPU 000F FY 246 0010 0011 KB 246 SF OB: OB 205 "Test receiving capacity"...
Page 471 Applications FB 110 continued: If, however, the REST output parameter has a value greater than zero, this means that the function block must be called again, for example in the next cycle. This means that you or the user program can only change the set parameters (i.e.
Page 472 Applications FB 110 continued: Parameter Significance Parameter Data name type type STAR Start the transfer of the data block on a positive-going edge RCPU Receiving CPU TNDB Type (H byte) and number (L byte) of the data block to be transferred.
Page 473 Applications FB 110 continued: 0025 =REST First send any remaining 0026 KB 0 data fields 0027 :><F 0028 =TRAN 0029 002A =STAR Positive edge at start 002B =EDGF input ? 002C =STAR 002D =EDGF 002E =GOOD 002F =EDGF 0030 0031 =NUMB Initialize the global flags 0032...
Page 474 Applications Application of FB 110 Application of FB 110 on the S5-155U Task You want CPU 1 to transfer data blocks DB 3 ( data fields 2 to 5) and DB 4 (data fields 1 to 3) to CPU 2 during the cyclic user program. The RECEIVE function (OB 204) is also called in the cyclic user program.
Page 475 Applications Application example continued: 0009 FB 110 000A NAME :TRAN-DAT 000B STAR : I 2.0 000C RCPU : FY 0 000D TNDB : FW 1 000E NUMB : FY 3 000F FIRB : FY 4 0010 ERRO : FY 5 0011 REST : FY 6 0012 CUBN :...
Page 476: Extending The Ipcflag Area
Applications Application example continued: In CPU 2, the RECEIVE function (OB 204) called by FB 2 enters each transmitted data field into the appropriate data block. It may take several cycles before a data block has been completely received. FB 2 LEN=yy SEGMENT 1 0000...
Page 477 Applications The solution Consecutive data words of a DB or DX data block are defined from DW 0 onwards as "IPC data words". Each link is assigned its own data block and is totally independent of the other links. At the beginning of the cycle block, the IPC data words are received with the aid of the special function organization blocks for multiprocessor communication.
Page 478 Applications Structure of the link list Table 10-8 Link list for extending the IPC flag area SUB-LIST 1 SUB-LIST 2 Link DB type No. of data number fields from CPU 1 DW 0 DW 16 to ..CPU 2 DW 1 DW 17 ...
Page 479 Applications The link consists of two similarly structured sub-lists, each with 16 data words. For each of the four sender CPUs (S1, S2, S3, S4) three entries are required to describe a link. • • Number of data fields The number of data fields specifies the size (= the number of data words) of the data word area to be transferred.
Page 480: Program Structure
Applications Program structure During restart, one of the CPUs calls the INITIALIZE function (OB 200) to reserve exactly the same number of coordinator memory fields per link as data fields to be transmitted on this link. To send and receive data word areas, each CPU uses two function blocks: FB no.
Page 481: Fig. 10-6 Overview Of The Blocks Required In Each Cpu
Applications OB 20 Restart OB to reserve OB 200 must the buffer on the only be called 923C coordinator in one processor. OB 200 OB 1 Cyclic user program extended by the calls for DB xxx the RECV-DAT and SEND-DAT FB 101 function blocks.
Page 482 Applications Programming function blocks FB 100: Sending data word areas Before you call FB 100, the data block containing the link list must be open. The function block SEND-DAT requires the number of the CPU on which it is called in order to evaluate the information contained in the link list.
Page 483 Applications FB 100 continued: 0013 0014 :SLW CPUN = CPUN * 4 0015 FY 245 Base address 0016 0017 KB 1 0018 FY 244 Link counter 0019 001A LOOP :L FY 245 Base address 001B FY 244 + counter 001C 001D FW 240 001E...
Page 484 Applications FB 100 continued: 0048 EMPT :L FY 244 Increment 0049 link counter 004A FY 244 004B KB 4 links 004C :<F processed ? 004D =LOOP 004E KB 0 Regular program end: 004F =ERWA RLO = 0, ERWA = 0 0050 :BEU 0051...
Page 485 Applications FB 101 continued: FB 101 LEN=88 SEGMENT 1 0000 NAME:RECV-DAT DECL :CPUN I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KF DECL :ERWA I/Q/D/B/T/C: Q BI/BY/W/D: 000B =CPUN Error if: 000C KB 1 000D :<F 000E =ERWA CPU no. <1 000F =CPUN 0010 KB 4 0011 :>F 0012...
Page 486 Applications FB 101 continued: 0037 FY 249 Receiving capacity = number 0038 FY 243 of reserved 0039 :><F memory fields ? 003A = EMPT 003B 003C RECV :L KB 246 SF OB: OB 204 "Receive a data field" 003D 003E FY 248 003F =OBER...
Page 487: Application Example
Applications Application example Application of FB 100/101 on the S5-155U Task You want to exchange data between three CPUs: From CPU 1 to CPU 2: data block DB 3, DW 0 to DW 127 (= 4 data fields) From CPU 1 to CPU 3: data block DX 4, DW 0 to DW 63 (= 2 data fields) From CPU 2 to CPU 1 and CPU 3:...
Page 488 Applications Application example continued: Implementation 1. Loading blocks The following blocks must be loaded in the indivitual CPUs: Function CPU 1 CPU 2 CPU 3 Restart OB OB 20 — — User program FB: SEND-DAT FB 100 FB 100 FB 100 FB: RECV-DAT FB 101 FB 101...
Page 489 Applications Application example continued: – – Sub-list 1 – – KS = ’S1’; Send from CPU 1 to .. KY = 002,004; .. CPU 2 (four data fields) KY = 003,002; .. CPU 3 (two data fields) KY = 004,000; KS = S2’;...
Page 490 Applications Application example continued: 4. Program calls for the function blocks in FB 1 of the CPUs: The user program on each CPU is extended by the RECV-DAT and SEND-DAT call. Function block FB 1 shown below is for CPU 1. For the other CPUs, the input parameter CPUN (CPU number) must be modified.
Page 491: Pg Interfaces And Functions
PG Interfaces and Functions Contents of Chapter 11 11.1 Overview ............. . 11 - 4 11.2 PG Functions.
Page 492 11.5 PG Functions via the S5 Bus ..........11 - 27 11.5.1 Application .
Page 493 PG Interfaces and Functions This chapter explains how to connect your PG to the CPU 948 and the functions provided by the PG software with which you can test your STEP 5 program. If you only use the standard PG interface (1st serial PG interface) you do not need to read Sections 11.4 and 11.5.
Page 494: 11.1 Overview
11.1 Overview You can load and test your user program using the online functions of the STEP 5 software. To use these functions, the CPU must be connected to the PG. The following interfaces are available for this link: • • link via the serial standard interface "PG - PLC", •...
Page 495: 11.2 Pg Functions
11.2 PG Functions Note The terms used in this section for the PG functions may in some cases differ from the terms in your PG software. Please refer to your STEP 5 manual. Calling and using functions How to call and use the individual PG functions is described in the manual for your PG.
Page 496: Info
11.2.1 Info Memory configuration The CPU 948 is available with two memory versions and you can check the memory capacity using the PG function "memory configuration". With this function, the following information about the CPU user memory is transferred to the PG (from PG software version V6.0 upwards with "Delta diskette"...
Page 497: Installation
Output DIR If you want to display a list of all the programmed blocks on the PG with the CPU 948, OB 0 is displayed instead of the system program blocks. The function is permitted in the operating modes RUN, SOFT STOP, HARD STOP and can also be called within the "program test"...
Page 498: Program Test
Transfer block With this function you can transfer new or existing logic and data blocks to the user memory of the CPU. If a block already exists in the user memory of the CPU, it is declared invalid and the new block becomes valid. Delete block With this function you declare a logic or data block in the user memory as invalid.
Page 499 Status block You can call the "status" PG function to test related operational sequences (STEP 5 operations) in one block at any location in the user program. The current signal status of operands, the accumulator contents, and the RLO are output on the PG screen for every executed operation in the block (i.e., step mode).
Page 500 Older PG software versions If you move the cursor quickly in the "status block" function with older PG software versions, each cursor movement means a wait of 3 to 5 seconds. Remedy: Cancel the status with the abort key, reposition the cursor and then continue the status function again.
Page 501 Calling test functions in SOFT You can also call the "program test" function and specify an initial STOP breakpoint when the CPU is in the soft STOP mode. The CPU remains in the soft STOP mode, and you can execute either a COLD RESTART or a MANUAL WARM RESTART.
Page 502: Fig. 11-2 Sequence Of "Program Test
Nesting with "interruptability While the "program test" function is running, the other program at operation boundaries" execution levels can be activated, if the mode "interruptability at operation boundaries" is set. When an operation has been processed at a breakpoint and a different program execution level is called at this point (e.g.
Page 503 • • Program processing → STOP mode: Interruptions If an interruption occurs during program processing (e.g., multipro- cessor stop, I/O not ready/STOP, error OB not programmed etc.) before the program reaches the specified breakpoint, the CPU goes into the STOP mode immediately. If you execute a COLD REST- ART or a MANUAL WARM RESTART, the "program test"...
Page 504 Status variables Using the "status variables" function, you can display the current signal states of certain operands (process variables). When a checkpoint is reached, the PG displays the present signal status of the desired process variable. You can display the following process variables: inputs, outputs, flags, timers, counters and data words.
Page 505 The peripheral outputs are forced byte by byte. In multiprocessor operation, you can force all peripheral outputs (regardless of the peripheral assignment in DB 1). Timeout errors that occur are detected when outputs are changed (PG message "I/O module does not exist"). Terminating the function You can terminate the function by pressing the <BREAK>...
Page 506: 11.3 Serial Link Pg - Plc Via 1St Or 2Nd Serial Interface
11.3 Serial Link PG - PLC via 1st or 2nd Serial Interface For the serial link PG - PLC there are the following possibilities: • • Direct link to the CPU via the standard cable. • • Link to the PG via the coordinator COR C. In this case the PG is connected via the cable to the coordinator.
Page 507: Parallel Operation Of Two Serial
11.4 Parallel Operation of Two Serial PG Interfaces You can use the second interface on the CPU 948 (SI 2) as a PG interface in exactly the same way as the first interface. To be able to link your PG via this interface, you must also order the PG interface module in addition to your CPU 948 (the order number is listed in the system manual 135U/155U /2/).
Page 508: Examples Of Configurations
Examples of configurations CP 143 CPU 948 PG connected via SINEC H1 and COR C PG connected directly "swing cable" SINEC H1 Fig. 11-4 First example of a configuration CPU 948 SI 1 OP connected directly (for operation and monitoring) SI 2 PG connected directly (for programming)
Page 509: Installation
11.4.1 Installation To use the second interface of the CPU 948 as a PG interface, follow the steps outlined below: Step Action Install the PG submodule in the CPU 948. (refer to the instructions in the Appendix) Connect the PG to the serial interface SI2. 11.4.2 Operation If you use the second interface as a PG interface then initially the full...
Page 510 The table below lists the pairs of functions that you cannot work with simultaneously. Table 11-2 Functions which cannot run simultaneously on both PGs Function active You must not activate this on the first PG: function on the second PG "Force"...
Page 511: Sequence In Certain Operating Situations
11.4.3 Sequence in Certain Operating Situations Parallel operation with If you work with PGs on both interfaces simultaneously, both PGs short-running functions want to execute their functions independently of each other. As long as they stagger the jobs they send to the CPU, the jobs will be processed in the order in which they arrive.
Page 512: Fig. 11-7 Typical Sequence Of A Cyclic Function And Parallel Short-Running Function
Parallel operation with The long-running functions "force" and ""program test" cannot long-running functions interrupt other functions and cannot be interrupted by other functions. They can therefore not be executed parallel to other functions, i.e. they are treated as a standard job "en bloc". Parallel operation with Cyclic functions can be executed both parallel to other cyclic and to cyclic functions...
Page 513 To allow a second PG to send a job to the CPU, the status function is interrupted between two requests and then continued on completion of the inserted job. Since the interrupting function requires CPU facilities, the whole CPU system facilities must be divided between the two functions, e.g.
Page 514: Fig. 11-8 Sequence Of Two Parallel Cyclic Functions
User on PG 2 CPU 948 User on PG 1 PG 1 informs the CPU of the variables to be output. PG 1 requests the current data. PG 1 requests the current data. PG 2 sends the first job PG 2 must wait until the CPU is free.
Page 515 Special feature with cyclic If the interrupting function blocks the CPU 948 ("status" in a block functions on both PGs that is not executed) the interrupted function is also blocked. It can only be resumed when the interrupting function is terminated. When working simultaneously with two PGs, the following sequence results: User on PG 1...
Page 516: 11.5 Pg Functions Via The S5 Bus
11.5 PG Functions via the S5 Bus 11.5.1 Application The PG functions via the S5 bus allow you to load and control S5-155U programmable controllers with the CPU 948 connected via SINEC H1 using the PG 7xx. With the PG functions via the S5 bus, the CPU 948 can be loaded up to eight times faster than via the PG interface.
Page 517 Fig 11-10 shows a typical configuration for the multiprocessor mode. S5-155U PG 7xx Bus coupler Bus coupler SINEC H1 Fig. 11-10 Multiprocessor mode with a CP 143 (2 x CPU 948, 1 x CP 143) No parameter assignment No parameter assignment is necessary on the CPU 948 to use the PG for the CPU functions via the S5 bus.
Page 518: How The Pg Functions Work Via The S5 Bus
11.5.2 How the PG Functions Work via the S5 Bus Using pages For communication with the CPUs, the CP 143 has four pages (interfaces). If you do not use the PG functions via the S5 bus, all the pages are available for communication using handling blocks (HDBs). When using the S5 bus functions, the pages of the CPU are divided into two pages for user HDBs and two pages for PG functions.
Page 519 Parameters for the CP 143 Assigning parameters for the CP 143 is described in the CP 143 manual (Further Reading /6/). Caution The interface numbers 232ff and 236ff must not be assigned on the CP 143 when operating with other SIMATIC CPUs. When operating the CPU 948 with other CPs, the use of interface numbers 232 to 247 is restricted.
Page 520: Installation And Getting Started
11.5.3 Installation and Getting During installation, remember the following alternatives. Started The CP 143 is used If the CP 143 is used exclusively for PG functions via the S5 bus, no exclusively for further parameters other than the SINEC H1 parameters must be set. PG Functions After POWER UP, the PG functions are always available on CPU 948 via the S5 bus without the CP 143 previously being synchronized with...
Page 521 Step Action Load the parameter data on the CP 143: The parameter data of the CP 143 can either be stored in an EPROM cartridge in the RAM of the CP 143. You can transfer the parameter data via the serial interface of the PG 7xx. The operations necessary for loading the parameter data of the CP 143 are described in /6/.
Page 522 The CP 143 is used for PG If you use the CP 143 for communication via SINEC H1 as well as for Functions and PG functions via the S5 bus, you must make further settings in Communication via addition to those described in Section 3.1 and must take certain special SINEC H1 features into account.
Page 523 1st CP 143 CPU 1 SSNR Page for user CPU 948 SSNR Page for user CPU 2 SSNR Page for functions CPU 948 SSNR Page for functions 2nd CP 143 CPU 3 SSNR Page for user CPU 948 SSNR Page for user CPU 4 End point...
Page 524: Condition Codes Indicating Problems
11.5.4 Condition Codes Indicating Each of the maximum four CPUs (CPU 948), for which the PG Problems functions via the S5 bus are activated, writes condition codes to its RS and RT areas if an error occurs in the PG functions via the S5 bus. These condition codes consist of a parameter assignment error byte (PAFE) for each possible connection and a condition code word (ANZW) to indicate the current sequence of the transmit and receive...
Page 525 Meaning of the code 71H: The code 71H means that the page does not exist. If this error occurs, the PG functions cannot be used via the S5 bus. In this case, check the interface assignment of the CP 143. Interface numbers 232ff or 236ff must be set (jumpers and SYSID!).
Page 526 Note The RT area is reset during an OVERALL RESET. If you use the PG functions via the S5 bus, the RT area is occupied as described above and is then no longer available for other programs (e.g. standard FBs). You should bear this in mind when planning your system.
Page 527: Appendix
Appendix Contents of Chapter 12 Appendix 1: Jumper Settings for System Interrupts........12 - 4 Appendix 2: Inserting and Removing the PG Submodule .
Page 528 Appendix This chapter provides additional information about the CPU 948 such as jumper settings for system interrupts, notes on inserting and removing the PG submodule, comparisons of runtimes with CPU 946/947 and CPU 928B, and results IDs of some of the special function OBs .
Page 529: Appendix 1: Jumper Settings For System Interrupts
Appendix 1: Jumper Settings for System Interrupts For interrupt-controlled program execution with the CPU 948, there are four system interrupts available, as follows: INT A/B/C/D (dependent on the CPU slot, see System Manual /2/, INT E, INT F INT G. The interrupts you want to use must be enabled using jumpers.
Page 530: Appendix 2: Inserting And Removing The Pg Submodule
Appendix 2: Inserting and Removing the PG Submodule If you want to use a PG submodule, this must first be added to the CPU (before the CPU is installed in the central controller). Caution Switch off the power supply to the programmable controller before you remove the CPU.
Page 531 Removing the submodule You remove the PG submodule as follows: Step Action Switch off the power supply to your PLC. Remove the CPU from the central controller. Undo the two screws securing the submodule and remove the submodule from the receptacle. Insert a further submodule (as described above) or close the submodule receptacle with the cover.
Page 532: Appendix 3: Technical Data Of The Cpu 948, Cpu 946/947 And Cpu 928B
Appendix 3: Technical Data of the CPU 948, CPU 946/947 and CPU 928B Operation / Processing CPU 948 CPU 946/947 CPU 928B Typical command execution times for bit commands: with 0.18 µ s 1.4 µ s 0.57 µ s F, I, Q 0.7 µ...
Page 533 Operation / Processing CPU 948 CPU 946/947 CPU 928B 11.6 µ s 4.4 µ s 20 µ s timer block length #0 + TBL* 0.32 µ s + TBL * 1.3 µ s + TBL * 1 µ s n = number of timers running (steps: 10 ms) (no difference between...
Page 534 Operation / Processing CPU 948 CPU 946/947 CPU 928B Resolution for delayed interrupt (OB 6) 1 ms – 1 ms Cycle time monitoring Default 200 ms 200 ms 150 ms selectable between 1 to 2550 ms 1 to 2550 ms 1 to 13000 ms triggerable Memory sizes...
Page 535: Appendix 4: Results Ids Of Some Of The Special Function Obs In Accu
Appendix 4: Results IDs of some of the Special Function OBs in ACCU 1 Byte IDs in Some of the byte IDs are used by several special function OBs. Their ACCU-1-LL significance therefore depends on the OB called. SF-OB ACCU-1-LL Meaning OB 124 Function processed correctly...
Page 536 SF-OB ACCU-1-LL Meaning OB 254/ Function processed correctly Errors: Block header on memory card invalid Not enough memory Source data block does not exist Block number or type illegal/source DB Block number or type illegal/destination DB Destination data block already exists in user memory Online function COMPRESS MEMORY active...
Page 537: Word Ids In Accu-1-L
Word IDs in Word results IDs are only used once (with one exception). The ACCU-1-L following table is therefore sorted according to ID values. ID in ID from Meaning ACCU-1-L SF OB: 8D01H OB 141 Illegal function no. in ACCU-2-L 8D02H One of the reserved bits in ACCU 1 is ’1’...
Page 538 ID in ID from Meaning ACCU-1-L SF OB: 9701H OB 151 Data block not loaded 970FH Block called more than once 9710H Wrong mode ("process interrupts via IB 0 = on") 9711H Illegal function no. 9712H Address area type illegal 9713H Data block no.
Page 539 ID in ID from Meaning ACCU-1-L SF OB: B629H OB 182 Length of destination data block in block (cont.) header< 5 words B62AH "Number of data words to be transferred" illegal (= 0 or > 4091) B62BH Source data block too short B62CH Destination data block too short F001H...
Page 540: Further Reading
Further Reading CPU 948 Programming Guide 13 - 1 C79000-A8576-C848-03...
Page 541 6ES5 998-1SA01 Handling Blocks Standard Function Blocks CPU 948 Order no. C79000-G8563-C572 SINEC Manual CP 143 with COM 143 Order no. 6GK1970-1AB43-0AB0 Hans Berger: Automating with the SIMATIC S5-155U SIEMENS AG ISBN 3-8009-1538-3 CPU 948 Programming Guide 13 - 3 C79000-A8576-C848-03...
Page 542 Programmable Controllers Basic Concepts SIEMENS AG Order no. E80850-C293-X-A2 Catalog ST 59: Programmers SIMATIC S5 /10/ Catalog ST 54.1: Programmable Controllers S5-135U, S5-155U and S5-155H /11/ Catalog ST 57: Standard Function Blocks and Driver Programs for Programmable Controllers of the U Series...
Page 543: Indexes
Indexes Contents of Chapter 14 List of Abbreviations ........... . 14 - 3 List of Key Words.
Page 544: List Of Abbreviations
List of Abbreviations Abbreviations (An explanation of the ISTACK abbreviations can be found in Section 5.4) ACCU-1 (2, 3, 4)-L low word in accumulator 1 (2, 3, 4), 16 bit ACCU-1 (2, 3, 4)-H high word in accumulator 1 (2, 3, 4), 16 bit ACCU-1 (2 ,3, 4)-LL low byte of low word in accumulator 1 (2, 3, 4), 8 bit ACCU-1 (2, 3, 4)-LH...
Page 545 call for a non-existent logic block opening a non-existent DB/DX-data block ladder diagram light-emitting diode power failure organization block or (bit code) overflow latching (word code) overflow (word code) PAFE parameter assignment error byte PARE parity error program block power failure on expansion unit programmer process image process image of the inputs...
Page 546: List Of Key Words
COLD RESTART 4-24 List of Key Words collision of timed interrupts 4-43 communication OBs 10-22 condition code byte 10-25 parameters 10-23 ERAB runtimes 10-31 see results codes communication processors (CPs) 10-7 comparison operations 3-32 control bits 5-5, 5-9 correcting blocks 2-15 counter value 3-28...
Page 547 decrementing 3-66 defaults, modifying delay interrupts 6-32, 6-35 delayed interrupt 1-21, 4-33, 4-37 - 4-38, 6-50 I/Os digital logic operations 3-50 modules 1-12 disable interrupts 6-11, 6-29 O area 1-12 dual-port RAM 9-29 P area 1-12 incrementing 3-66 interface to system program 1-9, 1-11, 2-18 interprocessor communication flags error analysis...
Page 548 memory organization mode of operation of CPU multiprocessor communication 6-62 application examples 10-53 P area assignment list 10-37 see I/Os buffering data 10-17 page area/DPR data amount 10-15 occupied register 9-30 initializing 10-33 pages modes 10-35 accessing 9-29 receive data 10-47 parameters for DX 0 send data...
Page 549 see also function blocks START-UP 3-11 general 3-11, 4-4, 4-19 QVZ (timeout error) 5-25 interruptions 4-31 triggering 4-20, 4-22 start-up types comparing 6-64 starting up 10-13 reaction time 4-50 STEP 5 operations 3-15 reactions with error OBs not loaded 5-21 STL (statement list) real-time clock 8-32...
Page 550 user interfaces for clock-controlled interrupt 4-39 for cyclic program execution 4-35 for delayed interrupt 4-38 for interrupts 4-48 for process interrupts 4-45 for start-up 4-27 for timed interrupts 4-42 user memory 1-15, 3-10 user program 1-8, 1-10 processing 3-4, 3-11 see program storing 1-11...
Page 551: List Of Tables And Figures
List of Tables and Figures List of Tables Table 2-1 Overview of the organization blocks of the CPU 948 for program execution..2 - 19 Table 2-2 Overview of the organization blocks of the CPU 948 for start-up....2 - 20 Table 2-3 Organization blocks of the CPU 948 for a SOFT STOP .
Page 552 Table 3-12 Digital logic operations........... 3 - 50 Table 3-13 Bit test operations .
Page 553 Table 4-7 User interfaces for process interrupts ........4 - 45 Table 4-8 User interfaces for interrupts .
Page 554 Table 6-15 Error IDs of OB 153 ........... . . 6 - 51 Table 6-16 Error IDs of OB 180 .
Page 555 Table 8-16 Structure of RS 99 (real-time clock: year, month) ......8 - 34 Table 8-17 Assignment of RS 120 (software protection) when writing.
Page 556 Table 10-6 Runtimes of the communication OBs........10 - 31 Table 10-7 Assignment list for OB 200 (initialize) .
Page 557: List Of Figures
List of Figures Fig. 1-1 Example of application of the S5-155U with the CPU 948 ......1 - 5 Fig.
Page 558 Fig. 4-5 Program execution after a cycle interruption ........4 - 14 Fig.
Page 559 Fig. 9-3 LIR/TIR with 16-bit memory areas (word-oriented) ......9 - 10 Fig. 9-4 LIR/TIR with 8-bit memory areas (byte-oriented) .
Page 560 Fig. 11-10 Multiprocessor mode with a CP 143 (2 x CPU 948, 1 x CP 143) ..........11 - 28 Fig.
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