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SIMATIC S5-155U CPU 948
Siemens SIMATIC S5-155U CPU 948 Manuals
Manuals and User Guides for Siemens SIMATIC S5-155U CPU 948. We have
1
Siemens SIMATIC S5-155U CPU 948 manual available for free PDF download: Programming Manual
Siemens SIMATIC S5-155U CPU 948 Programming Manual (562 pages)
Brand:
Siemens
| Category:
Controller
| Size: 2 MB
Table of Contents
Disclaimer of Liability
2
How to Use this Manual
3
Overview of the Chapters
4
Reference Tables
8
Operation
8
Table of Contents
9
Introduction
16
Contents of Chapter 1
17
Area of Application for the S5-155U with the CPU 948
18
Example of Application
19
Typical Mode of Operation of a CPU
20
The Programs in a CPU
22
System Program
22
User Program
25
Which Operands Are Available to the User Program
26
How Much Memory Is Available for the User Program
29
How to Tackle Programming
30
Programming Tools
33
What Is New with the CPU 948
34
CPU 948, Version A01
34
CPU 948, Version A02
37
CPU 948, Version A03 and Higher
37
Converting User Programs of the CPU 928B for the CPU 948
38
Organization Blocks
40
User Program
42
STEP 5 Programming Language
44
The LAD, CSF, STL Methods of Representation
44
Structured Programming
45
Fig. 2-1 Methods of Representation in the STEP 5 Programming Language
45
STEP 5 Operations
46
Number Representation
48
STEP 5 Blocks and Storing Them in Memory
52
Block Types
52
Fig. 2-2 Example of Block Storage in the User Memory
55
Program, Organization and Sequence Blocks
56
Block Calls
56
Fig. 2-3 Block Calls that Enable Processing of a Program Block
57
Organization Blocks as User Interfaces
58
Table 2-1 Overview of the Organization Blocks of the CPU 948 for Program Execution
59
Table 2-2 Overview of the Organization Blocks of the CPU 948 for Start-Up
60
Table 2-3 Organization Blocks of the CPU 948 for a SOFT STOP
60
Table 2-4 Overview of the Organization Blocks of the CPU 948 for Error Handling
60
Organization Blocks for Special Functions
62
Table 2-5 Overview of the Organization Blocks of the CPU 948 for Special Functions
62
Function Blocks
63
Structure of Function Blocks
64
Fig. 2-4 Structure of a Function Block (FB/FX)
64
Programming Function Blocks
66
Table 2-5 Permitted Formal Operands for Function Blocks
67
Calling Function Blocks and Assigning Parameters to Them
68
Table 2-6 Permitted Actual Operands for Function Blocks
69
Special Function Blocks
73
Data Blocks
75
Block Header
76
Maximum Length
76
Creating Data Blocks
77
Table 2-7 Data Formats Permitted in a Data Block
77
Opening Data Blocks
78
Special Data Blocks
81
Fig. 2-5 Range of Validity of an Opened Data Block
81
Program Execution
83
Principle of Program Execution
86
Fig. 3-1 Principle of Cyclic Program Execution
86
Program Organization
87
Fig. 3-2 Example of the Organization of the User Program According to the Program Structure
88
Fig. 3-3 Example of the Organization of the User Program According to the Structure of the
89
Fig. 3-4 Nested Logic Block Calls
90
Fig. 3-5 Example of Block Nesting Depth
91
Storing Program and Data Blocks
92
Processing the User Program
93
Definition of Terms Used in Program Execution
94
Interrupt Events
96
STEP 5 Operations with Examples
97
Condition Codes
98
Table 3-1 Result Condition Codes of STEP 5 Operations
100
Basic Operations
101
Binary Logic Operations
101
Table 3-2 Binary Logic Operations
101
Set/Reset Operations
102
Table 3-3 Set/Reset Operations
102
Load and Transfer Operations
103
Load Operations
104
Fig. 3-6 Load and Transfer Operations in a Byte-Oriented Memory Area
105
Fig. 3-7 Load and Transfer Operations in a Word-Oriented Memory Area
106
Timer and Counter Operations
108
Table 3-6 Timer and Counter Operations
108
Counter Value
110
Arithmetic Operations
113
Table 3-7 Arithmetic Operations
113
Comparison Operations
114
Block Operations
114
Table 3-8 Comparison Operations
114
Table 3-9 Block Operations
114
Nop/Display/Stop Operations
115
Table 3-10 Nop/Display/Stop Operations
115
Programming Examples in the STL, LAD and CSF Methods of Representation
116
Logic Operations
116
Programming Examples in the STL, LAD and CSF Methods of Representation
119
Timer Operations
122
Counter Operations
126
Supplementary Operations
131
Binary Logic Operations
132
Digital Logic Operations
132
Table 3-11 Binary Logic Operations with Formal Operands
132
Table 3-12 Digital Logic Operations
132
Bit Test Operations
133
Table 3-13 Bit Test Operations
133
Set/Reset Operations
134
Table 3-14 Set/Reset Operations with Formal Operands
134
Table 3-15 Set and Reset Operations
134
Timer and Counter Operations
135
Load and Transfer Operations
137
Table 3-18 Load and Transfer Operations with Special Operands
138
Table 3-19 Arithmetic Operation ENT
139
Table 3-20 Supplementary Arithmetic Operations
140
Executive Operations
141
Table 3-21 Jump Operations
141
Table 3-22 Shift Operations
143
Table 3-23 Conversion Operations
145
Conversion Examples
147
Table 3-24 Decrement/Increment Operation
148
Table 3-25 Processing Operations
148
Table 3-26 I/O Operations
154
Table 3-27 Other Operations
154
Table 3-28 Meaning of the Abbreviations in UAMW
155
Semaphore Operations
157
Table 3-29 Disable/Enable Semaphore
157
Fig. 3-8 Coordination of Access to the Global Memory
158
Main Program
160
Operating Statuses and Program Execution Levels
163
Introduction and Overview
166
Fig. 4-1 Front Panel of the CPU 948 with Display and Operating Elements
166
Table 4-1 Meaning of the Leds "RUN" , "STOP" and "SYSFAULT
167
Program Execution Levels
169
Fig. 4-2 Program Execution Levels
169
Fig. 4-3 Principle of Changing Level and the ISTACK
173
STOP Mode
174
Soft Stop
174
Fig. 4-4 Program Execution after POWER up
176
Fig. 4-5 Program Execution after a Cycle Interruption
176
Hard Stop
178
Led Displays
178
Overall Reset
179
Overall Reset
180
START-UP Mode
181
MANUAL and AUTOMATIC COLD RESTART
182
MANUAL and AUTOMATIC WARM RESTART
183
Comparison between COLD RESTART and WARM RESTART
186
Retentive Cold Restart
187
Comparison of COLD RESTART and RETENTIVE COLD RESTART
188
User Interfaces for Start-Up
189
Extended AUTOMATIC WARM RESTART with the CPU 948 (HOT RESTART)
192
Interruptions During START-UP
193
RUN Mode
195
Timed Interrupts
195
Cyclic Program Execution
196
Interrupt-Driven Program Execution
198
Specifying Time and Interrupt-Driven Program Execution
198
Time-Controlled Program Execution
199
Delayed Interrupt
200
Clock-Controlled Interrupt
201
Cyclic Timed Interrupts
203
Table 4-5 Sets of Intervals and Intervals of the TIMED INTERRUPTS
203
Table 4-6 Timed Interrupt Collision Ids: Meaning of the Bits in ACCU-1-L
205
Interrupt-Driven Program Execution
207
User Interfaces
207
INTERRUPTS Via Signal Lines of the S5 Bus
209
Fig. 4-7 Position of the Jumper Plug for Setting Interrupts
209
Table 4-8 User Interfaces for Interrupts
210
Disabling Interrupt-Driven Processing
211
Reaction Time
212
Program Execution Levels and Flags
212
Interrupt and Error Diagnostics
214
Frequent Errors in the User Program
215
Error Information
216
Procedure for Error Analysis
219
Control Bits and Interrupt Stack
220
Control Bits
221
Fig. 5-1 Example of the First Screen Form Page "OUTPUT ISTACK": Control Bits
221
Table 5-1 Meaning of the Control Bits SYSTEM DESCRIPTION
222
Table 5-2 Meaning of the Control Bits STOP CAUSE
222
Table 5-3 Meaning of the Control Bits START-UP IDS
223
Table 5-4 Meaning of the Control Bits ERROR IDS
224
ISTACK Content
225
Fig. 5-2 Example of a Screen Page "OUTPUT ISTACK
225
Table 5-5 Meaning of the ISTACK Ids for Errors
226
Table 5-6 ISTACK Ids CAUSE of INTERRUPTION
228
Warm Restart
229
Example of Error Diagnosis Using the ISTACK
230
Fig. 5-3 Example of Evaluating the ISTACK
230
Error Handling Using Organization Blocks
231
Table 5-7 the Organization Blocks Called in Case of Errors
231
Causes of Error and Reactions of the CPU
234
OB 19: Calling a Logic Block that Is Not Loaded (KB)
235
OB 19: Calling a Data Block that Is Not Loaded (KDB)
235
OB 23/24, ob 28/29:Timeout Error (QVZ)
236
OB 23/24, ob 28/29: Timeout Error (QVZ)
236
OB 25: Addressing Error (ADF)
237
OB 26: Cycle Time Exceeded Error (ZYK)
238
OB 27: (Substitution Error SUF)
239
OB 30: Parity Error and Timeout Error in the User Memory (PARE)
239
OB 32: Load and Transfer Error (TRAF)
240
OB 33: Collision of Timed Interrupts Error (WEFES/WEFEH)
241
Queue Overflow
241
OB 34: Error with G DB/GX DX (FEDBX)
243
OB 35: Communication Errors
243
OB 36: Error in Self-Test
244
Self-Test
245
Overview
245
What Is Tested
245
Description of the Test Functions
246
Settings
248
Error Handling
249
Overall Reset
249
Integrated Special Functions
252
Introduction
255
OB121: Set/Read System Time
255
Error Handling
257
OB 121: Set/Read System Time
258
Possible Errors
259
Table 6-2 Error Ids of ob 121 in ACCU-1-L
259
OB 122: "Disable Interrupts" On/Off
262
Table 6-3 Error Ids of ob 122 in ACCU-1-L
263
OB 124: Delete STEP 5 Blocks
264
Table 6-5 Result Ids of ob 124 in ACCU-1-LL
266
OB 125: Generate STEP 5 Blocks
267
Table 6-7 Result Ids of ob 125 in ACCU-1-LL
269
OB 126: Define, Transfer Process Images
270
Block Number
271
Table 6-8 Result Ids of ob 125 in ACCU-1-LL
272
OB 129: Battery State
275
OB 131: Delete Accus 1, 2, 3 and 4
276
OB 132/133: Roll-Up Accu/Roll-Down ACCU
277
6.10 ob 141: "Disable Single Cyclic Timed Interrupts" On/Off
279
Table 6-9 Error Ids of ob 141 in ACCU-1-L
281
6.11 ob 142: "Delay All Interrupts" On/Off
282
Table 6-10 Error Ids of ob 142 in ACCU-1-L
284
6.12 ob 143: "Delay Single Cyclic Timed Interrupts" On/Off
285
Table 6-11 Error Ids of ob 143 in ACCU-1-L
287
6.13 ob 150: Set/Read System Time
288
OB 150: Set/Read System Time
290
Table 6-12 Error Ids of ob 150 in ACCU-1-L
291
6.14 ob 151: Set/Read Time for Clock-Controlled Interrupt
293
Table 6-13 Error Ids of ob 151 in ACCU-1-L
296
6.15 ob 153: Set/Read Time for Delayed Interrupt
300
6.16 ob 180: Variable Data Block Access
303
Fig. 6-3 Shifting the DB Start Address
306
OB 181: Test Data Blocks (DB/DX)
307
Table 6-17 Error Codes of ob 181 and Their Scans
308
6.18 ob 182: Copy Data Area
309
Table 6-18 Error Ids of ob 182 in ACCU-1-L
311
6.19 ob 202 to 205: Multiprocessor Communication
312
6.20 ob 222: Restart Cycle Monitoring Time
313
6.21 ob 223: Compare Start-Up Modes
314
6.22 ob 254/255: Copy/Duplicate Data Blocks
315
Application
315
Table 6-21 Result Ids for ob 254/255 in ACCU-1-LL
318
Contents of Chapter
319
Structure of DX 0
319
Example of Input in DX 0
319
Parameters for DX 0
319
Table 7-1 DX 0 Parameters and Their Meaning
325
Examples of Parameter Assignment
329
STEP 5 Programming
329
Parameter Assignment Using the PG Screen Form
331
Memory Assignment and Memory Organization
335
Structure of the Memory Area
337
Memory Assignment in the CPU 948
338
Fig. 8-1 Memory Assignment in CPU 948/Overview
338
Memory Assignment for the Peripherals
341
Fig. 8-4 Address Areas for Peripherals (8 Bits) on the S5 Bus
341
User Memory Organization in the CPU 948
343
Fig. 8-5 Example: Location of Blocks in Memory
344
Block Address List in Data Block DB 0
346
RI/RJ Area
347
RS/RT Area
348
Table 8-2 Assignment of the RS Area
349
Bit Assignment of the System Data Words
351
Table 8-4 Bits of RS 1 (Current Process Interrupts)
352
Table 8-5 Bits of RS 5 (Cycle Time)
353
Table 8-6 Bits of RS 7 (PLC Stop Ids)
354
Table 8-7 Bits of RS 8 (Start and Start-Up Ids)
355
Table 8-8 Bits of RS 16 (Error Area Output Bytes 0 to 15)
356
Table 8-9 RS 75: General Errors
359
Table 8-11 RS 75: Error Codes of the Self Test Functions
361
Table 8-12 RS 76 to RS 78: Parameter Types
362
Table 8-13 Structure of RS 96 (Real-Time Clock: Seconds, 1/100 Seconds)
365
Table 8-14 Structure of RS 97 (Real-Time Clock: Hours, Minutes)
366
Table 8-15 Structure of RS 98 (Real-Time Clock: Date, Day of the Week)
366
Table 8-16 Structure of RS 99 (Real-Time Clock: Year, Month)
367
Table 8-18 Assignment of RS 120 (Software Protection) When Reading
370
Table 8-20 Bits of RS 253 (List of Interface Modules Plugged In)
374
Addressable System Data Area
375
Memory Access Using Absolute Addresses
379
Introduction
379
Memory Access Via Address in ACCU 1
379
Local Memory
381
Fig. 9-1 Global and Local Memory
382
Memory Access
383
Fig. 9-2 Access to Local or Global Areas Using Absolute Addresses
384
Table 9-1 Operations for Indirect Memory Access Using Registers
385
LIR/TIR: Loading to or Transferring from a 16-Bit Memory Area Indirectly
386
Table 9-2 16-Bit Register for LIR/TIR
386
Fig. 9-3 LIR/TIR with 16-Bit Memory Areas (Word-Oriented)
387
Fig. 9-4 LIR/TIR with 8-Bit Memory Areas (Byte-Oriented)
387
Fig. 9-5 Using the DBA Register
389
Fig. 9-6 Using the DBL Register
391
LDI/TDI: Loading to or Transferring from a 32-Bit Memory Area Indirectly
394
Transferring Memory Blocks
396
Table 9-4 Operations for Field Transfer
396
Table 9-5 Memory Areas Permitted for TNW, TXB and TXW
396
Fig. 9-7 Transferring Memory Fields
398
Operations with the Base Address Register (BR Register)
399
Table 9-6 Load and Arithmetic Operations with the BR Register
399
Operations for Transfer between Registers
400
Table 9-7 Register-Register Operations
400
Accessing the Local Memory
401
Table 9-8 Operations for Accessing the Local Memory
401
Fig. 9-8 Transfer Operations from One Register to Another
401
Accessing the Global Memory
402
Table 9-9 Operations for Access to the Global Memory Organized
404
Accessing the Dual-Port RAM Memory
406
Table 9-11 Operations for Access to Pages Organized in Bytes
408
Table 9-12 Operations for Access to Pages Organized as Words
410
Multiprocessor Mode and Communication in the S5-155U
411
10.1 Multiprocessor Mode
414
When to Use the Multiprocessor Mode
414
What Communications Mechanisms Are Available
414
Exchanging Data Via IPC Flags
415
Fig. 10-1 Transferring IPC Flags in the Multiprocessor Mode
416
Exchanging Data Via Handling Blocks
418
What Needs to be Programmed for the Multiprocessor Mode
419
How to Create Data Block DB 1
419
Starting up in the Multiprocessor Mode
423
Test Mode
424
10.2 Multiprocessor Communication
425
Introduction
425
How the Transmitter and Receiver Are Identified
426
Why Data Is Buffered
427
How the Buffer Is Processed and Managed
428
Data Protection
428
Fig. 10-5 Example of the Occupation of the COR Buffer
429
System Start-Up
431
Cold Restart
431
Calling Communication Obs
432
How to Assign Parameters to Communication Obs
433
How to Evaluate the Output Parameters
434
Table 10-1 Condition Codes of the Communication Obs
435
Table 10-2 Code Byte for the Communication Obs/Number Groups
436
Table 10-3 Condition Code Byte: Initialization Conflict Numbers
437
Table 10-4 Condition Code Byte: Error Numbers
438
Table 10-5 Condition Code Bytes: Warning Numbers
440
10.3 Runtimes of the Communication Obs
441
INITIALIZE Function (ob 200)
443
Function
443
Call Parameters
445
Input Parameters
445
Output Parameters
448
SEND Function (ob 202)
450
Function
450
Call Parameters
450
Input Parameters
450
Output Parameters
452
SEND TEST Function (ob 203)
455
Function
455
Call Parameters
455
Input Parameters
455
Output Parameters
455
RECEIVE Function (ob 204)
457
Function
457
Call Parameters
457
Input Parameters
457
Output Parameters
458
RECEIVE TEST Function (ob 205)
461
Function
461
Call Parameters
461
Input Parameters
461
Output Parameters
461
10.9 Applications
463
Calling the Special Function ob Using Function Blocks
463
Programming Function Blocks
464
Transferring Data Blocks
470
Extending the Ipcflag Area
476
Program Structure
480
Fig. 10-6 Overview of the Blocks Required in each CPU
481
Application Example
487
Fig. 10-7 Data Exchange between 3 Cpus
487
PG Interfaces and Functions
491
11.1 Overview
494
11.2 PG Functions
495
Info
496
Fig. 11-1 PG Display of the Memory Configuration
496
Installation
497
Program Test
498
Fig. 11-2 Sequence of "Program Test
502
11.3 Serial Link PG - PLC Via 1St or 2Nd Serial Interface
506
Parallel Operation of Two Serial
507
Parallel Operation of Two Serial PG Interfaces
507
Fig. 11-3 Using the Second Interface as a
507
Examples of Configurations
508
Fig. 11-4 First Example of a Configuration
508
Fig. 11-5 Second Example of a Configuration
508
Installation
509
Operation
509
Sequence in Certain Operating Situations
511
Fig. 11-7 Typical Sequence of a Cyclic Function and Parallel Short-Running Function
512
Fig. 11-8 Sequence of Two Parallel Cyclic Functions
514
11.5 PG Functions Via the S5 Bus
516
Application
516
How the PG Functions Work Via the S5 Bus
518
Installation and Getting Started
520
Condition Codes Indicating Problems
524
Appendix
527
Appendix 4: Results Ids of some of the Special Function Obs in ACCU 1
527
Byte Ids in ACCU-1-LL
527
Appendix 1: Jumper Settings for System Interrupts
529
Appendix 2: Inserting and Removing the PG Submodule
530
Appendix 3: Technical Data of the CPU 948, CPU 946/947 and CPU 928B
532
Appendix 4: Results Ids of some of the Special Function Obs in ACCU
535
Word Ids in ACCU-1-L
537
Further Reading
540
Indexes
543
List of Abbreviations
544
List of Key Words
546
List of Tables and Figures
551
List of Figures
557
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