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VMIC VMIVME-7586-346 Product Manual

Pc/at compatible vmebus controller
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VMIC VMIVME-7586-346
VMEbus CPU with Dual-Port Memory PC/104 and
Cache
A l l t r a d e m a r k s , b r a n d n a m e s , a n d b r a n d s a p p e a r i n g h e r e i n a r e t h e p r o p e r t y o f t h e i r r e s p e c t i v e o w n e r s .
• C r i t i c a l a n d e x p e d i t e d s e r v i c e s
• I n s t o c k / R e a d y - t o - s h i p
Artisan Scientific Corporation dba Artisan Technology Group is not an affiliate, representative, or authorized distributor for any manufacturer listed herein.
In Stock
Used and in Excellent Condition
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https://www.artisantg.com/80018-1
• We b u y y o u r e x c e s s , u n d e r u t i l i z e d , a n d i d l e e q u i p me n t
• F u l l - s e r v i c e , i n d e p e n d e n t r e p a i r c e n t e r

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  • Page 1 VMIC VMIVME-7586-346 VMEbus CPU with Dual-Port Memory PC/104 and Cache In Stock Used and in Excellent Condition Open Web Page https://www.artisantg.com/80018-1 A l l t r a d e m a r k s , b r a n d n a m e s , a n d b r a n d s a p p e a r i n g h e r e i n a r e t h e p r o p e r t y o f t h e i r r e s p e c t i v e o w n e r s .
  • Page 2 VMIVME-7586 PC/AT COMPATIBLE VMEbus CONTROLLER PRODUCT MANUAL DOCUMENT NO. 500-017586-000 B Revised July 21, 1997 VME MICROSYSTEMS INTERNATIONAL CORPORATION 12090 SOUTH MEMORIAL PARKWAY HUNTSVILLE, AL 35803-3308 (205) 880-0444 (800) 322-3616 FAX NO.: (205) 882-0859...
  • Page 3 VMIC assumes no responsibility resulting from omissions or errors in this manual, or from the use of information contained herein. VMIC reserves the right to make any changes, without notice, to this or any of VMIC’s products to improve reliability, performance, function, or design.
  • Page 4 Because of a recently discovered design flaw in the VIC64 (Cypress Semiconductor) used to implement the VMEbus interface on the VMIVME-7586, VMIC warns users that a malfunction may occur. The following paragraphs below provide information from Cypress concerning the conditions that must be present to cause this malfunction.
  • Page 5 RECORD OF REVISIONS REVISION PAGES INVOLVED DATE CHANGE NUMBER LETTER 10/25/96 Release 96-0744 07/21/97 Cover and Page iii 97-0539 REV LTR PAGE NO. VME MICROSYSTEMS INT’L CORP. DOC. NO. 500-017586-000 12090 South Memorial Parkway Huntsville, AL 35803-3308 • (205) 880-0444...
  • Page 6 VMIC SAFETY SUMMARY THE FOLLOWING GENERAL SAFETY PRECAUTIONS MUST BE OBSERVED DURING ALL PHASES OF THE OPERATION, SERVICE, AND REPAIR OF THIS PRODUCT. FAILURE TO COMPLY WITH THESE PRECAUTIONS OR WITH SPECIFIC WARNINGS ELSEWHERE IN THIS MANUAL VIOLATES SAFETY STANDARDS OF DESIGN, MANUFACTURE, AND INTENDED USE OF THIS PRODUCT. VME...
  • Page 7 SAFETY SYMBOLS GENERAL DEFINITIONS OF SAFETY SYMBOLS USED IN THIS MANUAL Instruction manual symbol: the product is marked with this symbol when it is necessary for the user to refer to the instruction manual in order to protect against damage to the system. Indicates dangerous voltage (terminals fed from the interior by voltage exceeding 1000 volts are so marked).
  • Page 8 TABLE OF CONTENTS CHAPTER 1 - INTRODUCTION ..........SECTION 1 - INTRODUCTION TO THE VMIVME-7586 ....... 1-1 SECTION 2 - ABOUT THIS MANUAL ........... 1-2 SECTION 3 - PRODUCT FAMILY ............1-3 SECTION 4 - REFERENCES ..............1-5 SECTION 5 - PC/AT FEATURES ............1-6 SECTION 6 - VMEbus FEATURES ............
  • Page 9 TABLE OF CONTENTS 500-017586-000 GENERAL RULE REGARDING OPERATING SYSTEMS ....2-8 CONFIGURATION EXAMPLES ............2-9 Configuring MS-DOS for the VMIVME-7586 ....... 2-9 Configuring Windows for the VMIVME-7586 ....... 2-10 CHAPTER 3 - PC/AT FUNCTIONS ........... 3-1 SECTION 1 - CPU FUNCTIONAL OVERVIEW ........3-1 SECTION 2 - PHYSICAL MEMORY ............
  • Page 10 500-017586-000 TABLE OF CONTENTS SECTION 3 - VMEbus MASTER OPERATION ........4-7 REAL MODE ACCESS ..............4-8 PROTECTED MODE ACCESS ............4-10 128 MBYTE - PROTECTED MODE ACCESS ........4-13 SECTION 4 - VMEbus SLAVE OPERATION ........4-16 INTERPROCESSOR COMMUNICATIONS ........4-17 DUAL-PORTED DRAM ..............
  • Page 11 TABLE OF CONTENTS 500-017586-000 SECTION 11 - VME64 FUNCTIONS ............4-45 MASTER VME64 OPERATION ............4-45 SLAVE VME64 OPERATION ............4-45 SECTION 12 - BYTE ORDERING ............4-46 BYTE SWAPPING ................4-46 The Byte-Swapping Problem Defined .......... 4-47 Byte Swapping and the VMEbus ..........4-48 VMIVME-7586 Byte-Swapping Hardware ........
  • Page 12 500-017586-000 TABLE OF CONTENTS Error Group Interrupt Vector Base Register ......... 4-75 Interprocessor Communications Registers ........4-76 VMEbus Interrupt Request/Status Register ......... 4-76 VMEbus Interrupt Vector Base Registers ........4-76 Transfer Timeout Register ............4-77 Local Bus Timing Register ............4-80 Block Transfer Definition Register ..........
  • Page 13 TABLE OF CONTENTS 500-017586-000 SECTION 2 - ETHERNET CONNECTOR PINOUT ....... A-3 SECTION 3 - FLOPPY DRIVE CONNECTOR PINOUT ......A-4 SECTION 4 - IDE HARD DRIVE CONNECTOR PINOUT ..... A-5 SECTION 5 - KEYBOARD CONNECTOR PINOUT ......A-6 SECTION 6 - PC/104 CONNECTOR PINOUT ........A-7 SECTION 7 - PRINTER CONNECTOR PINOUT ........
  • Page 14 500-017586-000 TABLE OF CONTENTS SECTION 5 - REPROGRAMMING FLASH MEMORY ......C-4 SECTION 6 - TECHNICAL DETAILS ............ C-4 SECTION 7 - PROGRAMMING ............. C-6 APPENDIX D - BASIC INPUT / OUTPUT SYSTEM ....SECTION 1 - INTRODUCTION .............. D-1 SECTION 2 - STANDARD FEATURES ..........
  • Page 15 TABLE OF CONTENTS 500-017586-000 Noncacheable Region ..............D-15 MEMORY SHADOW SUB-MENU ............. D-16 System Shadow ................D-17 Video Shadow ................D-17 Shadow Memory Regions ............D-17 C800 - CFFF ................D-18 D000 - DFFF ................D-18 E000 - EFFF ................D-18 BOOT OPTIONS SUB-MENU ............
  • Page 16 LIST OF FIGURES Figure 1-1 VMIVME-7586 Board View ..........1-3 Figure 1-2 VMIVME-7586 Partial Block Diagram ........ 1-7 Figure 1-3 VMIVME-7586 VMEbus Functions ........1-9 Figure 2-1 I/O Port and Jumper Locations ......... 2-3 Figure 2-2 LED Position on the Front Panel ........2-5 Figure 2-3 PC/104 Mechanical Connection ........
  • Page 17 LIST OF FIGURES 500-017586-000 Figure 4-15 Byte Relationships Using the Big-Endian 68040 ..... 4-48 Figure 4-16 5x86-to-VMEbus Data Byte Lanes ........4-50 Figure A-1 VMIVME-7586 Connector Locations ......... A-2 Figure A-2 Ethernet Connector Pinout ..........A-3 Figure A-3 Floppy Drive Connector Pinout ........
  • Page 18 LIST OF TABLES Table 1-1 PC/AT I/O Features ............1-8 Table 2-1 VMIVME-7586 Jumper Functions and Settings ....2-4 Table 2-2 VMEbus Window Addresses ..........2-9 Table 3-1 VMIVME-7586 Memory Map ..........3-3 Table 3-2 VMIVME-7586 I/O Address Map ........3-5 Table 3-3 PC/AT Hardware Interrupts ..........
  • Page 19 The VMIVME-7586 programmer may quickly and easily control all the VMIVME-7586 VMEbus functions simply by linking to a library of VMEbus interrupt and control functions. This library is located in VMICÕs VMIVME-9420 IOWorks Access software for Windows NT users and VMIVME-7420 VMEaccess software for MS-DOS users.
  • Page 20 CHAPTER 1 - INTRODUCTION 500-017586-000 SECTION 2 - ABOUT THIS MANUAL Because this product bridges the traditionally divergent worlds of Intel-based PCs and Motorola-based VMEbus controllers, some confusion over ÒconventionalÓ notation and terminology may exist. We have made every effort to make this manual consistent by adhering to conventions typical for the Motorola/VMEbus world;...
  • Page 21 SECTION 3 - PRODUCT FAMILY Figure 1-1 shows a simpliÞed view of the VMIVME-7586 board. The VMIVME-7586 is one member of VMIC's line of PC/AT compatible VMEbus controllers, all of which combine a standard PC/AT architecture with the ability to control VMEbus slave boards.
  • Page 22 VMEbus interface. It also supports L1 write-back cache and in slave mode the board provides VMEbus remap to alternate local address capability. VMIC also has other support products for the PC/AT compatible VMEbus controller line. The VMIVME-7450 is a dual-slot module which holds one 3.5 inch ßoppy drive and one 3.5 inch hard drive.
  • Page 23 SECTION 4 - REFERENCES For the most up-to-date physical description and speciÞcations for the VMIVME-7586, please refer to VMIC speciÞcation number 800-017586-000. There are many books widely available on the subject of general PC/AT use and programming. Some reference sources which may be particularly helpful in using or programming the VMIVME-7586 are listed below.
  • Page 24 CHAPTER 1 - INTRODUCTION 500-017586-000 SECTION 5 - PC/AT FEATURES The VMIVME-7586 performs all the functions of a standard IBM PC/AT motherboard with the following features: ¥ Single-Slot 6U Size ¥ High-performance 5x86 processor Standard 16 Kbyte internal cache ¥ The 5x86 processor supports level 1 (L1) write-back cache for near 90 MHz Pentium processor performance ¥...
  • Page 25 500-017586-000 PC/AT FEATURES SYSTEM BIOS DRAM 128 KB 4 MB, 8 MB 16 MB, 32 MB KEYBOARD KEYBOARD 5x86 CONTROLLER with WRITE-BACK MICRO L2 CACHE 2048 REAL-TIME CLOCK WRITE-BACK L2 CACHE 256 KB/1MB SVGA SVGA DISPLAY CONTROLLER VIDEO DRAM 82091AA SUPER PC / 104 COM1 /...
  • Page 26 CHAPTER 1 - INTRODUCTION 500-017586-000 Table 1-1 PC/AT I/O Features I/O FEATURE MS-DOS IDENTIFIER PHYSICAL ACCESS Two High-Speed Serial Ports Front Panel COM1, COM2 (16550-compatible RS-232C) RJ45 (male) X 2 One Enhanced Bidirectional Parallel Port Front Panel LPT1 (or LPT2) (IEEE-1284 ECP/EPP compliant) DB25S (female) AT-Style Keyboard Controller...
  • Page 27 500-017586-000 VMEbus FEATURES ¥ VMEbus BERR* 10 µ s bus error timer (jumper enabled) ¥ Complete VMEbus master access through Real-mode memory window or Protected-mode linear addressing ¥ Slave access from the VMEbus to local RAM and interprocessor communications registers ¥...
  • Page 28 INSTALLATION AND CHAPTER SETUP IN THIS CHAPTER: SECTION 1 - INTRODUCTION SECTION 2 - UNPACKING PROCEDURES SECTION 3 - HARDWARE SETUP SECTION 4 - LED STATUS DEFINITION SECTION 5 - INSTALLATION SECTION 6 - FRONT PANEL CONNECTORS SECTION 7 - PC/104 EXPANSION SITE SECTION 8 - BIOS SETUP SECTION 9 - CONFIGURING OPERATING SYSTEMS SECTION 1 - INTRODUCTION...
  • Page 29 All claims arising from shipping damage should be Þled with the carrier and a complete report sent to VMIC together with a request for advice concerning the disposition of the damaged item(s).
  • Page 30 500-017586-000 HARDWARE SETUP E5 - COM1 Pin 8 Function E25 - Reset Disable 1 - 2* RS-232 DCD Signal Installed* System Reset - Driven To VMEbus 2 - 3 RS-232 RI Signal Not Installed Front Panel Reset Will Not Be Driven Onto VMEbus E12 - Delta Tau Option** Installed Enabled...
  • Page 31 Enabled - System Reset Installed = Enabled (Default) Disable - Front Panel Reset Removed = Disabled NOTE: ANY OTHER JUMPER LOCATIONS ARE RESERVED FOR VMIC USE ONLY AND SHOULD NOT BE ALTERED FROM THE FACTORY DEFAULT SETTINGS. VMIVME-7586 PRODUCT MANUAL...
  • Page 32 500-017586-000 LED STATUS DEFINITION SECTION 4 - LED STATUS DEFINITION Position 2 Position 3 Position 1 STATUS RESET Figure 2-2 LED Position on the Front Panel Position 1 - Hard Drive Indicator - Indicates when hard drive activity is occurring. Position 2 - General Purpose/Status - ConÞgured to be used at programmerÕs discretion.
  • Page 33 6. Apply power to the system. Several messages are displayed on the screen, including names, versions, and copyright dates for the various BIOS modules on the VMIVME-7586. Among the screen messages should be a VMIC product identifier such as: VME Microsystems International Corp. VMIVME-7586 7.
  • Page 34 500-017586-000 PC/104 EXPANSION SITE a keyboard with a standard PC/AT connector to the VMIVME-7586. See Appendix A for connector pinouts and orientation. SECTION 7 - PC/104 EXPANSION SITE Expansion boards that are PC/104 compatible install directly to the VMIVME-7586Õs PC/104 Expansion Site (see Figure 2-1 on page 2-3). Figure 2-3 illustrates mechanical...
  • Page 35 CHAPTER 2 - INSTALLATION AND SETUP 500-017586-000 SECTION 8 - BIOS SETUP The VMIVME-7586 has an on-board BIOS Setup program that controls many conÞguration options. These options are saved in a special nonvolatile, battery-backed memory chip and are collectively referred to as the boardÕs ÒCMOS conÞguration.Ó...
  • Page 36 500-017586-000 CONFIGURING OPERATING SYSTEMS Windows. This prevents strange activity on the VMEbus, since any access within a VMEbus window is translated into a VMEbus access once VMEbus access is enabled. The complete VMIVME-7586 memory map is presented in Chapter 3, but for reference the address ranges to be excluded for the VMEbus Windows are listed in Table 2-2.
  • Page 37 CHAPTER 2 - INSTALLATION AND SETUP 500-017586-000 The most common memory manager used with MS-DOS is the one included with DOS itself, EMM386.EXE. If EMM386.EXE is loaded in your CONFIG.SYS conÞguration Þle, edit the line that loads EMM386.EXE and add the parameter to the line to exclude the Real Mode X=E000-EFFF VMEbus Window.
  • Page 38 CHAPTER PC/AT FUNCTIONS IN THIS CHAPTER: SECTION 1 - CPU FUNCTIONAL OVERVIEW SECTION 2 - PHYSICAL MEMORY SECTION 3 - MEMORY AND I/O PORT MAPS SECTION 4 - PC/AT INTERRUPTS SECTION 5 - ENHANCED I/O PERIPHERAL PORTS 3-12 SECTION 6 - VIDEO GRAPHICS ADAPTER 3-14 SECTION 7 - PC/104 EXPANSION SITE 3-15...
  • Page 39 CHAPTER 3 - PC/AT FUNCTIONS 500-017586-000 SECTION 2 - PHYSICAL MEMORY The VMIVME-7586 has one 72-pin SIMM socket, which supports a 1 M x 36, 2 M x 36, 4 M x 36, or 8 M x 36 factory-installed SIMM module for a total of 4, 8, 16, or 32 Mbyte of DRAM.
  • Page 40 500-017586-000 MEMORY AND I/O PORT MAPS SECTION 3 - MEMORY AND I/O PORT MAPS MEMORY MAP The memory map for the VMIVME-7586 is shown in Table 3-1. All systems share this same memory map, although a VMIVME-7586 with less than the full 32 Mbyte of DRAM does not Þll the entire space reserved for On-Board Extended Memory.
  • Page 41 CHAPTER 3 - PC/AT FUNCTIONS 500-017586-000 I/O PORT MAP The 5x86 CPU has special input/output instructions that access I/O peripherals residing in I/O addressing space (which is separate and distinct from memory addressing space). When the CPU decodes and executes an I/O instruction, it produces a 16-bit I/O address on lines A00-A15 and identiÞes the I/O cycle with the M/IO control line.
  • Page 42 500-017586-000 MEMORY AND I/O PORT MAPS Table 3-2 VMIVME-7586 I/O Address Map SIZE IN ASSOCIATED ADDRESS HARDWARE DEVICE PC/AT FUNCTION † BYTES JUMPERS RANGE DMA Controller 1 $000 - $00F ACC Micro 2040 Chip (Intel 8237A Compatible) $010 - $01F Reserved Master Interrupt Controller $020 - $021...
  • Page 43 HARDWARE DEVICE PC/AT FUNCTION † BYTES JUMPERS RANGE VMEbus Interface Registers $140 - $14F Custom VMIC Hardware E24 & E11 (see Chapter 4 for details) $150 - $153 Custom VMIC Hardware Slave Size and Remap Registers $154 - $16F Reserved...
  • Page 44 $400 - $4FF VIC Chip § VMEbus Interface controller (default) § $500 - $501 Reserved $502 - $508 Custom VMIC Hardware § Interrupt ID Registers (default) § $509 - $677 Reserved $678 - $67A Super I/O Chip LPT2 ECP Registers E6 &...
  • Page 45 CHAPTER 3 - PC/AT FUNCTIONS 500-017586-000 SECTION 4 - PC/AT INTERRUPTS In addition to an I/O port address, an I/O device often has a separate hardware interrupt line assignment. Assigned to each interrupt line is a corresponding interrupt vector in the 256-vector interrupt table at $00000 to $003FF in memory.
  • Page 46 500-017586-000 PC/AT INTERRUPTS Table 3-4 PC/AT Interrupt Vector Table INTERRUPT # REAL MODE PROTECTED MODE LINE Divide Error Same as Real Mode Debug Single Step Same as Real Mode Memory Parity Error, Same as Real Mode VMEbus Interrupts (Must be enabled in BIOS Setup) Debug Breakpoint Same as Real Mode ALU Overflow...
  • Page 47 CHAPTER 3 - PC/AT FUNCTIONS 500-017586-000 Table 3-4 PC/AT Interrupt Vector Table (Continued) INTERRUPT # REAL MODE PROTECTED MODE LINE Video Parameter Table Pntr Same as Real Mode Floppy Parm Table Pntr Same as Real Mode Video Graphics Table Pntr Same as Real Mode DOS Terminate Program Same as Real Mode...
  • Page 48 500-017586-000 PC/AT INTERRUPTS The maskable interrupts are prioritized in hardware by the equivalent of two cascaded Intel 8259A Priority Interrupt Controller (PIC) chips. At boot-up time, the BIOS writes an 8-bit vector to each PIC that maps each Interrupt Request line (IRQx) to its corresponding interrupt vector in memory.
  • Page 49 CHAPTER 3 - PC/AT FUNCTIONS 500-017586-000 8259 MASTER-PORTS $020-$021 IRQ1* IRQ2* VIC64 IRQ1 IRQ3 IRQ4 SYS IRQ6 IRQ7 IRQ8 IRQ3* IRQ4* VMEbus IRQ5* INTERF ACE 8259 SLAVE-PORTS $0A0-$0A1 CONTROLLER IRQ6* IRQ7* IRQ10 IRQ11 IRQ12 IRQ14 SYS SYS SYS_FAIL* ACFAIL* BERR* IPL0*-IPL2* VLIC VIC TO...
  • Page 50 500-017586-000 ENHANCED I/O PERIPHERAL PORTS SERIAL PORTS Each of the two serial ports uses a 16550 compatible UART, including 16 byte transmit and receive FIFO buffers. The FIFOs reduce processor overhead usually needed when the ports are active, allowing reliable serial transfer speeds up to 38.4 kilobaud.
  • Page 51 CHAPTER 3 - PC/AT FUNCTIONS 500-017586-000 The ECP protocol not only implements a hardware handshake, but adds a 16 byte FIFO with DMA capability to reduce processor overhead. The VMIVME-7586Õs AIP chip supports all parallel port modes in Table 3-5 on page 3-13, except the EPP mode is not supported if the alternate LPT1 I/O address of $3BC-$3BF is used (see Chapter 2 for hardware setup details).
  • Page 52 PCMCIA adapters, Ethernet and SCSI interfaces, and other I/O functions. VMICÕs VMIVME-7432 PC/104 to ISA Adapter is designed speciÞcally to mate with the VMIVME-7586, allowing it to use a standard half-length ISA bus board in the same chassis. This expansion allows low-cost or specialty ISA bus boards to be used in the same chassis with VMEbus equipment.
  • Page 53 CHAPTER VMEbus FUNCTIONS IN THIS CHAPTER: SECTION 1 - INTRODUCTION SECTION 2 - VMEbus INTERFACE SECTION 3 - VMEbus MASTER OPERATION SECTION 4 - VMEbus SLAVE OPERATION 4-16 SECTION 5 - SYSTEM CONTROLLER FUNCTIONS 4-31 SECTION 6 - VMEbus INTERRUPT HANDLING 4-32 SECTION 7 - VMEbus INTERRUPTER 4-39...
  • Page 54 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 SECTION 2 - VMEbus INTERFACE This section discusses how the VMIVME-7586 interfaces with the VMEbus. At powerup or after a system reset (but not after a soft reset, or reset), the VMIVME-7586 is ÒisolatedÓ from the VMEbus. The <Ctrl+Alt+Del>...
  • Page 55 500-017586-000 VMEbus INTERFACE Interprocessor 5x86 CPU Communications VMIVME-7586 5x86 Local Bus VMIVME-7586 Slot 1 System Controller DRAM MASTER Intrpt Ack System Daisy-Chain Reset Interrupt Driver Driver Timer Handler Slave (10 µs) Interrupter Stat/ID IQx 16 MHz Clock Arbiter Driver Requester Requester D at a Tr an s fe r Bus D TB Ar bi t ra ti on...
  • Page 56 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 VMEbus INTERFACE HARDWARE The VMIVME-7586 VMEbus hardware interface consists of a Cypress VIC64 VMEbus Interface Controller (hereafter referred to as the VIC or the VIC64), its companion VIC-to-Local bus Interface Circuitry (referred to as the VLIC), and three Cypress CY7C964.
  • Page 57 500-017586-000 VMEbus INTERFACE The CPU interface of the VIC was designed to be part of a Motorola 68030 system. An interface is required to connect the 5x86 bus to the 68030-like CPU interface of the VIC. This connection is accomplished by the VLIC using the functional modules illustrated in Figure 4-3.
  • Page 58 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 The VLIC contains system registers that allow the VMIVME-7586 VMEbus interface to be programmed. These are discussed in detail in Section 13. The VLIC also contains hardware to translate the 68030-like interrupt structure of the VIC to the PC/AT interrupt structure. Slave remapping functionality is also conÞgured in the VLIC circuit block.
  • Page 59 500-017586-000 VMEbus MASTER OPERATION In addition to setting the VIC Enable bit, address bit A10 must be set when accessing the VIC Registers or Interrupt Acknowledge Registers. This prevents conßicts that may occur between the VIC register addresses and the AT I/O resources located between I/O address $000 and $3FF. To access the VIC registers, program the VIC Base Register, then perform a byte I/O access to the desired VIC register according to the VIC Register Map on page 4-53.
  • Page 60 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 REAL MODE ACCESS When in Real Mode, accessing the 64 Kbyte of memory located at physical address $E0000 causes an access to VMEbus (provided the VME Enable bit is set in the General Purpose Command Register). The desired address modiÞer code is contained in the VIC Address ModiÞer Source Register.
  • Page 61 500-017586-000 VMEbus MASTER OPERATION VIC64 REGISTER AMSR REGISTER AM5-AM0 SYSTEM REGISTER EXT_STD_ADDR REGISTER A31-A16 A15-A1 A15-A1 5x86 D31-00 D31-D0 5x86 = REAL MODE 5x86 A19-A16 = 1110 = $E GP_COMMAND VME_EN = 1 Figure 4-4 Real Mode VMEbus Access VMIVME-7586 PRODUCT MANUAL...
  • Page 62 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 After powerup, accessing VMEbus in Real Mode requires at least the following steps: 1. Initialize the VIC Base Register. Program the VIC base address and enable access to the VIC by setting the VIC Enable bit. 2.
  • Page 63 500-017586-000 VMEbus MASTER OPERATION Table 4-1 Protected Mode VMEbus Address Modifiers. Note: I/O Port $143 must be set to $00 . ADDRESS MODIFIER (ASIZ1) (ASIZ0) (FC2) (FC1) AND MODE A24 Supervisory-program A24 Supervisory-data A24 Nonprivileged-program A24 Nonprivileged-data A16 Supervisory-program A16 Supervisory-data A16 Nonprivileged-program A16 Nonprivileged-data A32 Supervisory-program...
  • Page 64 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 VIC64 AMSR 5x86 VIC64 AMSR A29-A26 VIC64 AMSR VIC64 AMSR A32 - USER DATA A32 - USER CODE AM5-AM0 A32 - SUPER DATA 1 of 16 A32 - SUPER CODE A16 - USER DATA A16 - USER CODE A16 - SUPER DATA A16 - SUPER CODE...
  • Page 65 500-017586-000 VMEbus MASTER OPERATION After powerup, accessing VMEbus in Protected Mode requires at least the following steps: 1. Initialize the VIC Base Register. Program the VIC base address and enable access to the VIC by setting the VIC Enable bit. 2.
  • Page 66 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Table 4-2 128 Mbyte Master Window Definitions ADDRESS MODIFIER ADDRESS SIZE IN Mbytes (ASIZ1) (ASIZ0) (FC2) (FC1) AND MODE RANGE $4000 0000 - user-defined 47FF FFFF A32 User Data / User $5000 0000 - Block 53FF FFFF A32 User Pgm / User...
  • Page 67 500-017586-000 VMEbus MASTER OPERATION VIC64 AMSR 5x86 VIC64 AMSR A29-A26 VIC64 AMSR VIC64 AMSR A32 - USER DATA A32 - USER CODE AM5-AM0 A32 - SUPER DATA 1 of 16 A32 - SUPER CODE A16 - USER DATA A16 - USER CODE A16 - SUPER DATA A16 - SUPER CODE A24 - USER DATA...
  • Page 68 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 After powerup, accessing VMEbus in Protected Mode for 128 Mbyte access requires at least the following steps: 1. Initialize the VIC Base Register. Program the VIC base address and enable access to the VIC by setting the VIC Enable bit. 2.
  • Page 69 500-017586-000 VMEbus SLAVE OPERATION INTERPROCESSOR COMMUNICATIONS The VIC contains interprocessor communication facilities which are accessible in the VMEbus Short I/O (A16) address space (see Table 4-8 on page 4-53 for a complete slave register map). The facilities are: ¥ Four Global Mailbox Switches (ICGS0-3) ¥...
  • Page 70 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 5x86 LOCAL DATA BUS A31-A24 A32-A24 SL_MSW_ADDR CY7C964 A32-A24 SL_MSW_MASK MATCH NMSB A23-A16 CY7C964 MATCH A15-A8 SL_LSW_ADDR CY7C964 SL_LSW_MASK MATCH IFCSEL* VIC64 SLSEL1* A7-A1 SLSEL0* MBOX_EN A32_EN A24_EN GP_COMMAND REGISTER Figure 4-7 VMEbus Slave Interface Each CY7C964 contains a Slave Address Compare register and a Slave Address Mask register.
  • Page 71 500-017586-000 VMEbus SLAVE OPERATION As Figure 4-7 on page 4-18 shows, the LSB CY7C964 has a MATCH* output which is connected to the VIC ICFSEL* input. The MATCH* signal is activated when the VMEbus address matches the address deÞned by the LSB CY7C964 address compare and mask registers.
  • Page 72 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 SL_LSW_ADDR REGISTER MATCH SL_LSW_MASK REGISTER VMEbus A16 VMEbus A8 Figure 4-8 Slave Compare Operation The General Purpose Command system register contains a Mailbox Enable bit that is used to ensure that slave accesses to the VIC are blocked until the Slave A16 Address Compare and Slave A16 Address Mask registers are properly initialized.
  • Page 73 500-017586-000 VMEbus SLAVE OPERATION Example: Program VIC ICRs to be accessible by VMEbus addresses between $4000 and $7F00. 1. Write 0x4000 data to Slave A16 Address Compare register. 2. Write 0x3F00 data to Slave A16 Address Mask register. 3. Set Mailbox Enable bit in the General Purpose Command register. After powerup, the following procedure should be followed to allow a slave access to the VIC interprocessor communication facilities: 1.
  • Page 74 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 utility; however, extreme caution should be used when accessing this region to prevent overwriting the operating system. The VMIVME-7586 slave interface allows the dual-port DRAM slave address to be programmed in software. Also, incoming accesses may be remapped throughout the 32 Mbyte space.
  • Page 75 500-017586-000 VMEbus SLAVE OPERATION Register bits of the Slave A32/A24 Address Compare and Slave A32/A24 Address Mask Registers correspond to VMEbus address bits A31-A16. Note that D15-D8 of the Slave A32/A24 Address Compare and Slave A32/A24 Address Mask Registers correspond to registers contained in the MSB CY7C964.
  • Page 76 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 The dual-port DRAM can be conÞgured to be addressable using A32 accesses, A24 accesses, or both (by setting both the Slave A24 and Slave A32 Enable bits in the General Purpose Command Register). This may be useful for systems requiring the dual-port DRAM to be shared between A32 and A24 masters.
  • Page 77 500-017586-000 VMEbus SLAVE OPERATION Table 4-3 Slave Access Memory Map Local Address Resource $0200 0000 - $FFFF FFFF NOT ACCESSIBLE * Extended memory DRAM $0010 0000 - $01FF FFFF (31 Mbyte maximum)** $F0000 - $FFFFF System BIOS NOT ACCESSIBLE $E0000 - $EFFFF (will produce BERR*)*** Reserved for OS memory $D0000 - $DFFFF...
  • Page 78 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 programmer the capability of working around the dynamics of PC based compilers where memory usage may be unpredictable. The code developed on a secondary VMEbus board could, for instance, use a 64 Kbyte range starting at 1 Mbyte in the VMEbus address space for shared array storage in the VMIVME-7586.
  • Page 79 500-017586-000 VMEbus SLAVE OPERATION lower part of the Þgure depicts the VME address bus being gated to the 5x86 local address bus in the case that the corresponding window size register bit is set to Ô1Õ. If the corresponding window size register bit is set to Ô0Õ...
  • Page 80 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 NOTE: 64 K DDRESSES MAY ONLY BE REMAPPED ON BYTE BOUNDARIES DUE TO THE HARDWARE 4-10. IMPLEMENTATION AS DEPICTED IN IGURE Some of the implications of the system design include: Þrst, to disable size/remap function store $1FF into the window size register. This will gate the VME address bus directly to the 5x86 local bus.
  • Page 81 500-017586-000 VMEbus SLAVE OPERATION When conÞgured for A24 accesses, the VMIVME-7586 consumes at least 64 Kbyte of VMEbus A24 space (if the Slave A32/A24 Address Mask system register is cleared). Setting bit 0 of the Slave A32/A24 Address Mask register increases the memory allocation to 128 Kbyte. Setting the Slave A32/A24 Address Mask Register to all ones allocates the entire 16 Mbyte of VMEbus A24 space to the VMIVME-7586.
  • Page 82 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 A31 - A25 A31 - A25 N. C. CY7C964 A31 - A24 Intermediate A24 - A16 A24 - A16 CY7C964 A23 - A16 Remap Address A24 - A16 Remap Register Size Register A15 - A8 CY7C964 A15 - A8 A7 - A0...
  • Page 83 500-017586-000 SYSTEM CONTROLLER FUNCTIONS SECTION 5 - SYSTEM CONTROLLER FUNCTIONS For VMEbus slot-1 applications, the VMIVME-7586 may be jumpered to perform system controller functions including: ¥ 16 MHz System Clock ¥ SYSRESET* Driver ¥ IACK Daisy-Chain Driver ¥ Programmable Arbiter (PRI, SGL, and RRS modes supported) ¥...
  • Page 84 Interrupt Priorities Priority Source VMIVME-7586 Use LIRQ7 NOT USED Error Group ACFAIL*, Write post fail, Arbitration timeout, SYSFAIL* LIRQ6 VMIVME-7586 initiated BERR LIRQ5 Reserved by VMIC LIRQ4 Software Interrupt LIRQ3 NOT USED LIRQ2 Periodic Timer Interrupt 4-32 VMIVME-7586 PRODUCT MANUAL...
  • Page 85 500-017586-000 VMEbus INTERRUPT HANDLING Table 4-4 Interrupt Priorities (Continued) Priority Source VMIVME-7586 Use LIRQ1 NOT USED ICMS Group ICMS Group ICGS Group ICGS Group IRQ7 VMEbus IRQ7* IRQ6 VMEbus IRQ6* IRQ5 VMEbus IRQ5* IRQ4 VMEbus IRQ4* IRQ3 VMEbus IRQ3* IRQ2 VMEbus IRQ2* IRQ1 VMEbus IRQ1*...
  • Page 86 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 these PC/AT interrupts by using interrupt levels. The interrupt levels correspond to the PC/AT interrupt channels according to Table 4-5. Table 4-5 Interrupt Level Assignments Level PC/AT Interrupt IRQ11 IRQ12 VIC interrupts are acknowledged by reading the ID register associated with the PC/AT interrupt source.
  • Page 87 500-017586-000 VMEbus INTERRUPT HANDLING W A R N I N G THE NMI INTERRUPT ID, IRQ11 INTERRUPT ID, AND IRQ12 INTERRUPT ID REGISTERS SHOULD ONLY BE READ WHEN THE CORRESPONDING VIC INTERRUPT LEVEL IS PENDING. THIS IS GUARANTEED BY: 1. Programming the VIC to produce interrupts using only levels 4, 2, or 1. 2.
  • Page 88 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 SOFTWARE INTERRUPTS The VMIVME-7586 5x86 CPU can initiate a software-controlled interrupt on either the IRQ11, IRQ12, or NMI interrupts. This is accomplished by using the local interrupt LIRQ4 channel of the VIC. The VIC LIRQ4 input is connected to GND. A software-generated interrupt can be produced by programming the VIC LICR4 register.
  • Page 89 500-017586-000 VMEbus INTERRUPT HANDLING The timer is programmed using the VIC SS0CR0 register. The timer can be programmed for 50, 100, or 1000 Hz operation. The timer can be programmed to produce an interrupt using the LIRQ2 channel of the VIC. INTERRUPT PROCESSING The VIC produces interrupts that are level sensitive as required by the Motorola 68000 interrupt architecture.
  • Page 90 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Start ISR Read IRQ11_ID Register INIT IRQ11 Use vector to branch to Install specif i c ISR vector 11 Set up VIC64 interrupt sources for level 2 interrupt Initialize source vectors in VIC64 Write EOI to 8259 pic Unmask IR11 in...
  • Page 91 500-017586-000 VMEbus INTERRUPTER Start ISR Read part INIT NMI Install NMI Bit 6 PARITY ERR OR vector Set up VIC64 Read interrupt sources NMI_ID for level 4 Register interrupt Use vector to branch to specif i c ISR Initialize source vectors in VIC64 ISR Ready...
  • Page 92 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 accomplished by programming the VIC VIICR and the EGIVBR. The VIICR is used to program the desired interrupt level. The EGIVBR is used to program the interrupt vector that will be supplied to the 5x86 when the appropriate interrupt acknowledge register is read.
  • Page 93 500-017586-000 READ-MODIFY-WRITE CYCLES Use of Master VMEbus RMW cycles require that the VIC be programmed to support the RMW operation. This is programmed by using the VIC ICR. Bit 6 of this register is set if VMEbus RMW cycles are desired. A Master VMEbus RMW cycle is accomplished by instructing the 5x86 to access the VMEbus using a ÒLOCKEDÓ...
  • Page 94 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 To perform a RMW master access while in real mode, the C function is called as follows: tas_bit7_in_byte( 0xE000, vme_offset ); Where the VMEbus A15-A0 offset address is assigned to the variable vme_offset prior to the call, and VMEbus A31-A16 and VMEbus AM5-AM0 were previously set by initializing the Extended/Standard Address Register and the VIC Address ModiÞer Source Register.
  • Page 95 500-017586-000 BLOCK TRANSFERS slowing down VMEbus transfers. Accelerated local DMA mode maximizes the VMEbus transfer speed, but requires that the VMEbus BLT burst be limited to less than 15.6 µs. For master BLT accesses, limiting the BLT burst can be ensured by programming the VIC Release Control Register (RCR).
  • Page 96 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 The following sequence may be used to initiate master BLTs: Program SS0CR0, SS0CR1, and LBTR for single cycle or accelerated local DMA BLT. Program Block Transfer DeÞnition Register (BTDR) to 0x0F. Program Address ModiÞer Source Register to type address modiÞer corresponding to type of block transfer (standard supervisory, standard nonprivileged,...
  • Page 97 500-017586-000 VME64 FUNCTIONS SLAVE BLT OPERATION As described in Section 4, the slave select 0 VIC input is used for A32 slave accesses and slave select 1 is used for A24 slave accesses. Prior to the slave BLT the VIC slave select registers must be programmed to allow for A32 or A24 BLT slave accesses.
  • Page 98 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 SECTION 12 - BYTE ORDERING BYTE SWAPPING For a given addressing mode, the VMEbus SpeciÞcation deÞnes various types of data transfer cycles to access 1, 2, 3, or 4 byte locations at once. A set of four adjacent byte locations differing only in address bits (A00, A01) is deÞned as a four-byte group, or a Òbyte (0-3)Ó...
  • Page 99 500-017586-000 BYTE ORDERING Motorola compatible 680x0 VMEbus modules and the VMIVME-7586 requires special attention to avoid byte-ordering conßicts. The Byte-Swapping Problem Defined The byte-ordering issue exists due to the different traditions at the major microprocessor manufacturers, Motorola and Intel. Much VMEbus equipment is designed around MotorolaÕs 680x0 processors and compatibles, which store multiple-byte values in memory with the most signiÞcant byte at the lowest byte address.
  • Page 100 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 transfers. Conversely, the processor considers data retrieved from the lowest byte address to be the least signiÞcant byte after a multiple-byte read. Data retrieved from the highest byte address is considered to be the most signiÞcant byte.
  • Page 101 500-017586-000 BYTE ORDERING D31-D24 during a longword transfer while byte(3) must be transferred on lines D7-D0. This byte and address alignment is exactly the same as that for a big-endian processor such as the Motorola 68040 in Figure 4-15 on page 4-48.
  • Page 102 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 D31-D24 D31-D24 Local Data Bus D23-D16 D23-D16 D15-D08 D15-D08 D07-D00 D07-D00 D31-D24 5x86 D31-D24 D07-D00 D23-D16 D23-D16 D15-D08 D15-D08 D15-D08 D07-D00 D23-D16 D07-D00 D31-D24 D07-D00 D15-D08 D15-D08 D07-D00 3-Way Hardware Byte Swap Gateways Figure 4-16 5x86-to-VMEbus Data Byte Lanes The byte-swapping hardware is affected by two factors: the Big-Endian bit in the General Purpose Command Register, and the size of the transfer...
  • Page 103 500-017586-000 BYTE ORDERING Generally speaking, a set Big-Endian bit causes the 5x86 CPU to access the VMEbus much the same way a big-endian processor would. Two other facts should also be noted from Table 4-7: Þrst, no swapping is ever performed on single-byte transfers, regardless of the state of the Big Endian bit, and second, some form of swapping is always used for multiple-byte transfers.
  • Page 104 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 SECTION 13 - VMIVME-7586 REGISTERS REGISTER MAPS The VMIVME-7586 has three groups of custom registers: ¥ System Registers (12) ¥ Interrupt Acknowledge Registers (3) ¥ VIC Registers (58) All registers are in I/O addressing space, but only the System Registers have a Þxed location: I/O $140 through I/O $152.
  • Page 105 Table 4-8 System Register Map REGISTER NAME PAGE MNEMONIC ACCESS D15 D14 D13 D12 D11 D10 D9 Master Slave Slave General-Purpose Status Mailbox Slave A24 4-58 GP_COMMAND Byte Write $140 Big- Big- Word Command Enable Enable Enable Endian Endian Enable Enable 4-61 Product ID...
  • Page 106 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Table 4-9 VIC Register Map REGISTER NAME PAGE MNEMONIC VMEbus VMEbus Interrupter 4-65 VIICR $403 Interrupt IPL Value Interrupt Control Mask VMEbus Interrupt IRQ1 4-66 VICR1 $407 IPL Value Mask Control 1 VMEbus Interrupt IRQ2 4-66 VICR2...
  • Page 107 500-017586-000 VMIVME-7586 REGISTERS Table 4-9 VIC Register Map (Continued) REGISTER NAME PAGE MNEMONIC Error Group Interrupt 4-75 EGIVBR $45B Status/ID Value G roup Interrupt Number Vector Base Interprocessor 4-105 ICSR $45F ICGS Switch e s ICMS Switch e s Communications Switch Interprocessor 4-105 ICR0...
  • Page 108 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Table 4-9 VIC Register Map (Continued) REGISTER NAME PAGE MNEMONIC Meta- Deadlock Turbo SCON Interface ConÞguration 4-82 $4AF Control Control Control stability Signaling Enable Status Interval V M E b u s Arbiter/Requester Arbitration DRAM 4-84 ARCR...
  • Page 109 500-017586-000 VMIVME-7586 REGISTERS Table 4-10 Slave Access Register Map SHORT REGISTER NAME PAGE MNEMONIC ADDR Interprocessor 4-105 ICR0 User Data Communications 0 Interprocessor 4-105 ICR1 User Data Communications 1 Interprocessor 4-105 ICR2 User Data Communications 2 Interprocessor 4-105 ICR3 User Data Communications 3 Interprocessor 4-105...
  • Page 110 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Table 4-10 Slave Access Register Map (Continued) SHORT REGISTER NAME PAGE MNEMONIC ADDR Shaded Interprocessor Communications Registers are unique because they are also available to the local processor. SYSTEM REGISTER DETAILS General Purpose Command Register The General Purpose Command Register (GP_COMMAND) is a write-only byte register at I/O address $140.
  • Page 111 500-017586-000 VMIVME-7586 REGISTERS D6/D5 Big-Endian Bit Function Use Little-Endian multiple-byte transfers (default) Use Big-Endian multiple-byte transfers Bit 6 controls byte swapping for the VMIVME-7586 as a VMEbus master, while bit 5 controls byte swapping when the VMIVME-7586 is being accessed as a VMEbus slave device. Any byte swapping is transparent both to the local CPU and to VMEbus devices, but byte swapping is not supported during unaligned transfers.
  • Page 112 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 General Purpose Command Register: Mailbox Enable bit (D3) Bit 3 controls slave access to the VMIVME-7586Õs mailbox registers within the VIC. The default clear state disables slave accesses to the mailbox registers. Mailbox Enable Bit Function The mailbox registers will not respond to slave accesses (default) The mailbox registers will respond to slave accesses The Mailbox Enable bit allows the programmer to conÞgure the VIC and...
  • Page 113 The Product ID Register (BRD_ID) is a read-only byte register at I/O address $140. This register always contains the value $01, which uniquely identiÞes the VMIVME-7586 from other VMIC VMEbus products. Product ID Register BRD_ID (Read-Only byte at I/O $140)
  • Page 114 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Interrupt Acknowledge Registers starting at I/O $502. There is little reason to ever change the default setting. VIC Base Register: LPT Mode bit (D1) This utility bit controls whether or not the VMIVME-7586Õs parallel port is bidirectional or output only.
  • Page 115 500-017586-000 VMIVME-7586 REGISTERS When accessing the VMEbus through the Real Mode VMEbus Window, this register supplies any and all of the upper address bits, while the address modiÞer bits are supplied by the VIC Address ModiÞer Source Register. When accessing the VMEbus through the Protected Mode VMEbus Window, only the most signiÞcant byte of this register (bits D8-D15) is used, since all other address bits can be obtained from the 5x86 address lines.
  • Page 116 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Size Register The Size Register controls address bits A16 through A24 through the I/O word port $150. The register is active low. Setting all bits to 1 ($1FF) in the port $150 will disable the associated remap functionality. Setting the I/O word port $150 to $001 would, for example, map a 128 Kbyte region from the VMEbus to an address region speciÞed by the Remap Register.
  • Page 117 500-017586-000 VMIVME-7586 REGISTERS Note that the addresses listed for these registers are default addresses. Their actual location depends upon the value in the VIC Base Register. See the description of the VIC Base Register on page 4-61 for details. VIC REGISTER DETAILS All VIC registers are physically read/write byte registers, although the functions of some of the registers make them meaningful only as read-only or write-only.
  • Page 118 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 VMEbus Interrupter Interrupt Control Register: VMEbus Interrupt Mask bit (D7) When this bit is clear, the VIC signals a local interrupt at the acknowledgment of a previously issued VMEbus interrupt. When set, the VIC will not issue a local interrupt. VMEbus Interrupt Mask Bit Function The VIC issues a local interrupt upon acknowledgment of a VMEbus interrupt...
  • Page 119 500-017586-000 VMIVME-7586 REGISTERS VMEbus Interrupt Control Registers: IRQ Mask bit (D7) When this bit is clear, the VIC acts as a VMEbus interrupt handler by signaling a local interrupt at the speciÞed IPL level. When set, the VIC does not handle the VMEbus interrupt and no local interrupt is issued. IRQ Mask Bit Function The VIC signals the corresponding VMEbus interrupt with a local interrupt at the specified IPL level...
  • Page 120 Do not enable the interrupt until the interrupt handling routines are in place. Also, note that LIRC5 is reserved by VMIC and should never be altered from the default setting. Local Interrupt Control Registers LICR1-7 (VIC offset I/O $427-$43F)
  • Page 121 500-017586-000 VMIVME-7586 REGISTERS Local Interrupt Control Registers: High Polarity bit (D6) When this bit is set, the VIC responds to interrupts as active High if bit 5 is set (level sensitive) or on a rising edge if bit 5 is cleared (edge sensitive). When clear, the VIC responds to active Low or falling edges.
  • Page 122 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Local Interrupt Control Registers: IPL Value bit field (D2-D0) This value is inverted and driven onto the IPL lines when a local interrupt is presented on the LIRQ1-7* signals and bit 7 of this register is clear (enabled).
  • Page 123 500-017586-000 VMIVME-7586 REGISTERS IPL encoding for the four module switch interrupts. This register is initialized to a value of $F8 upon powerup or hard reset. ICMS Interrupt Control Register ICMSICR (VIC offset I/O $447) ICMS3 ICMS2 ICMS1 ICMS0 Mask Mask Mask Mask Value...
  • Page 124 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Error Group Interrupt Control Register: ACFAIL Interrupt Mask bit (D7) When this bit is clear, the VIC generates a local interrupt when ACFAIL* is detected as asserted. ACFAIL Mask Bit Function The VIC generates a local interrupt when ACFAIL* is detected as asserted The VIC will not generate a local interrupt when ACFAIL* is detected as asserted (default)
  • Page 125 500-017586-000 VMIVME-7586 REGISTERS Error Group Interrupt Control Register: IPL Value bit field (D2-D0) This value is inverted and driven onto the IPL signals when an error group interrupt is acknowledged. ICGS Interrupt Vector Base Register The ICGS Interrupt Vector Base Register (ICGSIVBR) is a read/write byte register at VIC offset I/O address $44F.
  • Page 126 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 programmed with a unique number for each VIC interrupt controller in the chassis to enable identiÞcation encoding for bits 1-0. ICMS Interrupt Vector Base Register ICMSIVBR (VIC offset I/O $453) Module Module Status/ID Status/ID Status/ID Status/ID Status/ID...
  • Page 127 500-017586-000 VMIVME-7586 REGISTERS Local Interrupt Vector Base Register: Local Interrupt Number bit field (D2-D0) This read-only value indicates which local interrupt is pending during a local interrupt acknowledge cycle. These bits are used with bits 7-3 to provide a unique status/ID vector for each local interrupt. The numeric value of this Þeld indicates the local interrupt number.
  • Page 128 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Error/Status Interrupt ACFAIL* asserted Write post failed Arbitration timeout SYSFAIL* asserted VMEbus Interrupter interrupt acknowledge DMA complete Interprocessor Communications Registers Please refer to the Interprocessor Communications Registers detailed beginning on page 4-103. VMEbus Interrupt Request/Status Register The VMEbus Interrupt Request/Status Register (VIRSR) is a read/write byte register at VIC offset I/O address $483.
  • Page 129 500-017586-000 VMIVME-7586 REGISTERS $49F corresponding to IRQ1 Ð IRQ7, respectively. These registers contain a single 8-bit Þeld that provides the status/ID vector for the VMEbus interrupt acknowledge cycles. These registers are initialized to a value of $0F upon powerup or hard reset. I/O Address Interrupt $487...
  • Page 130 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Transfer Timeout Register: VMEbus Timeout Period bit field (D7-D5) DeÞnes the VMEbus timeout. Note that the hardware timer, if enabled, will override all settings here except the 4 µs value. See the discussion concerning the system controller functions on page 4-7. VMEbus Timeout (µs) 64 (default)
  • Page 131 500-017586-000 VMIVME-7586 REGISTERS Transfer Timeout Register: Arbitration Timeout bit (D1) When this bit is set, the VIC as VMEbus arbiter has detected a VMEbus arbitration timeout. This is only used when conÞgured as the VMEbus system controller (SCON asserted). Arbitration Timeout Bit Function The VIC as VMEbus arbiter has not detected a VMEbus arbitration timeout (default) The VIC as VMEbus arbiter has detected a VMEbus arbitration...
  • Page 132 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Local Bus Timing Register The Local Bus Timing Register (LBTR) is a read/write byte register at VIC offset I/O address $4A7. This register provides timing control for PAS* and DS* signals when the VIC is local bus master. In the following descriptions, n is the binary value speciÞed in the bit Þelds.
  • Page 133 500-017586-000 VMIVME-7586 REGISTERS Local Bus Timing Register: Minimum PAS Asserted Time bit field (D3-D0) This Þeld speciÞes the minimum asserted time for the PAS* signal whenever the VIC is the local bus master. The time is speciÞed by (n+2) × 15.625 ns. The actual asserted time depends on a number of factors including local and VMEbus acknowledge timing.
  • Page 134 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Block Transfer Definition Register: Boundary Crossing Enable bits (D3-D2) When set, these bits enable both local and VMEbus 256-byte boundary crossing. Both bits must be set to enable BLT transfers on the VMIVME-7586. Block Transfer Definition Register: AMSR Enable bit (D1) When set, the VIC issues the address modiÞer code from the Address ModiÞer Source Register (AMSR) during block transfers.
  • Page 135 500-017586-000 VMIVME-7586 REGISTERS In the current implementation, the RMC* signal is provided by the 5x86 LOCK* signal. This provides the capability to perform a RMW signal. Interface Configuration Register: RMC Control Bit 1 (D5) This bit must remain clear. Interface Configuration Register: Deadlock Signaling bit field (D4-D3) These bits conÞgure deadlock signaling.
  • Page 136 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Interface Configuration Register: SCON Status bit (D0) This read-only bit contains the value of the SCON* pin. When set, the VIC is not the VMEbus system controller. When clear, the VIC is the VMEbus system controller.
  • Page 137 500-017586-000 VMIVME-7586 REGISTERS Arbiter/Requester Configuration Register: DRAM Refresh bit (D4) When this bit is set, the VIC performs CAS-before-RAS (DS* before PAS*) refresh functions. This bit should always remain clear on the VMIVME-7586. DRAM Refresh Bit Function The VIC performs no DRAM refresh functions (default) The VIC performs CAS-before-RAS (DS* before PAS*) refresh functions.
  • Page 138 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 user-deÞned address modiÞer codes. This bit is clear by default; it is rarely necessary to change the default setting. AM2-0 Option Bit Function The user-defined address modifier code (bits 5-0) is unqualified (default) The VIC issues the AM2-0 codes based on bits 5-3 of this register and address bits A27/A26 according to Table 4-1 on page 4-11 Address Modifier Source Register: AM5-3 Slave Qual bit (D6) When this bit is set, the VIC uses bits 5-3 in qualifying for slave accesses in...
  • Page 139 500-017586-000 VMIVME-7586 REGISTERS to be used for a speciÞc operation, it is important that they be cleared prior to starting that operation. Bus Error Status Register BESR (VIC offset I/O $4BB) VMEbus VMEbus Local Bus VMEbus VMEbus Local Bus SLSEL0 SLSEL1 Acquire Master...
  • Page 140 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 BERR and LBERR statuses and DMA termination statuses. This register is initialized to a value of $60 upon powerup or hard reset. DMA Status Register DMASR (VIC offset I/O $4BF) Master BERR LBERR VMEbus Local Bus Block Write...
  • Page 141 500-017586-000 VMIVME-7586 REGISTERS Slave Select 0 Control Register 0 The Slave Select 0 Control Register 0 (SS0CR0) is a read/write byte register at VIC offset I/O address $4C3. This register provides control of the slave selection 0 facilities of the VIC, which is dedicated to A32 access only on the VMIVME-7586.
  • Page 142 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Slave Select 0 Control Register 0: D32 Enable bit (D4) When this bit is set, D32 slave operations are enabled for SLSEL0. This bit has no effect for enabling D32 master accesses. D32 Enable Bit Function (D32 Slave Access Control) D32 slave operations are disabled for SLSEL0 (default) D32 slave operations are enabled for SLSEL0 Slave Select 0 Control Register 0: Address Space Configuration bit field (D3-D2)
  • Page 143 500-017586-000 VMIVME-7586 REGISTERS Slave Select 0 Control Register 1 The Slave Select 0 Control Register 1 (SS0CR1) is a read/write byte register at VIC offset I/O address $4C7. This register provides the various access and acquisition timings for slave transfers and slave block transfers for SLSEL0* in addition to data acquisition timing for master block transfers with local DMA.
  • Page 144 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Slave Select 0 Control Register 1: Timing Field 1 bit field (D7-D4) This bit Þeld establishes the following data access/acquisition timings: ¥ Second and subsequent cycle of a slave block transfer for SLSEL0* (SBAT1) ¥...
  • Page 145 500-017586-000 VMIVME-7586 REGISTERS Slave Select 0 Control Register 1: Timing Field 0 bit field (D3-D0) This bit Þeld establishes the following data access/acquisition timings: ¥ Single-cycle slave access timing for SLSEL0* (SAT) ¥ First cycle of a slave block transfer for SLSEL0* (SBAT0) ¥...
  • Page 146 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Slave Select 1 Control Register 0 The Slave Select 1 Control Register 0 (SS1CR0) is a read/write byte register at VIC offset I/O address $4CB. This register provides control of the slave selection 1 facilities of the VIC, which is dedicated for A24 access on the VMIVME-7586.
  • Page 147 500-017586-000 VMIVME-7586 REGISTERS Slave Select 1 Control Register 0: D32 Enable bit (D4) When this bit is set, D32 slave operations are enabled for SLSEL1. This bit has no effect for enabling D32 master accesses. D32 Enable Bit Function D32 slave operations are disabled for SLSEL1 (default) D32 slave operations are enabled for SLSEL1 Slave Select 1 Control Register 0: Address Space Configuration bit field (D3-D2) In the VMIVME-7586 implementation, SLSEL1 is dedicated to A24 slave...
  • Page 148 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Slave Select 1 Control Register 1 The Slave Select 1 Control Register 1 (SS1CR1) is a read/write byte register at VIC offset I/O address $4CF. This register provides the various access and acquisition timings for slave transfers and slave block transfers for SLSEL1*.
  • Page 149 500-017586-000 VMIVME-7586 REGISTERS Slave Select 1 Control Register 1: Timing Field 1 (D7-D4) This bit Þeld establishes the following data access/acquisition timing: ¥ Second and subsequent cycle of a slave block transfer for SLSEL1* (SBAT1) The delays are programmed in multiples of the 64 MHz clock period according to the following table: Timing Delay...
  • Page 150 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Slave Select 1 Control Register 1: Timing Field 0 bit field (D3-D0) This bit Þeld establishes the following data access/acquisition timings: ¥ Single-cycle slave access timing for SLSEL1* (SAT) ¥ First cycle of a slave block transfer for SLSEL1* (SBAT0) The delays are programmed in multiples of the 64 MHz clock period according to the following table: Timing...
  • Page 151 500-017586-000 VMIVME-7586 REGISTERS Release Control Register The Release Control Register (RCR) is a read/write byte register at VIC offset I/O address $4D3. This register conÞgures the VMEbus release mode. The burst count for block transfers with local DMA (and VME64 block transfers for controllers with the VIC64 option installed) is also conÞgured in the RCR.
  • Page 152 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Block Transfer Control Register The Block Transfer Control Register (BTCR) is a read/write byte register at VIC offset I/O address $4D7. This register provides control of the VIC block transfers. The local interleave periods and data direction are deÞned in this register.
  • Page 153 500-017586-000 VMIVME-7586 REGISTERS transfer. When performing BLT transfers, bit 6 must not be cleared until after the BLT is complete. Block Transfer with DMA Bit Function Concludes a block transfer with local DMA in progress (default) Enables block transfers with local DMA (Bits D7 and D5 must be clear) Block Transfer Control Register: MOVEM Enable bit (D5) Since MOVEM transfer mode is not supported by the VMIVME-7586, this...
  • Page 154 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Block Transfer Length Registers The Block Transfer Length Registers (BTLR1-0, or BTLR2-0 on controllers with the VIC64 option installed) are read/write byte registers at VIC offset I/O addresses $4E7 (BTLR2 on the VIC64 only), $4DB (BTLR1), and $4DF (BTLR0).
  • Page 155 500-017586-000 VMIVME-7586 REGISTERS System Reset Register The System Reset Register (SRR) is a read/write byte register at VIC offset I/O address $4E3. The system reset register provides the means to perform a VMEbus system reset (SYSRESET* asserted). Writing a value of $F0 causes this function to occur.
  • Page 156 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Interprocessor Communications Switch Register The Interprocessor Communications Switch Register (ICSR) is a read/write byte register at VIC offset I/O address $45F. This register provides setting, clearing, and monitoring of the interprocessor switch interrupts by way of the local bus. If the switch interrupts are enabled, setting these bits (more precisely, a clear-to-set transition) causes a local interrupt to occur in the same way as if the switch was set over the VMEbus.
  • Page 157 500-017586-000 VMIVME-7586 REGISTERS Interprocessor Communication Registers The Þve Interprocessor Communication Registers (ICR0-4) are read/write byte registers at VIC offset I/O addresses $463, $467, $46B, $46F, and $473, respectively. Their VMEbus slave Short I/O offset addresses are $01, $03, $05, $07, and $09, responding to both privileged and nonprivileged accesses.
  • Page 158 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Reset/Halt Status Register: IRESET Status bit (D7) On a VMEbus read, this bit indicates that the VIC is in a reset state. On a local bus read, this bit is set whenever ACFAIL* is asserted. This bit is read-only.
  • Page 159 VMIVME-7586 asserts SYSFAIL* automatically after any reset. Since other controllers on the VMEbus may not function normally while the SYSFAIL* line is active, VMIC recommends that the SYSFAIL Mask bit be set immediately after powerup or reset initialization routines, even if no VMEbus activity is planned.
  • Page 160 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 Mailbox Semaphore Register: VMEbus Master Status bit (D5) This read-only bit is set whenever the VIC is the VMEbus master, and the VIC is asserting AS*. This bit is not set when the VIC is VMEbus master to an idle bus in ROR and BCAP release modes.
  • Page 161 500-017586-000 VMIVME-7586 REGISTERS these registers is irrelevant; any write access performs the associated function. For example, any write to address $21 sets the ICMS0 switch, causing an interrupt on all masters that have not masked their ICMS0 switch. Set/Clear ICMS Switch Registers (Slave-Only) ICMS0-3 S/C (VMEbus Slave Short I/O offset address $20-$27) Any write access performs the associated set or clear function.
  • Page 162 ¥ No components of adjacent boards are disturbed when inserting or removing the board from the chassis ¥ Quality of cables and I/O connections If products must be returned, contact VMIC for a Return Material Authorization (RMA) Number. This RMA Number must be obtained prior to any return .
  • Page 163 APPENDIX CONNECTOR PINOUTS IN THIS APPENDIX: SECTION 1 - INTRODUCTION SECTION 2 - ETHERNET CONNECTOR PINOUT SECTION 3 - FLOPPY DRIVE CONNECTOR PINOUT SECTION 4 - IDE HARD DRIVE CONNECTOR PINOUT A-5 SECTION 5 - KEYBOARD CONNECTOR PINOUT SECTION 6 - PC/104 CONNECTOR PINOUT SECTION 7 - PRINTER CONNECTOR PINOUT SECTION 8 - SERIAL CONNECTOR PINOUT A-10...
  • Page 164 APPENDIX A - CONNECTOR PINOUTS 500-017586-000 COM1 Port RS-232 COM2 Port RS-232 Power and Status Indicators Reset Switch PC/104 Bus J3 PC/104 Bus J2 Parallel Port LPT1 PC/104 Expansion Site Monitor Port Ethernet Port Keyboard Port VMIVME-7586 Figure A-1 VMIVME-7586 Connector Locations VMIVME-7586 PRODUCT MANUAL...
  • Page 165 500-017586-000 ETHERNET CONNECTOR PINOUT SECTION 2 - ETHERNET CONNECTOR PINOUT On controller boards with an Ethernet option, a D15 female connector provides the Ethernet AUI interface. The pinout diagram for the Ethernet connector is shown in Figure A-2. ETHERNET CONNECTOR FUNCTION Reserved +12 VDC...
  • Page 166 APPENDIX A - CONNECTOR PINOUTS 500-017586-000 SECTION 3 - FLOPPY DRIVE CONNECTOR PINOUT The ßoppy drive connector is a dual-row 34-pin header connector. Pin 1 marks the beginning of the odd-numbered row. Most standard PC compatible ßoppy disk drives use this pinout, which is shown in Figure A-3.
  • Page 167 500-017586-000 IDE HARD DRIVE CONNECTOR PINOUT SECTION 4 - IDE HARD DRIVE CONNECTOR PINOUT Figure A-4 describes the pin assignment for the 40-pin IDE/ATA hard drive header connector. Like the ßoppy header connector it has an odd-numbered row and an even-numbered row. Pin 40 Pin 2 DIRECTION...
  • Page 168 APPENDIX A - CONNECTOR PINOUTS 500-017586-000 SECTION 5 - KEYBOARD CONNECTOR PINOUT The keyboard connector is a standard 6-pin female mini-DIN PS/2 style connector shown in Figure A-5; an adapter is supplied to connect a keyboard with a larger PC/AT-style connector to the VMIVME-7586. The PC/AT-style connector pinout is shown in Figure A-6.
  • Page 169 500-017586-000 PC/104 CONNECTOR PINOUT SECTION 6 - PC/104 CONNECTOR PINOUT Controllers supporting PC/104 expansion sites have a pair of header connectors which function as standard PC/104 connectors J1 and J2. The PC/104 speciÞcation designates pins by rows lettered A-D and numbers. The pin numbering is rather unusual;...
  • Page 170 APPENDIX A - CONNECTOR PINOUTS 500-017586-000 Table A-1 PC/104 Connector Pinout (Continued) J1 ROW A J1 ROW B J2 ROW C J2 ROW D SA11 SYSCLK SA10 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2 BALE +5 V VMIVME-7586 PRODUCT MANUAL...
  • Page 171 500-017586-000 PRINTER CONNECTOR PINOUT SECTION 7 - PRINTER CONNECTOR PINOUT The printer port shown in Figure A-8 uses a D25 female connector typical of any PC/AT system. PRINTER CONNECTOR DIRECTION FUNCTION In/Out Data Strobe In/Out Bidirectional Data D0 In/Out Bidirectional Data D1 In/Out Bidirectional Data D2 In/Out...
  • Page 172 APPENDIX A - CONNECTOR PINOUTS 500-017586-000 SECTION 8 - SERIAL CONNECTOR PINOUT Each standard RS-232 serial port connectors is either a D9 male as shown in the upper drawing in Figure A-9 or an RJ45 jack like the lower drawing in Figure A-9.
  • Page 173 500-017586-000 VIDEO CONNECTOR PINOUT SECTION 9 - VIDEO CONNECTOR PINOUT The video port uses a standard high-density D15 VGA connector. Figure A-10 shows the pinout. VIDEO CONNECTOR DIRECTION FUNCTION Green Blue Reserved Ground Ground Ground Ground Reserved Ground Reserved Reserved Horizontal Sync Vertical Sync Reserved...
  • Page 174 APPENDIX A - CONNECTOR PINOUTS 500-017586-000 SECTION 10 - VMEbus CONNECTOR PINOUT Figure A-11 shows the location of the VMEbus P1 and P2 connectors and their orientation. Table A-2 shows the pin assignments for the VMEbus connectors. Note that only Row B of connector P2 is used: all other pins on P2 are reserved and should not be connected.
  • Page 175 500-017586-000 VMEbus CONNECTOR PINOUT Table A-2 VMEbus Connector Pinout (Continued) P1 ROW A P1 ROW B P1 ROW C P2 ROW B NUMBER SIGNAL SIGNAL SIGNAL SIGNAL IACK IACKIN SERCLK IACKOUT SERDAT IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 -12 V +5 V STDBY +12 V +5 V...
  • Page 176 APPENDIX ETHERNET OPTION IN THIS APPENDIX: SECTION 1 - INTRODUCTION SECTION 2 - ETHERNET SOFTWARE COMPATIBILITY B-2 SECTION 3 - ETHERNET DRIVER SOFTWARE SECTION 4 - ETHERNET DIAGNOSTIC SOFTWARE SECTION 5 - TECHNICAL DETAILS SECTION 1 - INTRODUCTION The VMIVME-7586 PC/AT compatible VMEbus controller board can be ordered with the Ethernet Mezzanine option.
  • Page 177 APPENDIX B - ETHERNET OPTION 500-017586-000 COM1 Port RS-232 COM2 Port RS-232 Power and Status Indicators Reset Switch PC/104 Bus J3 PC/104 Bus J2 Parallel Port LPT1 PC/104 Expansion Site Monitor Port Ethernet Port Snap-In Spacers Keyboard Port VMIVME-7586 Figure B-1 Location of the Ethernet Mezzanine SECTION 2 - ETHERNET SOFTWARE COMPATIBILITY The Ethernet Mezzanine is based on National SemiconductorÕs DP83905...
  • Page 178 500-017586-000 ETHERNET DRIVER SOFTWARE NE2000-compatible card should execute correctly on the VMIVME-7586 with the Ethernet Mezzanine installed. SECTION 3 - ETHERNET DRIVER SOFTWARE Customers must supply their own driver software for use with the Ethernet Mezzanine. The Ethernet Mezzanine supports the following popular driver software: ¥...
  • Page 179 APPENDIX B - ETHERNET OPTION 500-017586-000 Test the Ethernet Mezzanine with the NIC Inspector as follows: 1. From the root directory of the ßoppy disk, enter to begin INSPECT execution. 2. Use the cursor keys to select an I/O address of 320 (the factory default).
  • Page 180 500-017586-000 TECHNICAL DETAILS SECTION 5 - TECHNICAL DETAILS The Ethernet Mezzanine is an ISA bus peripheral responding to 32 byte in I/O space at $0320 through $033F (the factory default I/O address). If a user-installed Boot EPROM resides in the U1 socket and is enabled, the Ethernet Mezzanine also occupies up to 32 Kbyte in ISA memory space at a user-selected address.
  • Page 181 APPENDIX B - ETHERNET OPTION 500-017586-000 STOP ! Use extreme caution when attempting to make changes to Boot EPROM options. It is possible to select an address range that conßicts with the system VGA area or the Real Mode VMEbus Window. Conßicting addresses can cause SERIOUS problems including a FATAL option.
  • Page 182 VMEbus master running software stored in the ßash memory. The Flash Memory Mezzanine emulates a 1.44 Mbyte ßoppy diskette using VMIC-proprietary Flash BIOS. The user can transfer the programs, control, and batch information from a 1.44 Mbyte ßoppy diskette (easily formatted with DOS system Þles) to the Flash Memory Mezzanine.
  • Page 183 APPENDIX C - FLASH MEMORY OPTION 500-017586-000 SECTION 2 - PREPARING THE FLASH MEMORY The Flash Memory Mezzanine has a jumper that controls write access to the ßash memory. This horizontal jumper is located on the side of the Flash Memory Mezzanine as shown in Figure C-1.
  • Page 184 5. The VMIVME-7586 with 2 Mbyte Flash Memory option is shipped with a 3.5 inch diskette containing the programming utility PFLASH.EXE Insert the VMIC diskette in the ßoppy drive and execute PFLASH.EXE The PFLASH program prompts for the user-formatted ßoppy to be reinserted.
  • Page 185 APPENDIX C - FLASH MEMORY OPTION 500-017586-000 SECTION 4 - USING FLASH MEMORY AS BOOT DEVICE 1. To conÞgure the VMIVME-7586 as a diskless VMEbus master, Þrst make sure the Flash Memory Mezzanine has system Þles copied onto it according to the previous procedure. 2.
  • Page 186 500-017586-000 TECHNICAL DETAILS The Flash BIOS is conÞgured from the factory to be read-only at memory range $C8000 Ð $CFFFF with a byte-wide data path. All I/O accesses are at 16-bit wide addresses $300, $302, and $304 (even though the Þeld at $302 contains only four valid data bits).
  • Page 187 APPENDIX C - FLASH MEMORY OPTION 500-017586-000 SECTION 7 - PROGRAMMING Please refer to the following publications by Intel or AMD for 28F020 programming algorithm information: 1994 Flash Memory: Volume I Intel Corporation Intel Literature Sales Department P.O. Box 7641 Mt.
  • Page 188 BASIC INPUT / APPENDIX OUTPUT SYSTEM IN THIS APPENDIX: SECTION 1 - INTRODUCTION SECTION 2 - STANDARD FEATURES SECTION 3 - QUICK SETUP SECTION 4 - PROGRAM DESCRIPTION SECTION 5 - PROGRAM MENUS AND MENU ITEMS SECTION 6 - EXITING THE PhoenixBIOS D-23 SECTION 7 - STATUS AND ERROR MESSAGES D-26...
  • Page 189 APPENDIX D - BASIC INPUT / OUTPUT SYSTEM 500-017586-000 • Detection of coprocessor • Memory caching • Selection of diskette types • Selection of fixed-disk type • User-defined fixed-disk types • Selection of video display • Support for servers without keyboard and video •...
  • Page 190 500-017586-000 QUICK SETUP PhoenixBIOS Setup - Cop yright 1985 - 94 Phoenix Technologies Ltd. Main Exit Item Specif i c Help System T ime: [15:36:05] System Date: [01/21/95] Diskette A: [1.44 MB, 3.5”] Diskette B: [Not Installed] IDE Adapter 0 Master (C: 425 MB) IDE Adapter 0 Slave (None)
  • Page 191 APPENDIX D - BASIC INPUT / OUTPUT SYSTEM 500-017586-000 PhoenixBIOS Setup - Copyright 1985 - 94 Phoenix Technologies Ltd. Main IDE Adapter 0 Master (None) Item SpecificHelp Autotype Fixed Disk: [Press Enter] Attempts to automatically detect [None] Type: the drive type for Cylinders: drives that comply with Heads:...
  • Page 192 500-017586-000 PROGRAM DESCRIPTION menu is displayed. Exit PhoenixBIOS Setup - Copyright 1985 - 94 Phoenix Technologies Ltd. Exit Item Specific Save changes & Exit Help Discard changes & Exit Load Default Values Load Previous Values Save Changes F1 Help -/+ Change Values Select Item F9 Setup Defaults ESC Exit...
  • Page 193 APPENDIX D - BASIC INPUT / OUTPUT SYSTEM 500-017586-000 USER INTERFACE , shown below, is the opening display. Using the following Main Menu menu display as an example, this section describes screen elements in both menus.. Main Exit PhoenixBIOS Setup - Cop yright 1985 - 94 Phoenix Technologies Ltd. Main Exit Item Specif i cHelp...
  • Page 194 500-017586-000 PROGRAM DESCRIPTION 6. Keystroke control summary in the legend bar shows all keystrokes necessary to move through the programÕs menu system. The next section, Control Key Summary , explains the function of each key. CONTROL KEY SUMMARY Use the following keys to move through the program and modify program values: Table D-1 PhoenixBIOS Setup Keystroke Actions KEYSTROKE...
  • Page 195 APPENDIX D - BASIC INPUT / OUTPUT SYSTEM 500-017586-000 SECTION 5 - PROGRAM MENUS AND MENU ITEMS MAIN MENU (Figure D-3) contains items and sub-menus to conÞgure Main Menu system components such as the time and date, ßoppy/hard disk drives, video adapter type, and keyboard type.
  • Page 196 500-017586-000 PROGRAM MENUS AND MENU ITEMS System Time Sets the internal system clock to hour:minutes:seconds System Date Sets the internal system date to include the month/date/year Diskette A:/B: ConÞgures ßoppy drives to the appropriate disk size. Select one of the following settings: 360 KB 5-1/4 inch 1.2 MB 5-1/4 inch 720 KB 3-1/2 inch...
  • Page 197 APPENDIX D - BASIC INPUT / OUTPUT SYSTEM 500-017586-000 Þeld. Extended memory is addressed from just above the Extended Memory 1 Mbyte Real Mode boundary to the 64 Mbyte level. IDE Adapter 0 Master/IDE Adapter 0 Slave Sub-menus The IDE adapters control the hard disk drives. The PhoenixBIOS supports up to two IDE adapters;...
  • Page 198 500-017586-000 PROGRAM MENUS AND MENU ITEMS Type Sets the disk type if you do not use the feature. You can Autotype Fixed disk select a predeÞned Þxed disk type or manually conÞgure all drive parameters. user-deÞned disk parameters. Set all disk User parameters.
  • Page 199 APPENDIX D - BASIC INPUT / OUTPUT SYSTEM 500-017586-000 Table D-2 PhoenixBIOS Fixed Disk Table Type Cylinders Head Sectors Wrt Pre Should always be set to None. Reserved 1024 D-12 VMIVME-7586 PRODUCT MANUAL...
  • Page 200 500-017586-000 PROGRAM MENUS AND MENU ITEMS Table D-2 PhoenixBIOS Fixed Disk Table (Continued) Type Cylinders Head Sectors Wrt Pre 1218 1224 1024 1024 Cylinders Sets the number of cylinders: 1 to 2048 Heads Sets the number of read/write heads: 1 to 16 Sectors/Track Sets the number of sectors per track: 1 to 64...
  • Page 201 APPENDIX D - BASIC INPUT / OUTPUT SYSTEM 500-017586-000 MEMORY CACHE SUB-MENU The Memory Cache sub-menu contains items that enable caching and the cache shadowing. Memory cache is a special storage area of static RAM (SRAM). The cache shadow is a speciÞed portion of dynamic RAM (DRAM).
  • Page 202 500-017586-000 PROGRAM MENUS AND MENU ITEMS Internal Cache Controls the processorÕs internal eight Kbyte cache memory: *Enabled - causes data contained in the main memory to be copied into the cache where it can be processed faster. - turns off internal cache. Disabled External Cache This menu item is displayed only on controllers with an external cache option.
  • Page 203 APPENDIX D - BASIC INPUT / OUTPUT SYSTEM 500-017586-000 Region 0, size: deÞnes the size of noncacheable Multiples of 16 region 0 in Kbyte. The factory default is 128 Kbyte. makes this region available for Disabled cache. Region 1, start: DeÞnes the start of noncacheable Region 1 multiples of 64 Kbyte.
  • Page 204 500-017586-000 PROGRAM MENUS AND MENU ITEMS PhoenixBIOS Setup - Cop yright 1985 - 94 Phoenix Technologies Ltd. Main Item Specif i cHelp Memory Shado w Enabled System Shado w [Enabled] Video shado w: Shadow Memory Re gions C800 - CFFF: [Disabled] D000 - DFFF: [Disabled]...
  • Page 205 APPENDIX D - BASIC INPUT / OUTPUT SYSTEM 500-017586-000 C800 - CFFF Enabled *Disabled D000 - DFFF Enabled *Disabled E000 - EFFF DeÞnes the VMEbus access, which should not be shadowed. This setting should always be disabled. Enabled *Disabled D-18 VMIVME-7586 PRODUCT MANUAL...
  • Page 206 500-017586-000 PROGRAM MENUS AND MENU ITEMS BOOT OPTIONS SUB-MENU The Boot Options sub-menu contains items that enable you to conÞgure system boot-up operations. From the , select and press Main Menu Boot Sequence <Enter> sub-menu appears (Figure D-7 on Boot Options page D-19).
  • Page 207 APPENDIX D - BASIC INPUT / OUTPUT SYSTEM 500-017586-000 -system boots without a keyboard. Uninstalled Boot Sequence Sets the systemÕs boot drive. *A: then C: - system attempts to boot from floppy drive A: then hard drive C:. - system attempts to boot from hard drive then C: then A: ßoppy drive...
  • Page 208 500-017586-000 PROGRAM MENUS AND MENU ITEMS Summary Screen Controls display of the system conÞguration screen (Figure D-8) during system start-up. Enabled Disabled Copyright 1985 - 94 Phoenix Technologies, Ltd. CPU [66 MHz] 486DX2 System R OM FAB6 - FFFF Coprocessor Installed BIOS Date 01/28/95...
  • Page 209 APPENDIX D - BASIC INPUT / OUTPUT SYSTEM 500-017586-000 PhoenixBIOS Setup - Cop yright 1985 - 94 Phoenix Technologies Ltd. Main Item Specif i c Keyboard Features Help [Off] Numlock: [Disabled] Key click: Keyboard auto-repeat rate: [30/sec] Keyboard auto-repeat delay: [1/2 sec] F1 Help Select Item...
  • Page 210 500-017586-000 EXITING THE PhoenixBIOS Keyboard Autorepeat Rate Controls the speed at which a keystroke is repeated per second. The possible values for this item include: , and * characters per second. 2, 6, 10, 13.3, 18.5, 21.8, 26.7 Keyboard Autorepeat Delay Controls the delay time between keystrokes.
  • Page 211 APPENDIX D - BASIC INPUT / OUTPUT SYSTEM 500-017586-000 Menu items contained in the are described below. To use Exit Exit Menu items, highlight the desired item and press <Enter> Save Changes & Exit Stores selected values, exits the setup program, and reboots the system. The new menu items, stored in CMOS (battery-backed CMOS RAM), are used.
  • Page 212 500-017586-000 EXITING THE PhoenixBIOS Save Changes Stores selected menu items in CMOS without exiting the program. You can return to the other menu if you want to review and change your selections. Select this item and press Press at the conÞrmation prompt to save <Enter>.
  • Page 213 APPENDIX D - BASIC INPUT / OUTPUT SYSTEM 500-017586-000 SECTION 7 - STATUS AND ERROR MESSAGES Table D-3 describes status and error messages you may encounter when using the BIOS setup program. Messages are listed in alphabetical order. If your system fails after you made changes in the setup program, you may be able to correct the problem by entering the program and restoring the factory defaults.
  • Page 214 500-017586-000 STATUS AND ERROR MESSAGES Table D-3 PhoenixBIOS Status and Error Messages (Continued) Message Description/User Action Keyboard is not working. Check keyboard Keyboard error and cable connections. The BIOS discovered a “stuck” key and Keyboard error nn displays the scan code nn identifying the problem key.
  • Page 215 APPENDIX D - BASIC INPUT / OUTPUT SYSTEM 500-017586-000 Table D-3 PhoenixBIOS Status and Error Messages (Continued) Message Description/User Action Shadow RAM failed at offset nnnn of the Shadow RAM Failed at 64 Kbyte block at which the error was offset: nnnn detected.

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