Page 1 VMIVME-7586 PC/AT COMPATIBLE VMEbus CONTROLLER PRODUCT MANUAL DOCUMENT NO. 500-017586-000 B Revised July 21, 1997 VME MICROSYSTEMS INTERNATIONAL CORPORATION 12090 SOUTH MEMORIAL PARKWAY HUNTSVILLE, AL 35803-3308 (205) 880-0444 (800) 322-3616 FAX NO.: (205) 882-0859...
Page 2 VMIC assumes no responsibility resulting from omissions or errors in this manual, or from the use of information contained herein. VMIC reserves the right to make any changes, without notice, to this or any of VMIC’s products to improve reliability, performance, function, or design.
Page 3 2. Block transfer master(s) can reassert AS* and execute a BLT 64 Address Broadcast quickly (less than about 100 ns AS* hightime). The VIC64 as used on the VMIVME-7586 does not cause trouble during Master Mode. In other words, the VMIVME-7586 can safely do master BLT 64 transactions under all conditions. The described malfunction only occurs when the VIC64 is a BLT 64 slave (read from/by master) and the slave transaction is rapidly followed by another BLT 64 slave transaction to another slave.
Page 4 RECORD OF REVISIONS REVISION PAGES INVOLVED DATE CHANGE NUMBER LETTER 10/25/96 Release 96-0744 07/21/97 Cover and Page iii 97-0539 REV LTR PAGE NO. VME MICROSYSTEMS INT’L CORP. DOC. NO. 500-017586-000 12090 South Memorial Parkway Huntsville, AL 35803-3308 • (205) 880-0444...
Page 5 VMIC SAFETY SUMMARY THE FOLLOWING GENERAL SAFETY PRECAUTIONS MUST BE OBSERVED DURING ALL PHASES OF THE OPERATION, SERVICE, AND REPAIR OF THIS PRODUCT. FAILURE TO COMPLY WITH THESE PRECAUTIONS OR WITH SPECIFIC WARNINGS ELSEWHERE IN THIS MANUAL VIOLATES SAFETY STANDARDS OF DESIGN, MANUFACTURE, AND INTENDED USE OF THIS PRODUCT. VME...
Page 6 SAFETY SYMBOLS GENERAL DEFINITIONS OF SAFETY SYMBOLS USED IN THIS MANUAL Instruction manual symbol: the product is marked with this symbol when it is necessary for the user to refer to the instruction manual in order to protect against damage to the system. Indicates dangerous voltage (terminals fed from the interior by voltage exceeding 1000 volts are so marked).
Page 7: Table Of Contents
TABLE OF CONTENTS CHAPTER 1 - INTRODUCTION ..........SECTION 1 - INTRODUCTION TO THE VMIVME-7586 ....... 1-1 SECTION 2 - ABOUT THIS MANUAL ........... 1-2 SECTION 3 - PRODUCT FAMILY ............1-3 SECTION 4 - REFERENCES ..............1-5 SECTION 5 - PC/AT FEATURES ............1-6 SECTION 6 - VMEbus FEATURES ............
Page 8 TABLE OF CONTENTS 500-017586-000 GENERAL RULE REGARDING OPERATING SYSTEMS ....2-8 CONFIGURATION EXAMPLES ............2-9 Configuring MS-DOS for the VMIVME-7586 ....... 2-9 Configuring Windows for the VMIVME-7586 ....... 2-10 CHAPTER 3 - PC/AT FUNCTIONS ........... 3-1 SECTION 1 - CPU FUNCTIONAL OVERVIEW ........3-1 SECTION 2 - PHYSICAL MEMORY ............
Page 9 SECTION 8 - VMEbus REQUESTER ............ 4-40 SECTION 9 - READ-MODIFY-WRITE CYCLES ........4-40 SECTION 10 - BLOCK TRANSFERS ............ 4-42 DRAM REFRESH CONSIDERATIONS ..........4-42 MASTER BLT OPERATION .............. 4-43 SLAVE BLT OPERATION ..............4-45 VMIVME-7586 PRODUCT MANUAL viii...
Page 10 The Byte-Swapping Problem Defined .......... 4-47 Byte Swapping and the VMEbus ..........4-48 VMIVME-7586 Byte-Swapping Hardware ........4-49 Master/Slave Byte Swapping ............4-51 SECTION 13 - VMIVME-7586 REGISTERS .......... 4-52 REGISTER MAPS ................4-52 SYSTEM REGISTER DETAILS ............4-58 General Purpose Command Register .......... 4-58 Product ID Register ..............
Page 11 Set/Clear ICMS Switch Registers (Slave-Only) ......4-108 CHAPTER 5 - MAINTENANCE ..........SECTION 1 - MAINTENANCE ............... 5-1 SECTION 2 - MAINTENANCE PRINTS ..........5-1 APPENDIX A - CONNECTOR PINOUTS ........SECTION 1 - INTRODUCTION .............. A-1 VMIVME-7586 PRODUCT MANUAL...
Page 12 SECTION 1 - INTRODUCTION .............. C-1 SECTION 2 - PREPARING THE FLASH MEMORY ......C-2 SECTION 3 - COPYING FILES TO FLASH MEMORY ......C-3 SECTION 4 - USING FLASH MEMORY AS BOOT DEVICE ....C-4 VMIVME-7586 PRODUCT MANUA L...
Page 13 Autotype Fixed Disk ..............D-10 Type ..................... D-11 Cylinders ..................D-13 Heads ................... D-13 Sectors/Track ................D-13 Write Precomp ................D-13 MEMORY CACHE SUB-MENU ............D-14 Internal Cache ................D-15 External Cache ................D-15 Cache Shadow Region ..............D-15 VMIVME-7586 PRODUCT MANUAL...
Page 14 Save Changes & Exit ..............D-24 Discard Changes & Exit ............... D-24 Load Default Values ..............D-24 Load Previous Values ..............D-24 Save Changes ................D-25 SECTION 7 - STATUS AND ERROR MESSAGES ....... D-26 xiii VMIVME-7586 PRODUCT MANUA L...
Page 15 LIST OF FIGURES Figure 1-1 VMIVME-7586 Board View ..........1-3 Figure 1-2 VMIVME-7586 Partial Block Diagram ........ 1-7 Figure 1-3 VMIVME-7586 VMEbus Functions ........1-9 Figure 2-1 I/O Port and Jumper Locations ......... 2-3 Figure 2-2 LED Position on the Front Panel ........2-5...
Page 16 500-017586-000 Figure 4-15 Byte Relationships Using the Big-Endian 68040 ..... 4-48 Figure 4-16 5x86-to-VMEbus Data Byte Lanes ........4-50 Figure A-1 VMIVME-7586 Connector Locations ......... A-2 Figure A-2 Ethernet Connector Pinout ..........A-3 Figure A-3 Floppy Drive Connector Pinout ........A-4 Figure A-4 IDE Hard Drive Connector Pinout ........
Page 17 ....2-4 Table 2-2 VMEbus Window Addresses ..........2-9 Table 3-1 VMIVME-7586 Memory Map ..........3-3 Table 3-2 VMIVME-7586 I/O Address Map ........3-5 Table 3-3 PC/AT Hardware Interrupts ..........3-8 Table 3-4 PC/AT Interrupt Vector Table ........... 3-9 Table 3-5 Parallel Port Modes ............
Page 18: Chapter 1 - Introduction
MS-DOS, Windows or OS/2 PC/AT compatible operating system. Its keyboard and video console interaction with the user is typical of a PC/AT. This PC/AT mode of the VMIVME-7586 is discussed in Chapter 3 of this manual.
Page 19: Section 2 - About This Manual
Where remainder = the fractional part of ( Linear Address ÷ 65536 ) Note that there are many possible segment:offset addresses for a single location. The formula above will provide a unique segment:offset address by forcing the segment to an even 64 Kbyte boundary, for example, $C000, VMIVME-7586 PRODUCT MANUAL...
Page 20: Section 3 - Product Family
$E000, and so forth. When using this formula, make sure to round the offset calculation properly! SECTION 3 - PRODUCT FAMILY Figure 1-1 shows a simpliÞed view of the VMIVME-7586 board. The VMIVME-7586 is one member of VMIC's line of PC/AT compatible VMEbus controllers, all of which combine a standard PC/AT architecture with the ability to control VMEbus slave boards.
Page 21 VMEbus interface. It also supports L1 write-back cache and in slave mode the board provides VMEbus remap to alternate local address capability. VMIC also has other support products for the PC/AT compatible VMEbus controller line. The VMIVME-7450 is a dual-slot module which holds one 3.5 inch ßoppy drive and one 3.5 inch hard drive.
Page 22: Section 4 - References
There are many books widely available on the subject of general PC/AT use and programming. Some reference sources which may be particularly helpful in using or programming the VMIVME-7586 are listed below. i486 Microprocessor Programmer's Reference Manual and the Intel 486DX Microprocessor Data Book Intel Corporation Literature Sales Dept.
Page 23: Section 5 - Pc/At Features
CHAPTER 1 - INTRODUCTION 500-017586-000 SECTION 5 - PC/AT FEATURES The VMIVME-7586 performs all the functions of a standard IBM PC/AT motherboard with the following features: ¥ Single-Slot 6U Size ¥ High-performance 5x86 processor Standard 16 Kbyte internal cache ¥ The 5x86 processor supports level 1 (L1) write-back cache for near 90 MHz Pentium processor performance ¥...
Page 24 VIDEO DRAM 82091AA SUPER PC / 104 COM1 / EXPANSION COM2 A32 / A24 BYTE INTERRUPTER SITE ADDRESS BUFFERS SWAP & CONTROLLER Multiplexer SLAVE REMAP CIRCUIT & HANDLER FLOPPY DRIVE VMEbus Figure 1-2 VMIVME-7586 Partial Block Diagram VMIVME-7586 PRODUCT MANUAL...
Page 25: Section 6 - Vmebus Features
LED Indicators Front Panel Hard Drive Activity SECTION 6 - VMEbus FEATURES In addition to its PC/AT functions, the VMIVME-7586 has the following VMEbus features: ¥ Single-slot, 6U height VMEbus board ¥ Complete six line Address ModiÞer (AM-Code) programmability ¥ 32-bit data interface with separate hardware byte/word swapping for master and slave accesses ¥...
Page 26 Pri o ri t y I nt er ru pt U ti l i t y Figure 1-3 VMIVME-7586 VMEbus Functions Figure 1-3 shows the VMIVME-7586 functions in a typical VMEbus system. The VMIVME-7586 is a versatile single-board solution for VMEbus control with familiar PC/AT operation. VMIVME-7586 PRODUCT MANUAL...
Page 27 SECTION 7 - PC/104 EXPANSION SITE SECTION 8 - BIOS SETUP SECTION 9 - CONFIGURING OPERATING SYSTEMS SECTION 1 - INTRODUCTION This chapter describes unpacking, inspection, hardware jumper settings, connector deÞnitions, installation, system setup, and operation of the VMIVME-7586. VMIVME-7586 PRODUCT MANUAL...
Page 28: Chapter 2 - Installation And Setup
SECTION 3 - HARDWARE SETUP The VMIVME-7586 has been tested for system operation and shipped with factory-installed header jumpers. Figure 2-1 illustrates the physical location of the user-conÞgurable jumpers and connectors on the board.
Page 29 E1, E2, and E3 - Local VGA Adapter All Installed* Enabled Ethernet Port All Removed Disabled E24 - System Controller Installed* Enabled Not Installed Disabled Keyboard Port VMIVME-7586 * Indicates Factory Default ** Consult Factory Before Changing Figure 2-1 I/O Port and Jumper Locations VMIVME-7586 PRODUCT MANUAL...
Page 30: Table 2-1 Vmivme-7586 Jumper Functions And Settings
Enabled - System Reset Installed = Enabled (Default) Disable - Front Panel Reset Removed = Disabled NOTE: ANY OTHER JUMPER LOCATIONS ARE RESERVED FOR VMIC USE ONLY AND SHOULD NOT BE ALTERED FROM THE FACTORY DEFAULT SETTINGS. VMIVME-7586 PRODUCT MANUAL...
Page 31: Section 4 - Led Status Definition
* * * * * * * * * * DO NOT INSTALL OR REMOVE BOARD WHILE POWER IS APPLIED. The VMIVME-7586 conforms to the VMEbus physical speciÞcation for a 6U x 4HP dual Eurocard (dual height, single-slot width). It can be plugged directly into any standard chassis accepting this type of board.
Page 32: Section 6 - Front Panel Connectors
CHAPTER 2 - INSTALLATION AND SETUP 500-017586-000 3. Choose a chassis slot. The VMIVME-7586 may be attached to a dual P1/P2 VMEbus backplane or a single P1 backplane. A single P1 connection supplies enough power and allows 16-bit data transfers and 24-bit addressing, but for 32-bit data transfers and 32-bit addressing a dual P1/P2 backplane is required.
Page 33: Section 7 - Pc/104 Expansion Site
500-017586-000 PC/104 EXPANSION SITE a keyboard with a standard PC/AT connector to the VMIVME-7586. See Appendix A for connector pinouts and orientation. SECTION 7 - PC/104 EXPANSION SITE Expansion boards that are PC/104 compatible install directly to the VMIVME-7586Õs PC/104 Expansion Site (see Figure 2-1 on page 2-3).
Page 34: Section 8 - Bios Setup
The VMIVME-7586 is shipped from the factory with no hard or ßoppy drives conÞgured in CMOS. The BIOS Setup program must be run to conÞgure the speciÞc drives attached. It is recommended that the user follow the procedure for Quick BIOS Setup in Appendix D to properly conÞgure the system.
Page 35: Configuration Examples
VMEbus window is translated into a VMEbus access once VMEbus access is enabled. The complete VMIVME-7586 memory map is presented in Chapter 3, but for reference the address ranges to be excluded for the VMEbus Windows are listed in Table 2-2.
Page 36: Configuring Windows For The Vmivme-7586
Conﬁguring Windows for the VMIVME-7586 Microsoft Windows will run well on the VMIVME-7586, but the Real Mode VMEbus Window needs to be excluded from its memory manager. Edit the SYSTEM.INI Þle in the main Windows directory and add the following...
Page 37 3-15 SECTION 1 - CPU FUNCTIONAL OVERVIEW The VMIVME-7586 uses the 5x86 microprocessor as the CPU. The CPUÕs performance is achieved primarily with a 16 Kbyte write-back cache. Instructions are executed in the Integer Unit and the Floating Point Unit.
Page 38: Chapter 3 - Pc/At Functions
The VMIVME-7586 includes both the system and video BIOS in a single 128 K x 8 EPROM. The system portion of this ROM (at $F0000) is automatically shadowed, but for higher performance it is recommended that shadow RAM for the video BIOS be enabled (see Appendix D).
Page 39: Section 3 - Memory And I/O Port Maps
SECTION 3 - MEMORY AND I/O PORT MAPS MEMORY MAP The memory map for the VMIVME-7586 is shown in Table 3-1. All systems share this same memory map, although a VMIVME-7586 with less than the full 32 Mbyte of DRAM does not Þll the entire space reserved for On-Board Extended Memory.
Page 40: I/O Port Map
This limits the PC/104 address space to 1024 locations ($000-$3FF). The VMIVME-7586 incorporates all standard I/O peripherals of the PC/AT architecture such as keyboard, DMA, interrupt controllers, timers and real-time clock, as well as parallel and serial I/O ports, video registers, and ßoppy and hard drive task registers.
Page 41: Table 3-2 Vmivme-7586 I/O Address Map
500-017586-000 MEMORY AND I/O PORT MAPS Table 3-2 VMIVME-7586 I/O Address Map SIZE IN ASSOCIATED ADDRESS HARDWARE DEVICE PC/AT FUNCTION † BYTES JUMPERS RANGE DMA Controller 1 $000 - $00F ACC Micro 2040 Chip (Intel 8237A Compatible) $010 - $01F...
Page 42 CHAPTER 3 - PC/AT FUNCTIONS 500-017586-000 Table 3-2 VMIVME-7586 I/O Address Map (Continued) SIZE IN ASSOCIATED ADDRESS HARDWARE DEVICE PC/AT FUNCTION † BYTES JUMPERS RANGE VMEbus Interface Registers $140 - $14F Custom VMIC Hardware E24 & E11 (see Chapter 4 for details)
Page 43 Hardware jumper settings are discussed in Chapter 2. While these I/O ports are reserved for the listed functions, they are not implemented on the VMIVME-7586. They are listed here to make the user aware of the standard PC/AT usage of these ports.
Page 44: Section 4 - Pc/At Interrupts
Table 3-4 on page 3-9 details the vectors in the interrupt vector table. Table 3-3 PC/AT Hardware Interrupts AT FUNCTION COMMENTS Parity Errors Used by VMIVME-7586 VMEbus Interface (Must be enabled in BIOS Setup) System Clock/Calendar Set by BIOS Setup System Clock/Calendar Set by BIOS Setup Duplexed to IRQ9...
Page 45: Table 3-4 Pc/At Interrupt Vector Table
Same as Real Mode ROM BASIC Entry Point Same as Real Mode Bootstrap Loader Same as Real Mode IRQ8 Real-Time Clock Same as Real Mode Control/Break Handler Same as Real Mode Timer Control Same as Real Mode VMIVME-7586 PRODUCT MANUAL...
Page 46 (primary) VMEbus Interrupts IRQ12 Same as Real Mode (alternate) 75-7F 117-127 Reserved by DOS Same as Real Mode 80-F0 128-240 Reserved for BASIC Same as Real Mode F1-FF 241-255 Reserved by DOS Same as Real Mode 3-10 VMIVME-7586 PRODUCT MANUAL...
Page 47 Bus (or ISA bus). This is the same implementation used on the VMIVME-7586Õs PC/104 expansion port. Figure 3-1 depicts the VMIVME-7586 interrupt logic pertaining to VMEbus operations. Note that the NMI interrupt generated by the VMIVME-7586 must be enabled in the BIOS Setup (see Appendix D).
Page 48: Section 5 - Enhanced I/O Peripheral Ports
The VMIVME-7586 incorporates the Intel 82091AA Advanced Integrated Peripheral chip, also known as the AIP or Super I/O chip. This chip provides the VMIVME-7586 with a ßoppy drive controller, IDE hard drive interface, two serial ports, and one parallel port. While the ßoppy and hard...
Page 49: Serial Ports
Windows communications port drivers that address this problem. PARALLEL PORT The VMIVME-7586Õs enhanced parallel port may be conÞgured for any one of four modes as deÞned by IEEE Standard 1284 shown in Table 3-5. Table 3-5...
Page 50: Section 6 - Video Graphics Adapter
SECTION 6 - VIDEO GRAPHICS ADAPTER The monitor port on the VMIVME-7586 is controlled by a Cirrus Logic chip with 1 Mbyte video DRAM. The video controller chip is hardware and BIOS compatible with the IBM EGA and VGA standards and also supports VESA high-resolution and extended video modes.
Page 51: Section 7 - Pc/104 Expansion Site
I/O functions. VMICÕs VMIVME-7432 PC/104 to ISA Adapter is designed speciÞcally to mate with the VMIVME-7586, allowing it to use a standard half-length ISA bus board in the same chassis. This expansion allows low-cost or specialty ISA bus boards to be used in the same chassis with VMEbus equipment.
Page 52: Chapter 4 - Vmebus Functions
The register details are provided last for easy reference for the programmer familiar with the VMIVME-7586, but the novice will need to study the reference section as well. The Þrst-time VMIVME-7586 user is strongly urged to read through the functional sections with a copy of the register and bit maps (beginning on page 4-53) close at hand.
Page 53: Section 2 - Vmebus Interface
VMIVME-7586 and the VMEbus. Note that the VMEbus is connected to the 5x86 local bus. In Real Mode, the VMIVME-7586 uses a paging scheme to access any part of the 4 Gbyte of VMEbus addressing space 64 Kbyte at a time through the Real Mode VMEbus Window at $E0000.
Page 54 U t il i t y Figure 4-1 VMIVME-7586 VMEbus Functions In Protected Mode, the VMIVME-7586 can access the VMEbus through the Protected Mode VMEbus Window, which occupies 1024 Mbyte beginning at $4300 0000. This 1024 Mbyte space is divided into 16 equal spaces of 16 Mbyte, each corresponding to the VMEbus but with different VMEbus Address ModiÞers.
Page 55: Vmebus Interface Hardware
CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 VMEbus INTERFACE HARDWARE The VMIVME-7586 VMEbus hardware interface consists of a Cypress VIC64 VMEbus Interface Controller (hereafter referred to as the VIC or the VIC64), its companion VIC-to-Local bus Interface Circuitry (referred to as the VLIC), and three Cypress CY7C964.
Page 56 DRAM refresh is required or when the 2048 DMA controller needs the bus. The data multiplexer function is used to implement byte swapping. Byte swapping is implemented in both directions (both VMIVME-7586 acting as VMEbus master and VMIVME-7586 being accessed as a VMEbus slave). VMIVME-7586 PRODUCT MANUAL...
Page 57: Programming The Vmebus Interface
CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 The VLIC contains system registers that allow the VMIVME-7586 VMEbus interface to be programmed. These are discussed in detail in Section 13. The VLIC also contains hardware to translate the 68030-like interrupt structure of the VIC to the PC/AT interrupt structure.
Page 58: Section 3 - Vmebus Master Operation
The VMIVME-7586 VMEbus interface allows the 5x86 to access the VMEbus while in Real Mode or Protected Mode. In Real Mode, the VMIVME-7586 accesses the VMEbus using a paging scheme to address any part of the 4 Gbyte VMEbus through a 64 Kbyte window at $E0000. Prior to accessing this segment, address modiÞer information must be...
Page 59: Real Mode Access
The upper address bits are contained in the Extended/Standard Address Register (VMEbus address bits A31-A16). The lower address bits (VMEbus address bits A15-A0) are driven directly by the CPU. See Figure 4-4 on page 4-9 for a graphic representation of Real Mode VMEbus access. VMIVME-7586 PRODUCT MANUAL...
Page 60: Figure 4-4 Real Mode Vmebus Access
VMEbus MASTER OPERATION VIC64 REGISTER AMSR REGISTER AM5-AM0 SYSTEM REGISTER EXT_STD_ADDR REGISTER A31-A16 A15-A1 A15-A1 5x86 D31-00 D31-D0 5x86 = REAL MODE 5x86 A19-A16 = 1110 = $E GP_COMMAND VME_EN = 1 Figure 4-4 Real Mode VMEbus Access VMIVME-7586 PRODUCT MANUAL...
Page 61: Protected Mode Access
The address size and type for each region are shown in Table 4-1 on page 4-11. See Figure 4-5 on page 4-12 for a pictorial representation of Protected Mode access. 4-10 VMIVME-7586 PRODUCT MANUAL...
Page 62 Source Register (AMSR). Shaded ﬁelds deﬁne the address modiﬁer when the AM2-0 Option bit is set. The bit is clear by default. See the description of the Address Modiﬁer Source Register, page 4-85 for additional information. VMIVME-7586 PRODUCT MANUAL 4-11...
Page 63: Figure 4-5 Protected Mode Vmebus Access
A24 - SUPER CODE A31-A24 I/ O PORT $143 = $00 5x86 A25-A24 = 01 5x86 = PR OTECTED MODE 5x86 A31-A30 = 01 GP_COMMAND VME_EN = 1 A23-A1 A23-A1 D31-00 D31-D0 5X86 Figure 4-5 Protected Mode VMEbus Access 4-12 VMIVME-7586 PRODUCT MANUAL...
Page 64: 128 Mbyte - Protected Mode Access
The address size and type for each region are shown in Table 4-2. See Figure 4-6 on page 4-15 for a pictorial representation of 128 Mbyte Protected Mode access. VMIVME-7586 PRODUCT MANUAL 4-13...
Page 65 $7400 0000 - 32 (wrapping Block 77FF FFFF occurs) A24 Super Data / Super $7800 0000 - 32 (wrapping Block 7BFF FFFF occurs) A24 Super Pgm / Super $7C00 0000 - 32 (wrapping Block 7FFF FFFF occurs) 4-14 VMIVME-7586 PRODUCT MANUAL...
Page 66: Figure 4-6 128 Mbyte Protected Mode Vmebus Access
A24 - SUPER CODE A31-A27 Set I/O PORT $143 = $01 5x86 = PROTECTED MODE 5x86 A31-A30 = 01 GP_COMMAND VME_EN = 1 A26-A1 A26-A1 D31-D0 5x86 D31-00 Figure 4-6 128 Mbyte Protected Mode VMEbus Access VMIVME-7586 PRODUCT MANUAL 4-15...
Page 67: Section 4 - Vmebus Slave Operation
Table 4-2 on page 4-14). A byte, word, or longword access generates a VMEbus access. SECTION 4 - VMEbus SLAVE OPERATION The VMIVME-7586 has two resources that are accessible by VMEbus slave accesses: VIC interprocessor communication facilities and dual-port DRAM.
Page 68: Interprocessor Communications
The above VIC resources are accessible using VMEbus A16 Short I/O accesses (as well as from the VMIVME-7586 itself, except for the Set/Clear Switch Registers). Unlike all other interprocessor communications resources, the registers that set or clear global (ICGS) switches are only accessible from privileged VMEbus accesses.
Page 69 Address Mask register. The compare register is used to program a base address to be used by VMEbus to access the resource. The mask register is used to deÞne an address range that is used to access the resource. 4-18 VMIVME-7586 PRODUCT MANUAL...
Page 70 Address Compare. VMEbus address bits deÞned in the Slave A16 Address Compare register become ÒdonÕt caresÓ when the corresponding bit in the Slave A16 Address Mask register is programmed with a 1. See Figure 4-8 on page 4-20 for a graphic description of both registers. VMIVME-7586 PRODUCT MANUAL 4-19...
Page 71: Figure 4-8 Slave Compare Operation
Example: Program VIC ICRs to reside at VMEbus address $A500 1. Write 0xA500 data to Slave A16 Address Compare register. 2. Write 0x0 to Slave A16 Address Mask register. 3. Set Mailbox Enable bit in General Purpose Command system register. 4-20 VMIVME-7586 PRODUCT MANUAL...
Page 72: Dual-Ported Dram
4. Initialize the General Purpose Command Register. Other bits may be set depending on the application. DUAL-PORTED DRAM All of the VMIVME-7586Õs DRAM (1 - 32 Mbyte, depending on the memory option ordered) is accessible from the VMEbus. More accurately, all VMIVME-7586 physical memory is accessible from the VMEbus. This includes all of the DRAM, but also includes all physical resources within the Þrst megabyte of 5x86 address space (640 Kbyte of RAM, VGA RAM...
Page 73 The VMIVME-7586 slave interface allows the dual-port DRAM slave address to be programmed in software. Also, incoming accesses may be remapped throughout the 32 Mbyte space. In addition, the VMEbus can access the DRAM using either A32 Extended addressing or A24 Standard addressing.
Page 74 DRAM will now be accessible using VMEbus addresses $1200 0000 through $12FF FFFF. Example: Program the VMIVME-7586 slave interface to map 1 Mbyte of on-board DRAM to A24 VMEbus address $10 0000. 1. Write 0xXX10 data to Slave A32/A24 Address Compare register.
Page 75: Slave Access Memory Map
VMEbus slave accesses. The VMIVME-7586 local addresses which map to the VMEbus cannot be accessed since they are off-board resources and would require the VMIVME-7586 to be both VMEbus master and VMEbus slave simultaneously. Table 4-3 on page 4-25 describes accessible and nonaccessible memory regions.
Page 76: Address Remapping
VGA display DRAM $00000 - $9FFFF 640 Kbyte of DRAM * This region of the VMIVME-7586 local address space cannot be accessed from the VMEbus. A31-A25 of the VMIVME-7586 local address bus are forced to 0 when a VMEbus slave access occurs.
Page 77: Figure 4-9 Remap Of Vmebus Space To 5X86 Space
The code developed on a secondary VMEbus board could, for instance, use a 64 Kbyte range starting at 1 Mbyte in the VMEbus address space for shared array storage in the VMIVME-7586. In this particular case, if a high memory manager was used such as HIGHMEM.SYS, then system drivers maybe loaded in the VMIVME-7586Õs address space starting at 1 Mbyte...
Page 78 Sizing Buffered 5x86 Window Size Register Local ..Address Address VME A16 Local A16 Local A24 VME A24 ..Remap Address Register Figure 4-10 Slave Remap Circuit Overview VMIVME-7586 PRODUCT MANUAL 4-27...
Page 79: System Considerations
OR ANOTHER BUS TIMEOUT MODULE ELSEWHERE SYSTEM CONSIDERATIONS Some systems may require that a VMEbus master size the VMIVME-7586 on-board extended memory. In this case, it is important to know that VMEbus accesses to the VMIVME-7586 local address range $10 0000 Ð...
Page 80 VMEbus). During a VMIVME-7586 slave access, VMEbus address bits connect to the VMIVME-7586 local address bits as shown in Figure 4-11. Note that local address bits A31-A25 are always driven to 0 during a slave access. VMIVME-7586 PRODUCT MANUAL...
Page 81 A25 are pulled low during a slave access to avoid accessing memory outside the 32Mbyte range. The CY7C964 uses the VMEbus address lines A31through A24 to generate a valid board decode which is not depicted in this figure. Figure 4-11 Slave Addressing Detail 4-30 VMIVME-7586 PRODUCT MANUAL...
Page 82: Section 5 - System Controller Functions
The VMIVME-7586 generates VMEbus SYSCLK and SYSRESET* signals and provides the IACK driver only if it is conÞgured as a system controller. See Chapter 2 for information on jumpering the VMIVME-7586 as a system controller. After powerup or a hard reset, the VIC automatically asserts SYSRESET* for the required minimum of 200 ms.
Page 83: Section 6 - Vmebus Interrupt Handling
VMIVME-7586 local DRAM controller requires the local bus every 15.6 µs to refresh the DRAM. Therefore, to properly signal a bus error for master operations caused by the VMIVME-7586, a timeout of less than 15.6 µs is required in order to guarantee DRAM refresh timing.
Page 84: Table 4-4 Interrupt Priorities
ID for highest priority pending interrupt that is programmed with that level. The VMIVME-7586 allows the user to choose one of three PC/AT interrupt channels to be used for interfacing with the VIC interrupts: IRQ11, IRQ12, or the NMI.
Page 85: Table 4-5 Interrupt Level Assignments
The VIC to local bus interface (VLIC) relies on getting a DTACK from the VIC for synchronization with the 5x86 local bus. Failure to receive a VIC DTACK will lock the 5x86 bus. 4-34 VMIVME-7586 PRODUCT MANUAL...
Page 86 The VMIVME-7586 IRQ11 and IRQ12 interrupts are dedicated for use with the VIC and therefore are not shared by any other on-board resource. In contrast, the VMIVME-7586 NMI interrupt is shared by the VIC and other on-board circuitry. The PC/AT architecture deÞnes two possible sources for the NMI: on-board parity errors and off-board parity errors.
Page 87: Software Interrupts
ID register within the appropriate interrupt service routine. INTERRUPT ON BERR* The VMIVME-7586 allows the 5x86 to receive an interrupt if the VMIVME-7586 causes a VMEbus BERR*. This is particularly important feature given that the 5x86 CPU does not directly support bus error conditions.
Page 88: Interrupt Processing
PC/AT hardware. These operations are shown for the IRQ11 and IRQ12 interrupts in Figure 4-12 on page 4-38. Operation for the NMI interrupt is shown in Figure 4-13 on page 4-39. VMIVME-7586 PRODUCT MANUAL 4-37...
Page 89: Figure 4-12 Flowchart For Non-Nmi Interrupt Processing For Irq11
2 interrupt Initialize source vectors in VIC64 Write EOI to 8259 pic Unmask IR11 in 8259 PIC Write REARM_INT Register ISR Ready End ISR Figure 4-12 Flowchart for Non-NMI Interrupt Processing for IRQ11 4-38 VMIVME-7586 PRODUCT MANUAL...
Page 90: Figure 4-13 Flowchart For Nmi Interrupt Processing
IRQ is acknowledged by an off-board interrupt handler, the VIC supplies the vector associated with that interrupt provided the VMIVME-7586 IACKIN* signal is active. The VMIVME-7586 can be programmed to interrupt the CPU when a VMIVME-7586 issued VMEbus interrupt has been acknowledged. This is VMIVME-7586 PRODUCT MANUAL...
Page 91: Section 8 - Vmebus Requester
(RMW) cycles to be performed. Slave VMEbus RMW cycles require no special programming of the VMIVME-7586. The VIC will keep the local bus on behalf of the VMEbus slave access until the read and write portion of the cycle is completed. The 5x86 is not allowed to interrupt the local bus read-modify-write cycle.
Page 92 5x86 LOCK* bus signal. The 5x86 LOCK* signal is connected to the RMC* input of the VIC. When the VIC detects a master VMEbus request by the VMIVME-7586 and the activation of the RMC* input, a VMEbus RMW cycle is performed. Note that this ÒlockedÓ...
Page 93: Section 10 - Block Transfers
The function returns a nonzero value if the bit was clear prior to the set. Local bus RMW cycles performed by the 5x86 cannot be interrupted by the VMIVME-7586 VMEbus slave access. Therefore, it is desirable to set up a multiprocessing semaphore that is located in the VMIVME-7586 dual-port RAM.
Page 94: Master Blt Operation
MASTER BLT OPERATION The VMIVME-7586 performs BLT using the VIC local DMA mode. The ÒMOVEMÓ mode of VIC BLT is not supported on the VMIVME-7586. The VIC allows local DMA mode to be operated in accelerated mode or single cycle mode.
Page 95 0x01000000 in little-endian format Write A31-A16 of the target VMEbus address into EXT_STD_ADDR register. Then write 0x40881500 to 0xE0000. To transfer the same data in big-endian format, set the M_BIG_ENDIAN bit and then write 0x00158840 to 0xE0000. 4-44 VMIVME-7586 PRODUCT MANUAL...
Page 96: Slave Blt Operation
SS1CR0 registers. Also, program the corresponding SS0CR1 or SS1CR1 register to 0x0. Program the LBTR to 0xFF. SECTION 11 - VME64 FUNCTIONS A VMIVME-7586 with the VME64 installed may transfer 64 bits at a time using VME64 MBLT block transfers. MASTER VME64 OPERATION As deÞned in Section 13, the BTDR has additional bit Þelds that the VIC64...
Page 97: Section 12 - Byte Ordering
Byte(1) Double Byte(2-3) Byte(2) Byte(3) Double Byte(0-1) Byte(0) Byte(1) Quad Byte(0-3) Byte(0) Byte(1) Byte(2) Byte(3) It is important to note the major byte-ordering differences between the VMEbus and the Intel 5x86 CPU. In addition, communication between 4-46 VMIVME-7586 PRODUCT MANUAL...
Page 98: The Byte-Swapping Problem Defined
Òlittle-endianÓ ordering. The VMIVME-7586 uses an Intel 5x86 microprocessor, which uses little-endian byte ordering. Byte arrangement and the byte relationship between data in the processor and transferred data in memory are shown in Figure 4-14.
Page 99: Byte Swapping And The Vmebus
The VMEbus SpeciÞcation does not specify which byte of a multiple-byte transfer is most signiÞcant. The VMEbus SpeciÞcation does, however, require certain byte lanes to be associated with certain byte addresses. As shown in Table 4-6 on page 4-46, byte(0) must be transferred on data lines 4-48 VMIVME-7586 PRODUCT MANUAL...
Page 100: Vmivme-7586 Byte-Swapping Hardware
VMEbus with its byte lanes crossed. For example, the 5x86 uses D0-D7 to transfer a byte to address $00, while the VMEbus requires D8-D15 be used. For this reason, special hardware has been incorporated into the VMIVME-7586 to facilitate different kinds of byte swapping for varying circumstances. VMIVME-7586 Byte-Swapping Hardware...
Page 101: Figure 4-16 5X86-To-Vmebus Data Byte Lanes
Table 4-7 details this relationship. Table 4-7 Byte Swap Modes BIG-ENDIAN SIZE OF TRANSFER SWAP MODE BIT STATUS single byte byte-swap word (two bytes) byte-swap longword (four bytes) word-swap word (two bytes) direct longword (four bytes) direct 4-50 VMIVME-7586 PRODUCT MANUAL...
Page 102: Master/Slave Byte Swapping
On the VMIVME-7586, byte ordering can be programmed for either big endian or little endian in both directions (that is, whether the VMIVME-7586 is a VMEbus master or a VMEbus slave). Two bits in the General Purpose Command Register control the byte-ordering modes for master and slave accesses: Master Big-Endian, and Slave Big-Endian.
Page 103: Section 13 - Vmivme-7586 Registers
CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 SECTION 13 - VMIVME-7586 REGISTERS REGISTER MAPS The VMIVME-7586 has three groups of custom registers: ¥ System Registers (12) ¥ Interrupt Acknowledge Registers (3) ¥ VIC Registers (58) All registers are in I/O addressing space, but only the System Registers have a Þxed location: I/O $140 through I/O $152.
Page 104 Table 4-8 System Register Map REGISTER NAME PAGE MNEMONIC ACCESS D15 D14 D13 D12 D11 D10 D9 Master Slave Slave General-Purpose Status Mailbox Slave A24 4-58 GP_COMMAND Byte Write $140 Big- Big- Word Command Enable Enable Enable Endian Endian Enable Enable 4-61 Product ID...
Page 105: Table 4-9 Vic Register Map
ICGS Interrupt Vector 4-73 ICGSVBR $44F Status/ID Value Global Switch Number Base ICMS Interrupt Vector Module Switch 4-73 ICMSVBR $453 Status/ID Value Number Base Local Interrupt Vector 4-74 LIVBR $457 Status/ID Value Local Interrupt Number Base 4-54 VMIVME-7586 PRODUCT MANUAL...
Page 106 Minimum PAS Deasserted Time Minimu m PAS Asser ted T i m e asserted Time Accel. Boundary Dual- AMSR Block Transfer DeÞnition 4-81 BTDR $4AB Boundary Slave Block Master Crossing Path Enable Crossing Enable Transfer Enable Enable Enable VMIVME-7586 PRODUCT MANUAL 4-55...
Page 107 The VIC occupies 256 bytes of I/O addressing space from its base at offset $00 to offset $FF: all addresses within that space not assigned to a register are considered Reserved and should not be accessed. Shaded registers are unique because they are available to other VMEbus masters in slave access mode. 4-56 VMIVME-7586 PRODUCT MANUAL...
Page 108: Table 4-10 Slave Access Register Map
Set/Clear ICGS registers, which may only be accessed as privileged. The VIC slave-addressable registers occupy 256 bytes of Short I/O addressing space: all addresses within that space not assigned to a register are considered Reserved and should not be accessed. VMIVME-7586 PRODUCT MANUAL 4-57...
Page 109: System Register Details
The VMEbus, however, expects MotorolaÕs big-endian method for transferring a multiple-byte group to the same locations. The VMIVME-7586 has hardware on-board to support either transfer method, and the byte-swapping hardware is controlled by bits 5 and 6 of this register.
Page 110 See the discussion on byte swapping in Section 12 for more details. General Purpose Command Register: Slave A32/A24 Enable bits (D4, D0) Bits 4 and 0 control slave access to the VMIVME-7586. The default clear state disables all slave accesses to the VMIVME-7586.
Page 111 CHAPTER 4 - VMEbus FUNCTIONS 500-017586-000 General Purpose Command Register: Mailbox Enable bit (D3) Bit 3 controls slave access to the VMIVME-7586Õs mailbox registers within the VIC. The default clear state disables slave accesses to the mailbox registers. Mailbox Enable Bit Function...
Page 112: Product Id Register
500-017586-000 VMIVME-7586 REGISTERS as the VMIVME-7586 is conÞgured as the system controller. Likewise, if the VMIVME-7586 is not the system controller, it will still respond to a VMEbus SYSRESET* regardless of the VME Enable bit status. If VMEbus accesses are disabled, an attempted access will terminate normally, but no data will actually be written, and any data read will be indeterminate.
Page 113: Extended/Standard Address Register
VIC Base Register: LPT Mode bit (D1) This utility bit controls whether or not the VMIVME-7586Õs parallel port is bidirectional or output only. A clear LPT Mode bit (the default) makes the port bidirectional. A set bit forces the port into an output-only conÞguration.
Page 114: On-Board Video Status Register
Slave Address Mask/Compare Registers These four related write-only word registers are associated with slave mode access to the VMIVME-7586. See the discussion regarding these registers and slave mode on page 4-16. Programming these registers and then setting the Mailbox Enable bit in the General Purpose Command Register allows VMEbus resources to access the VIC Interprocessor Communication Registers.
Page 115: Size Register
PC/AT I/O port at I/O_$61. A set bit indicates a VIC-sourced NMI. If the bit is clear, the ISR should pass control back to the system NMI handler without reading the NMI ID Register. 4-64 VMIVME-7586 PRODUCT MANUAL...
Page 116: Vic Register Details
¥ The register and bit deÞnitions in this manual are customized for this controller; therefore, some more general functions described in the VIC manual either do not apply to the VMIVME-7586 or have slightly different applications. Such differences are pointed out in this manual wherever possible.
Page 117: Vmebus Interrupt Control Registers
$F8 upon powerup or hard reset. See Section 6 on page 4-32 for a detailed discussion of interrupt handling procedures. VMEbus Interrupt Control Registers VICR1–7 (VIC offset I/O $403–$41F) IRQ Mask Value Value Value 4-66 VMIVME-7586 PRODUCT MANUAL...
Page 118: Dma Status Interrupt Control Register
VMEbus Interrupt Control Registers: IPL Value bit ﬁeld (D2-D0) This interrupt level value is inverted and driven onto the IPL lines when an interrupt is acknowledged. The VMIVME-7586 supports PC/AT NMI interrupts on level 4, and IRQ11 and IRQ12 interrupts on IPL levels 2 and 1, respectively.
Page 119: Local Interrupt Control Registers
Do not enable the interrupt until the interrupt handling routines are in place. Also, note that LIRC5 is reserved by VMIC and should never be altered from the default setting. Local Interrupt Control Registers LICR1-7 (VIC offset I/O $427-$43F)
Page 120 Autovector mode required normal VMIVME-7586 operation. When clear, autovector mode is disabled; the interrupting source must provide the Status/ID vector to the processor. Autovector Bit Function The interrupting source provides the status/ID vector for the local interrupt acknowledge cycle to the processor (default) (not supported on the VMIVME-7586) Autovector mode.
Page 121: Icgs Interrupt Control Register
This value is inverted and driven onto the IPL signals when a global switch is acknowledged. ICMS Interrupt Control Register The ICMS Interrupt Control Register (ICMSICR) is a read/write byte register at VIC offset I/O address $447. This register provides enabling and 4-70 VMIVME-7586 PRODUCT MANUAL...
Page 122: Error Group Interrupt Control Register
IPL encoding for the error group interrupts. Error Group Interrupt Control Register EGICR (VIC offset I/O $44B) Write Arbitration ACFAIL SYSFAIL Post Fail Timeout SYSFAIL Interrupt Interrupt Interrupt Interrupt State Value Value Value Mask Mask Mask Mask VMIVME-7586 PRODUCT MANUAL 4-71...
Page 123 (default) Error Group Interrupt Control Register: Write Post Fail Interrupt Mask bit (D6) Write posting is not supported on the VMIVME-7586, therefore bit 6 should remain set. Error Group Interrupt Control Register: Arbitration Timeout Interrupt Mask bit (D5) When this bit is clear, the VIC generates a local interrupt when an arbitration timeout has occurred.
Page 124: Icgs Interrupt Vector Base Register
ICMS Interrupt Vector Base Register The ICMS Interrupt Vector Base Register (ICMSIVBR) is a read/write byte register at VIC offset I/O address $453. This register provides the status/ID vector for the module switch interrupts. The status/ID must be VMIVME-7586 PRODUCT MANUAL 4-73...
Page 125: Local Interrupt Vector Base Register
Bit 2 Bit 1 Bit 0 Number Number Number Local Interrupt Vector Base Register: Status/ID bit ﬁeld (D7-D3) These bits are user-deÞnable and are used with bits 2-0 to provide a unique local interrupt status/ID vector. 4-74 VMIVME-7586 PRODUCT MANUAL...
Page 126: Error Group Interrupt Vector Base Register
This read-only value indicates which group interrupt is pending during the interrupt acknowledge cycle. These bits are used with bits 7-3 to provide a unique status/ID vector for each error group interrupt. These bits are valid only during the interrupt acknowledge cycle. VMIVME-7586 PRODUCT MANUAL 4-75...
Page 127: Interprocessor Communications Registers
This bit provides enabling and disabling for the VMEbus Interrupt Switches. VMEbus Interrupt Vector Base Registers The VMEbus Interrupt Vector Base Registers (VIVBR) are read/write byte registers at VIC offset I/O addresses $487, $48B, $48F, $493, $497, $49B, 4-76 VMIVME-7586 PRODUCT MANUAL...
Page 128: Transfer Timeout Register
Transfer Timeout Register TTR (VIC offset I/O $4A3) VMEbus VMEbus VMEbus Local Bus Local Bus Local Bus Include Arbitration Timeout Timeout Timeout Timeout Timeout Timeout VMEbus Timeout Period Period Period Period Period Period Acquisition VMIVME-7586 PRODUCT MANUAL 4-77...
Page 129 4-7. VMEbus Timeout (µs) 64 (default) Inﬁnite (timer disabled) Transfer Timeout Register: Local Bus Timeout Period bit ﬁeld (D4-D2) DeÞnes the local bus timeout. Local Bus Timeout (µs) 32 (default) Inﬁnite (timer disabled) 4-78 VMIVME-7586 PRODUCT MANUAL...
Page 130 When clear, the local bus timer will stop and reset when the VMEbus is requested. Include VMEbus Acquisition Bit Function The local bus timer will stop and reset when the VMEbus is requested (default) The local bus timer will include waiting for VMEbus acquisition VMIVME-7586 PRODUCT MANUAL 4-79...
Page 131: Local Bus Timing Register
RMW cycles or BLT transfers on the VMIVME-7586. Minimum DS Deasserted Time Bit Function The minimum deasserted time for the DS* signal is 15.625 ns (default) The minimum deasserted time for the DS* signal is 31.250 ns 4-80 VMIVME-7586 PRODUCT MANUAL...
Page 132: Block Transfer Definition Register
VMEbus acknowledge timing. This value must be set to maximum (all bits set) when performing slave RMW cycles or BLT transfers on the VMIVME-7586. Block Transfer Deﬁnition Register The Block Transfer DeÞnition Register (BTDR) is a read/write byte register at VIC offset I/O address $4AB.
Page 133: Interface Configuration Register
When set, the VIC issues the address modiÞer code from the Address ModiÞer Source Register (AMSR) during block transfers. This bit must be set to enable BLT transfers on the VMIVME-7586. Block Transfer Deﬁnition Register: Dual Path Enable bit (D0) When set, dual path mode is enabled on the VIC during master block transfers.
Page 134 If bit 4 is enabled, bit 3 may be used to prevent the assertion of HALT* for RMC deadlocks. The default condition, using the DEDLK* signal alone, is recommended for the VMIVME-7586 and is the only condition possible for slave accesses.
Page 135: Arbiter/Requester Configuration Register
The VIC performs round-robin VMEbus arbitration (default) The VIC performs priority VMEbus arbitration Arbiter/Requester Conﬁguration Register: VMEbus Request Level bit ﬁeld (D6-D5) The VMEbus request level is set according to the following table: VMEbus Request Level BR3 (default) 4-84 VMIVME-7586 PRODUCT MANUAL...
Page 136: Address Modifier Source Register
The VIC performs no DRAM refresh functions (default) The VIC performs CAS-before-RAS (DS* before PAS*) refresh functions. This bit should never be set on the VMIVME-7586. Arbiter/Requester Conﬁguration Register: Fairness Timer Enable bit ﬁeld (D3-D0) The VMEbus fair requester is enabled in this bit Þeld according to the...
Page 137: Bus Error Status Register
VMEbus mastership, and timeout status. All bits except bit 7 are ßags that are automatically cleared on reset and must otherwise be cleared manually by the local processor after being set by status conditions. If these bits are 4-86 VMIVME-7586 PRODUCT MANUAL...
Page 138: Dma Status Register
(LBERR asserted to the VIC). Once set, this bit must be cleared manually. (Local bus Error errors will never occur in the current VMIVME-7586 conﬁguration.) This bit is set when a VMEbus bus error is signaled (BERR asserted). Once set, this...
Page 139 DMA Status Register: Master Write Post Info bit (D7) This bit is set whenever master write post information is stored. Since write posting is not supported on the VMIVME-7586, this bit should always be clear. DMA Status Register: VMEbus Bus Error bit (D4) This bit is set when a VMEbus bus error is signaled (BERR* asserted).
Page 140: Slave Select 0 Control Register 0
VIC offset I/O address $4C3. This register provides control of the slave selection 0 facilities of the VIC, which is dedicated to A32 access only on the VMIVME-7586. Enabling of the IRQ2 timer interrupt is also conÞgured in this register. This register is initialized to a value of $00 upon powerup or hard reset.
Page 141 DMA. The DSACKi* signals should be held asserted in this mode. This method must be used for block transfers on the VMIVME-7586. Reserved. When performing BLT transfers, bit 1 must always be set and bit 0 must be clear (for accelerated local bus transfers).
Page 142 Slave Select 0 Control Register 1 SS0CR1 (VIC offset I/O $4C7) Timing Timing Timing Timing Timing Timing Timing Timing Field 1 Field 1 Field 1 Field 1 Field 0 Field 0 Field 0 Field 0 VMIVME-7586 PRODUCT MANUAL 4-91...
Page 143: Slave Select 0 Control Register 1
Timing Delay 0 ns (default) 31.2500 ns 39.0625 ns 46.8750 ns 54.6875 ns 62.5000 ns 70.3125 ns 78.1250 ns 85.9375 ns 93.7500 ns 101.5625 ns 109.3750 ns 117.1875 ns 125.0000 ns 132.8125 ns 140.6250 ns 4-92 VMIVME-7586 PRODUCT MANUAL...
Page 144 Timing Delay 0 ns (default) 31.2500 ns 39.0625 ns 46.8750 ns 54.6875 ns 62.5000 ns 70.3125 ns 78.1250 ns 85.9375 ns 93.7500 ns 101.5625 ns 109.3750 ns 117.1875 ns 125.0000 ns 132.8125 ns 140.6250 ns VMIVME-7586 PRODUCT MANUAL 4-93...
Page 145: Slave Select 1 Control Register 0
1 facilities of the VIC, which is dedicated for A24 access on the VMIVME-7586. Master and slave write posting is enabled in this register as well. This register is initialized to a value of $00 upon powerup or hard reset.
Page 146 D32 slave operations are enabled for SLSEL1 Slave Select 1 Control Register 0: Address Space Conﬁguration bit ﬁeld (D3-D2) In the VMIVME-7586 implementation, SLSEL1 is dedicated to A24 slave access, therefore, the only value supported here is %01. The SLSEL1 address space is conÞgured according to the following table:...
Page 147 Slave Select 1 Control Register 1 SS1CR1 (VIC offset I/O $4CF) Timing Timing Timing Timing Timing Timing Timing Timing Field 1 Field 1 Field 1 Field 1 Field 0 Field 0 Field 0 Field 0 4-96 VMIVME-7586 PRODUCT MANUAL...
Page 148: Slave Select 1 Control Register 1
Timing Delay 0 ns (default) 31.2500 ns 39.0625 ns 46.8750 ns 54.6875 ns 62.5000 ns 70.3125 ns 78.1250 ns 85.9375 ns 93.7500 ns 101.5625 ns 109.3750 ns 117.1875 ns 125.0000 ns 132.8125 ns 140.6250 ns VMIVME-7586 PRODUCT MANUAL 4-97...
Page 149 Timing Delay 0 ns (default) 31.2500 ns 39.0625 ns 46.8750 ns 54.6875 ns 62.5000 ns 70.3125 ns 78.1250 ns 85.9375 ns 93.7500 ns 101.5625 ns 109.3750 ns 117.1875 ns 125.0000 ns 132.8125 ns 140.6250 ns 4-98 VMIVME-7586 PRODUCT MANUAL...
Page 150: Release Control Register
64 cycles per burst. All other values correspond directly to the burst count. For MBLT D64 block transfers (only available on controllers with the VIC64 option installed), the burst length is 4 times the actual Þeld contents, and a value of 0 implies 256 cycles (4 x 64). VMIVME-7586 PRODUCT MANUAL 4-99...
Page 151: Block Transfer Control Register
Period with DMA Block Transfer Control Register: Module-Based DMA bit (D7) Since the VMIVME-7586 does not support module-based DMA transfers, this bit must always remain clear. When this bit is set, module-based DMA transfers are enabled. Module-Based DMA Bit Function...
Page 152 Enables block transfers with local DMA (Bits D7 and D5 must be clear) Block Transfer Control Register: MOVEM Enable bit (D5) Since MOVEM transfer mode is not supported by the VMIVME-7586, this bit should always remain clear. When this bit is set, MOVEM transfers are enabled.
Page 153: Block Transfer Length Registers
8 bits (bits 23-16) on VIC64 chips only. BTLR1 contains the next most signiÞcant 8 bits of the length (bits 15-8), and BTLR0 the least (bits 7-0). The count must always be even; therefore, bit D0 of BTLR0 must always be clear. 4-102 VMIVME-7586 PRODUCT MANUAL...
Page 154: System Reset Register
Slave A16 Address Compare Register. See the Interprocessor Communications section on page 4-13 for more details concerning the conÞguration and use of the mailbox registers. Also, refer to Table 4-8 on page 4-53 for a complete slave register map. VMIVME-7586 PRODUCT MANUAL 4-103...
Page 155: Interprocessor Communications Switch Register
Interprocessor Communications Switch Register: ICMS Switches bit ﬁeld (D3-D0) Bits 0, 1, 2, and 3 correspond to ICMS 0, 1, 2, and 3, respectively. If the switch interrupts are enabled, a clear-to-set transition causes the associated interrupt. 4-104 VMIVME-7586 PRODUCT MANUAL...
Page 156: Interprocessor Communication Registers
This register provides local or remote reset and HALT*. Reset/Halt Status Register ICR6 (VIC offset I/O $47B) (VMEbus Slave Short I/O offset address $0D) IRESET/ Reset/ Reset/ IRESET HALT HALT HALT Status Status Status Status VMIVME-7586 PRODUCT MANUAL 4-105...
Page 157: Mailbox Semaphore Register
VIC offset I/O address $47F. Its VMEbus slave Short I/O offset address is $0F, responding to both privileged and nonprivileged accesses. This register provides semaphores to the Þve general-purpose interprocessor communication registers (ICR4-0). The remaining bits indicate VMEbus master status, generate HALT* and RESET*, and mask SYSRESET*. 4-106 VMIVME-7586 PRODUCT MANUAL...
Page 158 VMIVME-7586 asserts SYSFAIL* automatically after any reset. Since other controllers on the VMEbus may not function normally while the SYSFAIL* line is active, VMIC recommends that the SYSFAIL Mask bit be set immediately after powerup or reset initialization routines, even if no VMEbus activity is planned.
Page 159: Set/Clear Icgs Switch Registers (Slave-Only)
ICMS1, and so on (see Table 4-8 on page 4-53 for a complete slave register map). These registers are slave-only and not addressable in the local processorÕs I/O space (although they are available to the local processor through the VMEbus just as any VMEbus resource). The data written to 4-108 VMIVME-7586 PRODUCT MANUAL...
Page 160 ICMS0 switch. Set/Clear ICMS Switch Registers (Slave-Only) ICMS0-3 S/C (VMEbus Slave Short I/O offset address $20-$27) Any write access performs the associated set or clear function. VMIVME-7586 PRODUCT MANUAL 4-109...
Page 161: Chapter 5 - Maintenance
¥ No components of adjacent boards are disturbed when inserting or removing the board from the chassis ¥ Quality of cables and I/O connections If products must be returned, contact VMIC for a Return Material Authorization (RMA) Number. This RMA Number must be obtained prior to any return .
Page 162: Section 1 - Introduction
The VMIVME-7586 PC/AT Compatible VMEbus Controller has several connectors for its many I/O ports. Figure A-1 on page A-2 shows the locations of the connectors. Wherever possible, the VMIVME-7586 uses connectors and pinouts typical for any desktop PC. This ensures maximum compatibility with a minimum of confusion.
Page 163: Appendix A - Connector Pinouts
500-017586-000 COM1 Port RS-232 COM2 Port RS-232 Power and Status Indicators Reset Switch PC/104 Bus J3 PC/104 Bus J2 Parallel Port LPT1 PC/104 Expansion Site Monitor Port Ethernet Port Keyboard Port VMIVME-7586 Figure A-1 VMIVME-7586 Connector Locations VMIVME-7586 PRODUCT MANUAL...
Page 164: Section 2 - Ethernet Connector Pinout
On controller boards with an Ethernet option, a D15 female connector provides the Ethernet AUI interface. The pinout diagram for the Ethernet connector is shown in Figure A-2. ETHERNET CONNECTOR FUNCTION Reserved +12 VDC Reserved Figure A-2 Ethernet Connector Pinout VMIVME-7586 PRODUCT MANUAL...
Page 165: Section 3 - Floppy Drive Connector Pinout
Ground From Controller Write Enable Ground From Drive Track 0 Ground From Drive Write Protect Ground From Drive Read Data Ground From Controller Select Head 1 Ground From Drive Disk Change Figure A-3 Floppy Drive Connector Pinout VMIVME-7586 PRODUCT MANUAL...
Page 166: Section 4 - Ide Hard Drive Connector Pinout
Signal Ground Interrupt Request #14 16-bit Data Word Size Address Line #1 Diagnostic Test Passed Address Line #0 Address Line #2 Chip Select #0 Chip Select #1 Slave/Activity Status Signal Ground Figure A-4 IDE Hard Drive Connector Pinout VMIVME-7586 PRODUCT MANUAL...
Page 167: Section 5 - Keyboard Connector Pinout
The keyboard connector is a standard 6-pin female mini-DIN PS/2 style connector shown in Figure A-5; an adapter is supplied to connect a keyboard with a larger PC/AT-style connector to the VMIVME-7586. The PC/AT-style connector pinout is shown in Figure A-6.
Page 168: Section 6 - Pc/104 Connector Pinout
+12 V MEMR DRQ0 IOCHRDY (key) MEMW DACK5 SMEMW DRQ5 SA19 SMEMR DACK6 SA18 SD10 DRQ6 SA17 SD11 DACK7 SA16 DACK3 SD12 DRQ7 SA15 DRQ3 SD13 +5 V SA14 DACK1 SD14 MASTER SA13 DRQ1 SD15 SA12 REFRESH (key) VMIVME-7586 PRODUCT MANUAL...
Page 169 APPENDIX A - CONNECTOR PINOUTS 500-017586-000 Table A-1 PC/104 Connector Pinout (Continued) J1 ROW A J1 ROW B J2 ROW C J2 ROW D SA11 SYSCLK SA10 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2 BALE +5 V VMIVME-7586 PRODUCT MANUAL...
Page 170: Section 7 - Printer Connector Pinout
Out of Paper Device Selected Auto Feed Error Initialize Device Device Ready for Input Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Shield Chassis Ground Figure A-8 Printer Connector Pinout VMIVME-7586 PRODUCT MANUAL...
Page 171: Section 8 - Serial Connector Pinout
If the supplied RJ45-to-D9 adapter is being used, D9 pin 9 is not connected and D9 pin 1 is the DCD or RI signal from RJ45 pin 8. Figure A-9 Serial Connector Pinouts A-10 VMIVME-7586 PRODUCT MANUAL...
Page 172: Section 9 - Video Connector Pinout
The video port uses a standard high-density D15 VGA connector. Figure A-10 shows the pinout. VIDEO CONNECTOR DIRECTION FUNCTION Green Blue Reserved Ground Ground Ground Ground Reserved Ground Reserved Reserved Horizontal Sync Vertical Sync Reserved Shield Chassis Ground Figure A-10 Video Connector Pinout VMIVME-7586 PRODUCT MANUAL A-11...
Page 173: Section 10 - Vmebus Connector Pinout
P1 ROW B P1 ROW C P2 ROW B NUMBER SIGNAL SIGNAL SIGNAL SIGNAL BBSY +5 V BCLR ACFAIL Reserved BG0IN BG0OUT BG1IN BG1OUT BG2IN BG2OUT SYSCLK BG3IN SYSFAIL BG3OUT BERR SYSRESET LWORD +5 V WRITE DTACK A-12 VMIVME-7586 PRODUCT MANUAL...
Page 174 P1 ROW C P2 ROW B NUMBER SIGNAL SIGNAL SIGNAL SIGNAL IACK IACKIN SERCLK IACKOUT SERDAT IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 -12 V +5 V STDBY +12 V +5 V +5 V +5 V +5 V VMIVME-7586 PRODUCT MANUAL A-13...
Page 175: Appendix B - Ethernet Option
Figure B-1 on page B-2 shows the factory-installed Ethernet Mezzanine on the VMIVME-7586 controller board. Note that the Ethernet Mezzanine AUI connector on the front panel of a VMIVME-7586 is not functional unless the Ethernet Mezzanine is installed. VMIVME-7586 PRODUCT MANUAL...
Page 176: Section 2 - Ethernet Software Compatibility
Location of the Ethernet Mezzanine SECTION 2 - ETHERNET SOFTWARE COMPATIBILITY The Ethernet Mezzanine is based on National SemiconductorÕs DP83905 AT/LANTIC VLSI chip. This device is software compatible with NovellÕs NE2000 standard. Any software that can be conÞgured to support an VMIVME-7586 PRODUCT MANUAL...
Page 177: Section 3 - Ethernet Driver Software
500-017586-000 ETHERNET DRIVER SOFTWARE NE2000-compatible card should execute correctly on the VMIVME-7586 with the Ethernet Mezzanine installed. SECTION 3 - ETHERNET DRIVER SOFTWARE Customers must supply their own driver software for use with the Ethernet Mezzanine. The Ethernet Mezzanine supports the following popular driver software: ¥...
Page 178 Mezzanine. 3. Press as required to select an I/O port address of 0x320. <F1> Then press <Enter> 4. Highlight Exit (using the down arrow key) and press <Enter> 5. Press the key to begin diagnostic tests. <F5> VMIVME-7586 PRODUCT MANUAL...
Page 179: Section 5 - Technical Details
Atlantic IC its operating parameters at powerup. These parameters include the memory location of the Boot EPROM. Valid selections for the memory occupied by the Boot EPROM on the VMIVME-7586 are listed in Table B-1 on page B-6. VMIVME-7586 PRODUCT MANUAL...
Page 180: Table B-1 Boot Eprom Address Selection
32 Kbyte from $C8000 to $CFFFF D000 DO NOT SELECT !!! (Conﬂicts with VMEbus Window) D800 DO NOT SELECT !!! (Conﬂicts with VMEbus Window) DO NOT SELECT A BOOT EPROM ADDRESS CONFLICTING WITH THE VGA AREA. This produces a nonrecoverable FATAL error. VMIVME-7586 PRODUCT MANUAL...
Page 181: Appendix C - Flash Memory Option
The VMIVME-7586 PC/AT Compatible VMEbus Controller can be ordered with the 2 Mbyte Flash Memory Mezzanine option. The Flash Memory Mezzanine allows the user to conÞgure the VMIVME-7586 as a diskless VMEbus master running software stored in the ßash memory.
Page 182: Section 2 - Preparing The Flash Memory
RS-232 COM2 Port RS-232 Power and Status Indicators Reset Switch PC/104 Bus J3 PC/104 Bus J2 Parallel Port LPT1 PC/104 Expansion Site Monitor Port Ethernet Port Snap-In Spacers Keyboard Port VMIVME-7586 Figure C-1 Flash Mezzanine Jumper Location VMIVME-7586 PRODUCT MANUAL...
Page 183: Section 3 - Copying Files To Flash Memory
1.44 Mbyte ßoppy diskette. Note: the ßash will be seen as a 1.44 Mbyte drive A. 4. Remove the bootable ßoppy diskette. 5. The VMIVME-7586 with 2 Mbyte Flash Memory option is shipped with a 3.5 inch diskette containing the programming utility PFLASH.EXE Insert the VMIC diskette in the ßoppy drive and execute...
Page 184: Section 4 - Using Flash Memory As Boot Device
. Also, ensure the system boot sequence searches drive before drive 5. If the VMIVME-7586 is to be conÞgured as a diskless VMEbus CPU without a keyboard, select keyboard ÒNot InstalledÓ under the boot options. 6. Save the new conÞguration to CMOS and reboot the VMIVME-7586.
Page 185 Upper Address Register (Write-Only word at I/O $302) D15 D14 D13 D12 D11 D10 D9 A20 A19 A18 A17 4 Most Signiﬁcant Address Bits Flash Data Register (Read-Only word at I/O $304) D15 D14 D13 D12 D11 D10 D9 16-bit Flash Data VMIVME-7586 PRODUCT MANUAL...
Page 186: Section 7 - Programming
1994 Flash Memory: Volume I Intel Corporation Intel Literature Sales Department P.O. Box 7641 Mt. Prospect, IL 60056-7641 1994/1995 Flash Memory Products Data Book Advanced Micro Devices 901 Thompson Place P.O. Box 3453 Sunnyvale, CA 94088-3453 VMIVME-7586 PRODUCT MANUAL...
Page 187: Appendix D - Basic Input / Output System
SECTION 2 - STANDARD FEATURES The PhoenixBIOS setup program contains standard system conÞguration settings necessary for board operation. Standard BIOS features are listed below: • Ultra-fast memory testing • Speed independence (8254 PIT) • Power-On Self Tests (POST) VMIVME-7586 PRODUCT MANUAL...
Page 188: Section 3 - Quick Setup
Menu Items section later in this chapter. 1. Powerup or reboot the system. The PhoenixBIOS displays the message: Press <F2> to enter SETUP... 2. Press and the menu appears (see Figure D-1 on page D-3 ). <F2> Main VMIVME-7586 PRODUCT MANUAL...
Page 189 <Shift + Tab> <-/+> 5. To use the autodetect settings for the primary hard disk, select the sub-menu and press . The Adapter 0 Master <Enter> IDE Adapter 0 Master sub-menu displays. VMIVME-7586 PRODUCT MANUAL...
Page 190 Main 13. From the menu, conÞgure the ßoppy drive type(s). The type of Main drive must be properly entered or boot errors will occur. 14. To save your selections, move to the menu and press Exit <Enter> VMIVME-7586 PRODUCT MANUAL...
Page 191: Section 4 - Program Description
Save Changes & Exit 16. The VMIVME-7586 automatically reboots with the new values in effect. If any error messages are displayed, refer to the Status and Error Messages section later in this chapter for a description of the problem.
Page 192: User Interface
<-/+> 4. Arrows indicate sub-menus. Move to the sub-menu and press <Enter> access advanced settings. 5. The Help Window provides a brief description of each selected menu item. VMIVME-7586 PRODUCT MANUAL...
Page 193: Control Key Summary
3. To change values, use the keys and press when done. <+/-> <Enter> NOTE: THE DEFAULT VALUE FOR <F9> AND <F10> IS ALWAYS “N”. TO EXECUTE THESE ITEMS, PRESS <E > TO CONTINUE. NTER VMIVME-7586 PRODUCT MANUAL...
Page 194: Section 5 - Program Menus And Menu Items
. To exit sub-menus, press <Enter> <Esc> items are described below along with the available values. Main Menu Sub-menus are described in the following sections. NOTE: FACTORY DEFAULT SETTINGS FOR MENU ITEMS ARE DENOTED BY AN ASTERISK (*). VMIVME-7586 PRODUCT MANUAL...
Page 195: System Time
Reports the systemÕs available base and extended memory. This is not a user-conÞgurable item. The PhoenixBIOS automatically senses and reports system memory. Memory is reported in 64 Kbyte increments. The BIOS reports up to 640 Kbyte in the Þeld and 65,472 Kbyte in the Base Memory VMIVME-7586 PRODUCT MANUAL...
Page 196: Ide Adapter 0 Master/Ide Adapter 0 Slave Sub-Menus
Autotype Fixed Disk Automatically determines parameters, Type, Cylinders, Heads, , for the existing hard drive. The BIOS Sectors/Track Write Precomp displays the determined parameters and requests user conÞrmation. If conÞrmed, the drive parameters are saved as listed. D-10 VMIVME-7586 PRODUCT MANUAL...
Page 197: Type
Each Þxed-disk drive 1 to 39 supports 39 predeÞned drive types. Table D-2 on page D-12 lists these predeÞned types and their default values. When you select a drive type, the remaining parameters are automatically set. VMIVME-7586 PRODUCT MANUAL D-11...
Page 198: Table D-2 Phoenixbios Fixed Disk Table
APPENDIX D - BASIC INPUT / OUTPUT SYSTEM 500-017586-000 Table D-2 PhoenixBIOS Fixed Disk Table Type Cylinders Head Sectors Wrt Pre Should always be set to None. Reserved 1024 D-12 VMIVME-7586 PRODUCT MANUAL...
Page 199: Cylinders
Sectors/Track Sets the number of sectors per track: 1 to 64 Write Precomp Sets the number of the cylinder at which to change the write timing: 1-2048 should always be selected for IDE hard disks. None VMIVME-7586 PRODUCT MANUAL D-13...
Page 200: Memory Cache Sub-Menu
This menu item appears only on controllers with an external cache option. Figure D-5 PhoenixBIOS Memory Cache Sub-menu The items contained in this sub-menu are described along with their available options. NOTE: THE FACTORY DEFAULT SETTINGS FOR MENU ITEMS ARE DENOTED BY AN ASTERISK (*). D-14 VMIVME-7586 PRODUCT MANUAL...
Page 201: Internal Cache
SpeciÞes the following areas of regular and extended memory as noncacheable regions: Region 0, start: DeÞnes the start of noncacheable Region 0 multiples of 64 Kbyte. The start point is the offset from the beginning of memory. The factory default is 896 Kbyte. VMIVME-7586 PRODUCT MANUAL D-15...
Page 202: Memory Shadow Sub-Menu
To access the sub-menu: Memory Shadow From the , select and press Main Menu Memory Shadow <Enter> sub-menu appears (Figure D-6 on Memory Shadow page D-17). D-16 VMIVME-7586 PRODUCT MANUAL...
Page 203: System Shadow
The items contained in this sub-menu are described below along with their available options. NOTE: THE FACTORY DEFAULT SETTINGS FOR MENU ITEMS ARE DENOTED BY AN ASTERISK (*). System Shadow Permanently enabled. Video Shadow Shadows video BIOS. *Enabled Disabled Shadow Memory Regions DeÞnes the ROM shadow regions: VMIVME-7586 PRODUCT MANUAL D-17...
Page 204: C800 - Cfff
APPENDIX D - BASIC INPUT / OUTPUT SYSTEM 500-017586-000 C800 - CFFF Enabled *Disabled D000 - DFFF Enabled *Disabled E000 - EFFF DeÞnes the VMEbus access, which should not be shadowed. This setting should always be disabled. Enabled *Disabled D-18 VMIVME-7586 PRODUCT MANUAL...
Page 205: Boot Options Sub-Menu
The following section provides descriptions of menu items and their corresponding options. NOTE: THE DEFAULT SETTINGS FOR MENU ITEMS ARE DENOTED BY AN ASTERISK (*). Keyboard Enables the system to boot without an installed keyboard. *Installed - system boots with a keyboard installed. VMIVME-7586 PRODUCT MANUAL D-19...
Page 206: Boot Sequence
For help in resolving POST problems, all PhoenixBIOS error and status messages are contained in the List of Messages section later in this chapter. Floppy Check Seeks diskette drives during bootup. Disabling speeds boot time and increases the longevity of the diskette drives. *Enabled Disabled D-20 VMIVME-7586 PRODUCT MANUAL...
Page 207: Summary Screen
Figure D-8 PhoenixBIOS Example Summary Screen KEYBOARD FEATURES sub-menu contains menu items that enable you to set Keyboard Features keyboard functionality. From the , select and press Main Menu Numlock <Enter> sub-menu appears (Figure D-9). Keyboard Features VMIVME-7586 PRODUCT MANUAL D-21...
Page 208: Keyboard Features
<NumLock> *off - causes the numeric keypad arrow keys to serve as cursor movement keys. turns on if it Þnds a numeric key Auto <NumLock> pad. Key click Controls audible key click. *Enabled Disabled D-22 VMIVME-7586 PRODUCT MANUAL...
Page 209: Keyboard Autorepeat Rate
Load Pre vious V alues Save Changes F1 Help -/+ Change Values Select Item F9 Setup Def a ults ESC Exit Enter Select Sub-Menu Select Menu F10 Pre vious V alues Figure D-10 PhoenixBIOS Exit Menu VMIVME-7586 PRODUCT MANUAL D-23...
Page 210: Save Changes & Exit
Resets all menu items to values previously set in CMOS. Select this item and press to reload the menu items. Select at the <Enter> conÞrmation prompt to continue; to return to the without Exit Menu retrieving previous values. D-24 VMIVME-7586 PRODUCT MANUAL...
Page 211: Save Changes
Select this item and press Press at the conÞrmation prompt to save <Enter>. selections and return to the to return to the without Main Menu Exit Menu saving. VMIVME-7586 PRODUCT MANUAL D-25...
Page 212: Section 7 - Status And Error Messages
Incorrect Drive B type in the setup program. - run SETUP There is a problem with NVRAM (CMOS) Invalid NVRAM media access. type The keyboard controller failed testing. Keyboard controller Check the keyboard and keyboard error controller. D-26 VMIVME-7586 PRODUCT MANUAL...
Page 213 Run the setup program and verify that the wait-state conﬁguration is correct. This error is cleared the next time the system is booted. The real-time clock fails the BIOS test. It Real time clock error may require board repair. VMIVME-7586 PRODUCT MANUAL D-27...
Page 214 UMB upper limit segment limit of Upper Memory Blocks, indicating address: nnnn released segments of the BIOS which may be reclaimed by a virtual memory manager. The video BIOS successfully copied to Video BIOS shadowed shadow RAM. D-28 VMIVME-7586 PRODUCT MANUAL...

VMIC VMIVME-7586 Product Manual

Chapter 1 - Introduction

Chapter 2 - Installation and Setup

Chapter 3 - Pc/At Functions

CHAPTER 4 - Vmebus FUNCTIONS

Chapter 5 - Maintenance

Appendix A - Connector Pinouts

Appendix B - Ethernet Option

Appendix C - Flash Memory Option

Appendix D - Basic Input / Output System

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Summary of Contents for VMIC VMIVME-7586