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Aries Embedded MSMP1 Hardware Manual

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MSMP1 Hardware Manual
MSMP1 Hardware Manual
Version:
2.2
Created on:
May 19, 2022
Created by:
Diana Korchmar, Angeline Wamai, Andreas Widder
© ARIES Embedded GmbH. The information contained in this document is strictly confiden-
tial. This document may not be copied, reproduced, translated, changed or distributed
without the written approval of ARIES Embedded GmbH
Page 1 of 42

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Summary of Contents for Aries Embedded MSMP1

  • Page 1 Created by: Diana Korchmar, Angeline Wamai, Andreas Widder © ARIES Embedded GmbH. The information contained in this document is strictly confiden- tial. This document may not be copied, reproduced, translated, changed or distributed without the written approval of ARIES Embedded GmbH...
  • Page 2 2 Overview 2.1 MSMP1 Microprocessor SiP ........
  • Page 3 ..........4.2.17 MSMP1 SiP Pads .
  • Page 4 ARIES Embedded. ARIES Embedded explicitly reserves the rights to change or add to the contents of this Preliminary User’s Manual or parts of it without notification.
  • Page 5 1.3 Copyright This document may not be copied, reproduced, translated, changed or distributed, completely or partially in any form without the written approval of ARIES Embedded GmbH. 1.4 Registered Trademarks The contents of this document may be subject of intellectual property rights (including but not limited to copyright, trademark, or patent rights).
  • Page 6 MSMP1 fits to an OSM size M SoM in a size of only 30x45mm. Due to its 476 contacts the SoM offer the CPU almost transparently so that it can be used almost without functional restrictions due to the pin-multiplexing of the CPU.
  • Page 7 MSMP1 Hardware Manual 2.2 Feature Set • STM32MP1 (STMicroelectronics) – Single/Dual Cortex-A7, up to 800MHz – Cortex-M4, up to 209MHz • 512MB – 1GB DDR3L RAM • 4GB – 64GB eMMC NAND Flash • 10/100/1000MBit Ethernet • USB2.0 Host/OTG • 2x CAN •...
  • Page 8 MSMP1 Hardware Manual 2.3 Order Codes The MSMP1 SoM is available in the following standard configurations: • MSMP151-A0C – STM32MP151 – 512MB LPDDR3 RAM – no eMMC – 512MBit SPI NOR – -25. . . +85°C • MSMP157-BAA – STM32MP157 –...
  • Page 9 MSMP1 Hardware Manual 2.4 Block Diagram Chapter 2. Overview Page 9 of 42...
  • Page 10 MSMP1 Hardware Manual 2.5 Dimensions Chapter 2. Overview Page 10 of 42...
  • Page 11 MSMP1 Hardware Manual 2.6 Part Overview Assembly Top Assembly Bottom Chapter 2. Overview Page 11 of 42...
  • Page 12 MSMP1 Hardware Manual 2.7 Handling Recommendations To avoid mechanical damage to the components populated on MSMP1 it is strongly recommended not to apply mechanical force on the Ball Grid Array (BGA) components. The BGA components are marked as shaded in the figure below: Chapter 2.
  • Page 13 MSMP1 Hardware Manual CHAPTER THREE OPEN STANDARD MODUL (OSM) The idea of all Open Standard Modules™ is to create a new, future proof and versatile standard for small- size, low-cost embedded computer modules, combining the following key characteristics: • Completely machine processible during soldering, assembly and testing •...
  • Page 14 MSMP1 Hardware Manual 3.1 Module Sizes and Dimensions OSM SoMs are highly scalable in size, performance and functionality as they are available in different mechanical sizes and contact count: Size Metrics Contact Count Colour Outline Size-0 – “Zero” 30 mm x 15 mm 188 contacts Size-S –...
  • Page 15 MSMP1 Hardware Manual 3.2 Contact Characteristics: OSM SoMs are available with different contact characteristics: 3.2.1 ENIG-LGA All OSM-SoMs by ARIES Embedded are using ENIG-LGA contacts on its PCBs: 3.2.2 Fused Tin Grid Array 3.2.3 BGA Chapter 3. Open Standard Modul (OSM)
  • Page 16 MSMP1 Hardware Manual 3.3 Contact Grid The Contact Grid for the Open Standard Module™ Specification is symmetrically and defines the following dimensions: • Contact Diameter: 0.8 mm • Contact Grid: 1.25 mm • Contact-to-Contact: 0.45 mm • Contact-to-Edge: 0.85 mm Chapter 3.
  • Page 17 MSMP1 Hardware Manual 3.4 Recommendations for Processing OSM System on Modules In the following the MSRZFive-AAA SoM will be used as a reference. MSRZFive is available as a LGA332 package with round flat pads on the solder side of the SoM: Chapter 3.
  • Page 18 MSMP1 Hardware Manual 3.4.1 Design 3.4.1.1 Layout PCB The connecting pad size of the baseboard layout should be similar to the layout of e.g. the FIVEberry baseboard. The pad size is defined with 0.8mm, the pitch 1.25mm. 3.4.1.2 Stencil The stencil should have a with of 120µm. The openings in the stencil should be round shape with a diameter of 0.8mm, accordingly.
  • Page 19 MSMP1 Hardware Manual 3.4.2.2 Production For mounting the OSM SoMs the SoMs will be offered to the SMT machine in a tray or a reel. For the pickup of the SoM, using a vacuum nozzle, the SoM should be picked up by using a mechanical point as much as possible in the middle of the SoM, e.g.
  • Page 20 MSMP1 Hardware Manual 3.5 OSM Design Guide The primary purpose of OSM Design Guide is to serve as a suggestion for developers of OSM Carrier Boards and for OSM Module customers who wish to have a OSM based system developed. The document should also be valuable to FAEs and Product managers to help them understand the OSM Module infrastructure.
  • Page 21 MSMP1 Hardware Manual CHAPTER FOUR RESOURCES 4.1 Components 4.1.1 MPU STM32MP157 microprocessors are based on the flexible architecture of a Dual Arm® Cortex®-A7 core running up to 800 MHz and Cortex®-M4 at 209 MHz combined with a dedicated 3D graphics processing unit (GPU) and MIPI-DSI display interface and a CAN FD interface.
  • Page 22 STMicroelectronics. 4.1.2 LPDDR3 SDRAM The MSMP1 is equipped with 1 block of NANYA NT6CL128M32DM-H1 or NT6CL256M32AM LPDDR3 SDRAM resulting in up to 4/8 GB of 32bit memory. Device is available in the commercial temperature range -30°C. . . +105°C. The memory interface operates with 1866Mbps speed rate. The memory interface is clocked at 933MHz using the 1.2V/1.8V SDRAM standard interface.
  • Page 23 RES# 4.1.4 eMMC Flash The MSMP1 supports one eMMC NAND Flash in the range of 4-64 GByte. The eMMC provides a high-speed memory card interface compliant with JEDEC Version 5.0, eliminating the need for users to be concerned about directly controlling Flash Memories.
  • Page 24 I C and IO interface. MSMP1 is operational for supply voltages in the range of 2.8V to 5.5V. MSMP1 is available, depending on the installed PMIC, in a version to support either 1.8V IO-voltage or 3.3V IO-voltage. PMIC Derivatives...
  • Page 25 PA14 3V3, 680R to PA14 red PA13 3V3, 680R to PA13 green 4.2 Interfaces 4.2.1 I2C When using MSMP1 in conformity to the OSM standard two I2C interfaces are available: MPU Pin Function SiP Pads Remarks I2C2_SCL AA15 2k2 pullup to VCC...
  • Page 26 MSMP1 Hardware Manual 4.2.3 SPI When using MSMP1 in conformity to the OSM standard three SPI interface are available: MPU Pin Function SiP Pads SPI1_SCK SPI1_MISO SPI1_MOSI SPI1_NSS SPI3_SCK SPI3_MISO SPI3_MOSI SPI3_NSS SPI4_SCK SPI4_MISO SPI4_MOSI SPI4_NSS AA23 4.2.4 JTAG MPU Pin...
  • Page 27 MSMP1 Hardware Manual 4.2.5.2 UART-Console MPU Pin Function SiP Pads UART4_RX UART4_TX 4.2.5.3 USART MPU Pin Function SiP Pads USART2_RX (GPIO) USART2_TX (GPIO) USART2_RTS (FMC_NOE) USART2_CTS (TIM1_BKIN) USART2_CK (GPIO) 4.2.6 TIMER/PWM MPU Pin Function SiP Pads PA8 (TIM1_CH1) PA9 (TIM1_CH2)
  • Page 28 MSMP1 Hardware Manual 4.2.7 Ethernet MPU Pin Function SiP Pads ETH_RGMII_CLK125 ETH_RGMII_GTX_CLK ETH_RGMII_TX_CTL ETH_RGMII_TXD0 ETH_RGMII_TXD1 ETH_RGMII_TXD2 ETH_RGMII_TXD3 ETH_RGMII_RX_CLK ETH_RGMII_RX_CTL ETH_RGMII_RXD0 ETH_RGMII_RXD1 ETH_RGMII_RXD2 ETH_RGMII_RXD3 ETH_GMII_RX_ER ETH_GMII_CRS ETH_GMII_COL ETH_MDC ETH_MDIO ETH_MDINT ETH_PHYINT 4.2.8 FDCAN MPU Pin Function SiP Pads FDCAN1_TX AC17 FDCAN1_RX...
  • Page 29 MSMP1 Hardware Manual 4.2.9 COM/FMC MPU Pin Function SiP Pads PD14 (GPIO/FMC_AD0) PD15 (GPIO/FMC_AD1) (GPIO/FMC_AD2/I2C5_SDA) (GPIO/FMC_AD3/I2C5_SCL) (GPIO/FMC_AD4/QSPI_BK2_IO0) (GPIO/FMC_AD5/QSPI_BK2_IO1) (GPIO/FMC_AD6/QSPI_BK2_IO2) PE10 (GPIO/FMC_AD7/QSPI_BK2_IO3) PD11 (GPIO/FMC_CLE) PD12 (GPIO/FMC_ALE) (GPIO/FMC_NWAIT) PD5 (GPIO/FMC_NWE) PG9 (GPIO/FMC_NCE) PC13 (RTC_OUT1) 4.2.10 USB1 Interface (OTG) MPU Pin Function SiP Pads...
  • Page 30 MSMP1 Hardware Manual 4.2.12 DISPLAY-RGB MPU Pin Function SiP Pads LCD_R0 LCD_R1 AA29 LCD_R2 LCD_R3 LCD_R4 LCD_R5 LCD_R6 LCD_R7 LCD_G0 LCD_G1 AA30 LCD_G2 LCD_G3 LCD_G4 LCD_G5 LCD_G6 LCD_G7 LCD_B0 LCD_B1 AA31 LCD_B2 LCD_B3 LCD_B4 LCD_B5 LCD_B6 LCD_B7 LCD_CLK LCD_VSYNC LCD_HSYNC...
  • Page 31 MSMP1 Hardware Manual 4.2.14 SDCARD MPU Pin Function SiP Pads SDMMC1_CK SDMMC1_CMD SDMMC1_D0 SDMMC1_D1 SDMMC1_D2 SDMMC1_D3 SD_CardDetect PB6/SD_PWR_EN PB10/SD_WP 4.2.15 GPIO MPU Pin Function SiP Pads PA8 (GPIO/TIM1_CH1) PA9 (GPIO/TIM1_CH2) PE13 (GPIO/TIM1_CH3) PA11 (GPIO/TIM1_CH4) PH10 (GPIO/TIM5_CH1) PH11 (GPIO/TIM5_CH2) PA12 (GPIO/TIM1_ETR)
  • Page 32 MSMP1 Hardware Manual Table 2 – continued from previous page MPU Pin Function SiP Pads PH15 (GPIO/TIM8_CH3N) PI4 (GPIO/TIM8_BKIN) PI5 (GPIO/TIM8_CH1) PI6 (GPIO/TIM8_CH2) PI7 (GPIO/TIM8_CH3) PI9 (GPIO) PI11 (GPIO) (GPIO/TIM1_CH3N) (GPIO/UART8_RTS) PG10 (GPIO/UART8_CTS) 4.2.16 ADC MPU Pin Function SiP Pads...
  • Page 33 MSMP1 Hardware Manual 4.2.17 MSMP1 SiP Pads 4.2.17.1 Contact Groups 4.2.17.2 Contact Grid Numbering Chapter 4. Resources Page 33 of 42...
  • Page 34 MSMP1 Hardware Manual 4.2.17.3 Contact Table MPU Pin Function SiP Pads MPU Pin Function SiP Pads ETHERNET ETH_RGMII_GTX_CLK ETH_RGMII_TXD0 ETH_RGMII_TXD1 ETH_RGMII_TXD2 ETH_RGMII_TXD2 ETH_RGMII_TXD3 ETH_RGMII_TX_CTL ETH_RGMII_RX_CLK ETH_RGMII_RXDO ETH_RGMII_RXD1 ETH_RGMII_RXD2 ETH_RGMII_RXD3 ETH_RGMII_RXD3 ETH_GMII_RX_ER ETH_RGMII_RX_CTL ETH_GMII_CRS ERH_GMII_COL ETH_RGMII_CLK125 ETH_MDC ETH_MDIO – – –...
  • Page 35 MSMP1 Hardware Manual Table 3 – continued from previous page MPU Pin Function SiP Pads MPU Pin Function SiP Pads SDIO FDCAN1_TX AC17 FDCAN1_RX AB17 FDCAN2_TX AC19 FDCAN2_RX AB19 AA15 USB1_D_P AC14 AB15 USB1_D_N AB13 – – AC16 – –...
  • Page 36 MSMP1 Hardware Manual Table 3 – continued from previous page MPU Pin Function SiP Pads MPU Pin Function SiP Pads PC0 (GPIO) PC3 (GPIO) PC7 (GPIO) PD8 (GPIO) PD9 (GPIO) (GPIO/TIM1_BKIN2) PF2 (GPIO) PF3 (GPIO) PF10 (GPIO/QSPI_CLK) PF15 (GPIO) PG2 (GPIO)
  • Page 37 MSMP1 Hardware Manual Table 3 – continued from previous page MPU Pin Function SiP Pads MPU Pin Function SiP Pads LCD_G6 LCD_G7 LCD_B2 LCD_B3 LCD_B4 LCD_B5 LCD_B6 LCD_B7 LCD_CLK LCD_VSYNC LCD_HSYNC LCD_BL_CTRL LCD_DE NRST PI11 (GPIO) – – – MIPI DSI...
  • Page 38 MSMP1 Hardware Manual Table 3 – continued from previous page MPU Pin Function SiP Pads MPU Pin Function SiP Pads – eDP_B_BL_EN – eDP_B_BL_PWM – UFS_TX0_N AC29 – UFS_TX0_P AC28 – UFS_RX0_N AC32 – UFS_RX0_P AC31 – UFS_TX1_N AB30 –...
  • Page 39 – RESERVED – RESERVED AB25 – RESERVED AB26 – – – 4.3 Schematics Schematics for the MSMP1 SiP may be obtained on request. Please contact sales@aries-embedded.de. Below the OSM schematics footprint is shown: Chapter 4. Resources Page 39 of 42...
  • Page 40 MSMP1 Hardware Manual Chapter 4. Resources Page 40 of 42...
  • Page 41 MSMP1 Hardware Manual Chapter 4. Resources Page 41 of 42...
  • Page 42 MSMP1 Hardware Manual Chapter 4. Resources Page 42 of 42...