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ARIES Embedded. ARIES Embedded explicitly reserves the rights to change or add to the contents of this Preliminary User’s Manual or parts of it without notification.
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1.3 Copyright This document may not be copied, reproduced, translated, changed or distributed, completely or partially in any form without the written approval of ARIES Embedded GmbH. 1.4 Registered Trademarks The contents of this document may be subject of intellectual property rights (including but not limited to copyright, trademark, or patent rights).
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MSMP1 fits to an OSM size M SoM in a size of only 30x45mm. Due to its 476 contacts the SoM offer the CPU almost transparently so that it can be used almost without functional restrictions due to the pin-multiplexing of the CPU.
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MSMP1 Hardware Manual 2.2 Feature Set • STM32MP1 (STMicroelectronics) – Single/Dual Cortex-A7, up to 800MHz – Cortex-M4, up to 209MHz • 512MB – 1GB DDR3L RAM • 4GB – 64GB eMMC NAND Flash • 10/100/1000MBit Ethernet • USB2.0 Host/OTG • 2x CAN •...
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MSMP1 Hardware Manual 2.3 Order Codes The MSMP1 SoM is available in the following standard configurations: • MSMP151-A0C – STM32MP151 – 512MB LPDDR3 RAM – no eMMC – 512MBit SPI NOR – -25. . . +85°C • MSMP157-BAA – STM32MP157 –...
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MSMP1 Hardware Manual 2.6 Part Overview Assembly Top Assembly Bottom Chapter 2. Overview Page 11 of 42...
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MSMP1 Hardware Manual 2.7 Handling Recommendations To avoid mechanical damage to the components populated on MSMP1 it is strongly recommended not to apply mechanical force on the Ball Grid Array (BGA) components. The BGA components are marked as shaded in the figure below: Chapter 2.
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MSMP1 Hardware Manual CHAPTER THREE OPEN STANDARD MODUL (OSM) The idea of all Open Standard Modules™ is to create a new, future proof and versatile standard for small- size, low-cost embedded computer modules, combining the following key characteristics: • Completely machine processible during soldering, assembly and testing •...
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MSMP1 Hardware Manual 3.1 Module Sizes and Dimensions OSM SoMs are highly scalable in size, performance and functionality as they are available in different mechanical sizes and contact count: Size Metrics Contact Count Colour Outline Size-0 – “Zero” 30 mm x 15 mm 188 contacts Size-S –...
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MSMP1 Hardware Manual 3.2 Contact Characteristics: OSM SoMs are available with different contact characteristics: 3.2.1 ENIG-LGA All OSM-SoMs by ARIES Embedded are using ENIG-LGA contacts on its PCBs: 3.2.2 Fused Tin Grid Array 3.2.3 BGA Chapter 3. Open Standard Modul (OSM)
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MSMP1 Hardware Manual 3.3 Contact Grid The Contact Grid for the Open Standard Module™ Specification is symmetrically and defines the following dimensions: • Contact Diameter: 0.8 mm • Contact Grid: 1.25 mm • Contact-to-Contact: 0.45 mm • Contact-to-Edge: 0.85 mm Chapter 3.
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MSMP1 Hardware Manual 3.4 Recommendations for Processing OSM System on Modules In the following the MSRZFive-AAA SoM will be used as a reference. MSRZFive is available as a LGA332 package with round flat pads on the solder side of the SoM: Chapter 3.
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MSMP1 Hardware Manual 3.4.1 Design 3.4.1.1 Layout PCB The connecting pad size of the baseboard layout should be similar to the layout of e.g. the FIVEberry baseboard. The pad size is defined with 0.8mm, the pitch 1.25mm. 3.4.1.2 Stencil The stencil should have a with of 120µm. The openings in the stencil should be round shape with a diameter of 0.8mm, accordingly.
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MSMP1 Hardware Manual 3.4.2.2 Production For mounting the OSM SoMs the SoMs will be offered to the SMT machine in a tray or a reel. For the pickup of the SoM, using a vacuum nozzle, the SoM should be picked up by using a mechanical point as much as possible in the middle of the SoM, e.g.
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MSMP1 Hardware Manual 3.5 OSM Design Guide The primary purpose of OSM Design Guide is to serve as a suggestion for developers of OSM Carrier Boards and for OSM Module customers who wish to have a OSM based system developed. The document should also be valuable to FAEs and Product managers to help them understand the OSM Module infrastructure.
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MSMP1 Hardware Manual CHAPTER FOUR RESOURCES 4.1 Components 4.1.1 MPU STM32MP157 microprocessors are based on the flexible architecture of a Dual Arm® Cortex®-A7 core running up to 800 MHz and Cortex®-M4 at 209 MHz combined with a dedicated 3D graphics processing unit (GPU) and MIPI-DSI display interface and a CAN FD interface.
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STMicroelectronics. 4.1.2 LPDDR3 SDRAM The MSMP1 is equipped with 1 block of NANYA NT6CL128M32DM-H1 or NT6CL256M32AM LPDDR3 SDRAM resulting in up to 4/8 GB of 32bit memory. Device is available in the commercial temperature range -30°C. . . +105°C. The memory interface operates with 1866Mbps speed rate. The memory interface is clocked at 933MHz using the 1.2V/1.8V SDRAM standard interface.
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RES# 4.1.4 eMMC Flash The MSMP1 supports one eMMC NAND Flash in the range of 4-64 GByte. The eMMC provides a high-speed memory card interface compliant with JEDEC Version 5.0, eliminating the need for users to be concerned about directly controlling Flash Memories.
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I C and IO interface. MSMP1 is operational for supply voltages in the range of 2.8V to 5.5V. MSMP1 is available, depending on the installed PMIC, in a version to support either 1.8V IO-voltage or 3.3V IO-voltage. PMIC Derivatives...
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PA14 3V3, 680R to PA14 red PA13 3V3, 680R to PA13 green 4.2 Interfaces 4.2.1 I2C When using MSMP1 in conformity to the OSM standard two I2C interfaces are available: MPU Pin Function SiP Pads Remarks I2C2_SCL AA15 2k2 pullup to VCC...
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MSMP1 Hardware Manual 4.2.3 SPI When using MSMP1 in conformity to the OSM standard three SPI interface are available: MPU Pin Function SiP Pads SPI1_SCK SPI1_MISO SPI1_MOSI SPI1_NSS SPI3_SCK SPI3_MISO SPI3_MOSI SPI3_NSS SPI4_SCK SPI4_MISO SPI4_MOSI SPI4_NSS AA23 4.2.4 JTAG MPU Pin...
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– RESERVED – RESERVED AB25 – RESERVED AB26 – – – 4.3 Schematics Schematics for the MSMP1 SiP may be obtained on request. Please contact sales@aries-embedded.de. Below the OSM schematics footprint is shown: Chapter 4. Resources Page 39 of 42...
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