Aries Embedded MRZG2LS Hardware Manual

Hide thumbs

Table Of Contents

Quick Links

Download this manual

MRZG2LS/MRZV2LS Hardware Manual

Version:

1.1

Created on:

Apr 20, 2023

Created by:

Angeline Wamai, Andreas Widder

tial. This document may not be copied, reproduced, translated, changed or distributed

without the written approval of ARIES Embedded GmbH

Page 1 of 35

Table of Contents

Need help?

Do you have a question about the MRZG2LS and is the answer not in the manual?

Questions and answers

Summary of Contents for Aries Embedded MRZG2LS

Page 1 Apr 20, 2023 Created by: Angeline Wamai, Andreas Widder © ARIES Embedded GmbH. The information contained in this document is strictly confiden- tial. This document may not be copied, reproduced, translated, changed or distributed without the written approval of ARIES Embedded GmbH...
Page 2: Table Of Contents
2 Overview 2.1 MRZG2LS and MRZV2LS ........
Page 3 MRZG2LS/MRZV2LS Hardware Manual 3.13.1 MIP-CSI ......... . .
Page 4: About This Manual
ARIES Embedded. ARIES Embedded explicitly reserves the rights to change or add to the contents of this Preliminary User’s Manual or parts of it without notification.
Page 5: Registered Trademarks
The contents of this document may be subject of intellectual property rights (including but not limited to copyright, trademark, or patent rights). Any such rights that are not expressly licensed or already owned by a third party are reserved by ARIES Embedded GmbH. 1.5 Care and Maintenance •...
Page 6: Overview
OVERVIEW 2.1 MRZG2LS and MRZV2LS The MRZG2LS and MRZV2LS are SMARC V2.1 compliant System-on-Modules based on Renesas RZ Family architecture. They offer high-performance for embedded systems.The SMARC Modules are used as building blocks for portable and stationary embedded systems. The modular approach allows for the following;...
Page 7 MRZG2LS/MRZV2LS Hardware Manual Chapter 2. Overview Page 7 of 35...
Page 8: Feature Set
MRZG2LS/MRZV2LS Hardware Manual 2.2 Feature Set • Single or Dual Cortex-A55, up to 1GHz • optional AI accelerator; DRP-AI on MRZV2L • 3D Graphics engine (Arm Mali-G31) • Video Codec (H.264) • Cortex-M33 • 512MB – 4GB DDR4 RAM • SPI NOR •...
Page 9: Block Diagram
MRZG2LS/MRZV2LS Hardware Manual 2.3 Block Diagram 2.4 Order Codes The difference between the MRZG2LS and MRZV2LS is the microprocessor used. The connector used in with the RZ/V2L is pin-compatible with RZ/G2L. Therefore both function the same. Their key features are listed below: MRZG2LS-BAA •...
Page 10: Part Locations
MRZG2LS/MRZV2LS Hardware Manual 2.5 Part Locations Assembly Top Assembly Bottom Chapter 2. Overview Page 10 of 35...
Page 11: Mechanical Information
MRZG2LS/MRZV2LS Hardware Manual 2.6 Mechanical Information Chapter 2. Overview Page 11 of 35...
Page 12 MRZG2LS/MRZV2LS Hardware Manual Handling Recommendation To avoid mechanical damage to the components populated on SoM it is strongly recommended not to apply mechanical force on the Ball Grid Array (BGA) components. The BGA components are marked as shaded in the figure below: Chapter 2.
Page 13: Resources
MRZG2LS/MRZV2LS Hardware Manual CHAPTER THREE RESOURCES 3.1 MPU The RZ/G2L microprocessor includes a Cortex®-A55 (1.2 GHz) CPU, 16-bit DDR3L / DDR4 interface, 3D graphics engine with Arm Mali-G31 and video codec (H.264). It also has many interfaces such as camera input, display output, USB 2.0, and Gbit-Ether, making it ideal for applications such as entry-class industrial human-machine interfaces (HMIs) and embedded devices with video capabilities.
Page 14: Mpu Derivatives
• DDR4 or DDR3L Memory interface For more information about the RZ/G2L and RZ/V2L MCU please refer to the documentation which is available from Renesas. 3.1.1 MPU Derivatives Depending on the targeted MPU the following derivatives are populated on MRZG2LS: MPU Family Derivative Comment...
Page 15: Power Managment Ic
5P35023 again through the I2C interface. 3.5 DDR4 SDRAM By default the MRZG2LS SoM is populated 16bit wide with a 8GBit DDR4 SDRAM component K4A8G165WB-BITD. MPU Signals for DDR4...
Page 16 MRZG2LS/MRZV2LS Hardware Manual Table 1 – continued from previous page MPU Pin Function DDR4 MPU Pin Function DDR4 – DDR_BG0 AC26 DDR_DQS1_P DDR_ODT0 AC27 DDR_DQS1_N DDR_CLK_P AC29 DDR_DM1 DDR_CLK_N – DDR_CKE – DDR_CSO_N – – – 1V2_DDR4 – – DDR_RESET_N DDR_ADDR14 –...
Page 17: Sd-Card Interfaces
MRZG2LS/MRZV2LS Hardware Manual 3.6 SD-card Interfaces 3.6.1 MPU Signals for eMMC NAND Flash MRZG2LS supports a 4GByte to 64GByte eMMC NAND Flash. The eMMC device is a bootable device. The following table provides the connections MPU to eMMC NAND flash: Function...
Page 18: Spi And Qspi
10k pull-up 3.7.3 QSPI NOR FLASH MPU Signals for SPI NOR FLASH MRZG2LS supports a 128MBit to 512MBit QSPI NOR Flash. The SPI NOR device is a bootable device. The following table provides the connections MPU to SPI-NOR flash: MPU Pin...
Page 19: I2C
MRZG2LS/MRZV2LS Hardware Manual 3.8 I2C MPU Signals for I2C MPU Pin Function Connector Remarks P1 Pin RZ_I2C0.CLK 2k20 Pull-up RZ_I2C0.DAT 2k20 Pull-up RZ_I2C1.CLK S139 2k20 Pull-up RZ_I2C1.DAT S140 2k20 Pull-up RZ_I2C3.CLK 2k20 Pull-up RZ_I2C3.DAT 2k20 Pull-up 3.9 I2S MPU Signals for I2S...
Page 20: Ethernet
MRZG2LS/MRZV2LS Hardware Manual 3.10 Ethernet On the MRZG2LS SoM no/one/two Ethernet PHYs type Microchip KSZ9131RNXC can be populated. 3.10.1 Ethernet 1 MPU Signals to Ethernet PHY1 MPU Pin Function PHY1 ETH1_TXCLK ETH1_TX_CTL ETH1_TXD0 ETH1_TXD1 ETH1_TXD2 ETH1_TXD3 ETH1_RXCLK ETH1_RX_CTL ETH1_RXD0 ETH1_RXD1...
Page 21: Ethernet 2
TXRXP_B TXRXM_B LINK1000# TXRXP_C TXRXM_C LINK_ACT# TXRXP_D TXRXM_D 3.11 CAN MPU Signals for CAN MRZG2LS supports the 2 native CAN interfaces of the MPU as follows: MPU Pin Func- Connector tion P1 Pin AH22 CAN0_TX P143 AG22 CAN0_RX P144 AE23...
Page 22: Usb Interfaces
MRZG2LS/MRZV2LS Hardware Manual 3.12 USB Interfaces The MRZG2LS SoM supports 2 USB interfaces, USB0 and USB1. 3.12.1 Interface USB0 Interface USB0 functions as USB2.0 OTG interface. MPU Signals for USB0 MPU Pin Function Connector P1 Pin USB0.D_P USB0.D_N USB0.EN_OC# AH10 USB0_VBUS_DET USB0.OTG_ID...
Page 23: Mipi
MRZG2LS/MRZV2LS Hardware Manual 3.13 MIPI 3.13.1 MIP-CSI The MRZG2LS supports a 4 lane wide MIPI-CSI interface: MPU Pin Function Connector P1 Pin AG13 CSI.CLK_P AG12 CSI.CLK_N AJ13 CSI.DATA0_P AH13 CSI.DATA0_N AJ12 CSI.DATA1_P AH12 CSI.DATA1_N AJ14 CSI.DATA2_P AH14 CSI.DATA2_N AJ11 CSI.DATA3_P AH11 CSI.DATA3_N...
Page 24: Jtag
MRZG2LS/MRZV2LS Hardware Manual 3.14 JTAG The JTAG signals of the CPU are routed to the fpc-connector P2, type 10051922-1010EHLF (Amphenol) and comply to the following pinout: MPU Pin Function Connector/ Remarks VDD_JTAG 1.8V TRST# 10k Pull-up 10k Pull-up 10k Pull-up 10k Pull-up n.c.
Page 25: A/D-Converter (Adc)
MRZG2LS/MRZV2LS Hardware Manual 3.16 A/D-Converter (ADC) The ADC signals of the CPU are routed to the fpc-connector P3, type 10051922-1010EHLF (Amphenol) and comply to the following pinout: MPU Pin Function Connector Remarks P3/ Pin ADC_CH0 47k Pull-down, optional, not populated...
Page 26: P1 - 314 Pins Edge Connector
MRZG2LS/MRZV2LS Hardware Manual 3.17 P1 - 314 Pins Edge Connector 3.17.1 Pin Numbering Chapter 3. Resources Page 26 of 35...
Page 27: Top Side
MRZG2LS/MRZV2LS Hardware Manual 3.17.2 Top Side Connector/Pin Function Device/ Pin Remarks SMB_ALERT# n.c. CSI1_CK+ MPU AG13 CSI1_CK- MPU AG12 GBE1_SDP n.c. GBE0_SDP n.c. CSI1_RX0+ MPU AJ13 CSI1_RX0- MPU AH13 CSI1_RX1+ MPU AJ12 CSI1_RX1- MPU AH12 CSI1_RX2+ MPU AJ14 CSI1_RX2- MPU AH14...
Page 28 MRZG2LS/MRZV2LS Hardware Manual Table 2 – continued from previous page Connector/Pin Function Device/ Pin Remarks SATA_TX+ n.c. SATA_TX- n.c. SATA_RX+ n.c. SATA_RX- n.c. SPI1_CS0# MPU B19 SPI1_CS1# n.c. SPI1_CK MPU A19 SPI1_DIN MPU D18 SPI1_DO MPU F17 USB0+ MPU AH9...
Page 29 MRZG2LS/MRZV2LS Hardware Manual Table 2 – continued from previous page Connector/Pin Function Device/ Pin Remarks HDMI_D0+ n.c. HDMI_D0- n.c. P100 P101 HDMI_CK+ n.c. P102 HDMI_CK- n.c. P103 P104 HDMI_HPD n.c. P105 HDMI_CTRL_CK n.c. P106 HDMI_CRL_DAT n.c. P107 DP1_AUX_SEL n.c. P108...
Page 30 MRZG2LS/MRZV2LS Hardware Manual Table 2 – continued from previous page Connector/Pin Function Device/ Pin Remarks P143 CAN0_TX MPU AH22 P144 CAN0_RX MPU AG22 P145 CAN1_TX MPU AE23 P146 CAN1_RX MPU AF23 P147 VDD_IN P148 VDD_IN P149 VDD_IN P150 VDD_IN P151...
Page 31: Bottom Side
MRZG2LS/MRZV2LS Hardware Manual 3.17.3 Bottom Side Connector/Pin Function Device/ Pin Remarks I2C_CAM1_CK MPU B24 I2C_CAM1_DAT MPU A25 RSVD n.c. I2C_CAM0_CK n.c. CAM_MCK n.c. I2C_CAM_DAT n.c. CSI0_CK+ n.c. CSI0_CK- n.c. CSI0_RX0+ n.c. CSI0_RX0- n.c. CSI0_RX1+ n.c. CSI0_RX1- n.c. GBE1_MDIO+ PHY2 2...
Page 32 MRZG2LS/MRZV2LS Hardware Manual Table 3 – continued from previous page Connector/Pin Function Device/ Pin Remarks I2C_GP_CK MPU D3 I2C_GP_DAT MPU C2 I2S2_LRCK MPU A10 I2S2_SDOUT MPU C12 I2S2_SDIN MPU D13 I2S2_CK MPU B10 SATA_ACT# n.c. USB5_EN_OC# n.c. QSPI_IO_2 n.c. QSPI_IO_3 n.c.
Page 33 MRZG2LS/MRZV2LS Hardware Manual Table 3 – continued from previous page Connector/Pin Function Device/ Pin Remarks DP0_LANE1- n.c. HDMI_D0+ n.c. HDMI_D0- n.c. S100 DP0_LANE2- n.c. S101 S102 HDMI_CK- n.c. S103 DP0_LANE3- n.c. S104 HDMI_HPD n.c. S105 HDMI_CTRL_CK n.c. S106 HDMI_CTRL_DA n.c.
Page 34 MRZG2LS/MRZV2LS Hardware Manual Table 3 – continued from previous page Connector/Pin Function Device/ Pin Remarks S146 PCIE_WAKE# n.c. S147 VDD_RTC S148 LID# n.c. S149 SLEEP# n.c. S150 VIN_PWR_BAD# PMIC 47 S151 CHARGING# n.c. S152 CHARGER_PRSNT# n.c. S153 CARRIER_STBY# PMIC 56...
Page 35: Contents
MRZG2LS/MRZV2LS Hardware Manual 3.18 Schematics Schematics for the MRZG2LS and MRZV2LS may be obtained on request. Please contact sales@aries- embedded.de for more information. Chapter 3. Resources Page 35 of 35...

This manual is also suitable for:

Mrzv2ls