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Aries Embedded RISC-V on MAX10 User Manual

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RISC-V on MAX10 User Guide
RISC-V on MAX10 User Guide
Version:
1.0
Created on:
Feb 14, 2022
Created by:
Johannes Schwenk
The information contained in this document is strictly confidential.
This document may not be copied, reproduced, translated, changed or
distributed without the written approval of ARIES Embedded GmbH.
© ARIES Embedded GmbH.
Page 1 of 20

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Summary of Contents for Aries Embedded RISC-V on MAX10

  • Page 1 Created by: Johannes Schwenk © ARIES Embedded GmbH. The information contained in this document is strictly confidential. This document may not be copied, reproduced, translated, changed or distributed without the written approval of ARIES Embedded GmbH. Page 1 of 20...

  • Page 2: Table Of Contents

    RISC-V on MAX10 User Guide CONTENTS: 1 About this manual 1.1 Imprint ..........
  • Page 3 RISC-V on MAX10 User Guide 5.2 C-Firmware ..........

  • Page 4: About This Manual

    ARIES Embedded. ARIES Embedded explicitly reserves the rights to change or add to the contents of this Preliminary User Guide or parts of it without notification.

  • Page 5: Copyright

    1.3 Copyright This document may not be copied, reproduced, translated, changed or distributed, completely or partially in any form without the written approval of ARIES Embedded GmbH. 1.4 Registered Trademarks The contents of this document may be subject of intellectual property rights (including but not limited to copyright, trademark, or patent rights).

  • Page 6: Introduction

    RISC-V on MAX10 User Guide CHAPTER INTRODUCTION reference designs demonstrate the implementation of an open-source RISC-V core running FreeRTOS and interfacing with different peripherals. This guide shows how to install the neccessacy requirements and how to run and modify the RISC-V examples on the MX10 and SpiderBoard SoMs. The examples are also suitable as starting point for developement.

  • Page 7: Risc-V Core Benchmark

    RISC-V on MAX10 User Guide 2.1.1 RISC-V Core Benchmark The following tests were conducted on the MX10-U (with 10M50DAF256I7G, Speedgrade 7) using Quartus 20.1 Lite. Quartus Compilation effort was set to Performance (Aggressive) with most options that increase max- imum frequency turned on. The clock frequency of the FPGA system was 25 MHz. The benchmarks were compiled using GCC version 11.1.0 with the compiler flags -O3...

  • Page 8: Requirements

    RISC-V on MAX10 User Guide CHAPTER THREE REQUIREMENTS 3.1 MAX10 SoMs To run the RISC-V demos on a MAX10 board one of the following SoMs is required: • SpiderSoM-S (10M08SAU169C8G) • MX10-S8 (10M08DAF256C8G) • MX10-U (10M50DAF256I7G) To compile the firmware the RISC-V GCC toolchain is required.

  • Page 9: Risc-V Gcc

    RISC-V on MAX10 User Guide 3.3 RISC-V GCC This guide installs the toolchain under /opt/riscv, this path is configurable. For other Linux distributions the toolchain can be installed similarly. For more information, please visit the official RISC-V GNU Compiler Toolchain repository.

  • Page 10: Openocd

    RISC-V on MAX10 User Guide 3.5 OpenOCD The PIC onboard programming solution is used in conjunction with OpenOCD. For OpenOCD, the libftdi driver with blaster support is required. 3.5.1 Linux On Linux the apt version usually suffices: sudo apt install openocd Create a bash script to programm the FPGA more conveniently.

  • Page 11: Serial Console

    RISC-V on MAX10 User Guide 3.6 Serial Console The reference design implements UART connected via PIC-USB to the host PC. To use the serial commu- nication to the FPGA a console emulator is required. 3.6.1 Linux One can install picocom on Linux and add the user to the dialout-group using the following commands on...
  • Page 12 RISC-V on MAX10 User Guide Now the serial port is available as a Windows COM device and can be used with tools such as PuTTY or TeraTerm. Chapter 3. Requirements Page 12 of 20...

  • Page 13: Programming The Demos

    RISC-V on MAX10 User Guide CHAPTER FOUR PROGRAMMING THE DEMOS Note: The directory Prebuild contains a precompiled firmware image aswell as a prebuild FPGA image. These can be used to skip the corresponding steps in this chapter. 4.1 Compiling the Firmware Navigate to the project directory corresponding to the module (Spider_S, MX10_S8, MX10_U).

  • Page 14: Programming The Fpga

    RISC-V on MAX10 User Guide 4.3 Programming the FPGA The MAX10 FPGA supports programming the SRAM cells integrated into the FPGA fabric, this configura- tion is lost whenever the FPGA is powered off and as such is useful for testing and debugging. The MAX10 FPGA also includes internal non-volatile FLASH to store a configuration image, which on powerup will be loaded into the SRAM.

  • Page 15: Reference Design

    RISC-V on MAX10 User Guide CHAPTER FIVE REFERENCE DESIGN For each of the supported MAX10 SoMs a reference design is included. The reference design implements: • RISC-V 32-bit Core – PicoRV32 RV32IM (SpiderSoM-S) – VexRiscv RV32IM (MX10-S) – VexRiscv+Cache RV32IMAFC (MX10-U) •...

  • Page 16: Intel Platform Designer (Qsys)

    RISC-V on MAX10 User Guide 5.1.1 Intel Platform Designer (Qsys) The Intel Platform Designer implements the RISC-V system. The CPU core and peripheral devices are instatiated, configured and communicate via the Avalon Interconnect. Each device occupies a memory range in the address space, the interconnect will automatically resolve the access signals.

  • Page 17: Vexriscv

    RISC-V on MAX10 User Guide Parameter Description Enable Interrupts Enables the internal interrupt controller. Masked IRQ A 1 bit in this bitmask permanently disables the corresponding interrupt. Latched IRQ A 1 bit in this bitmask latches the interrupt signal (edge-triggered) instead of operating on level sensitive interrupts.

  • Page 18: Freertos

    RISC-V on MAX10 User Guide 5.2.2 FreeRTOS For FreeRTOS the RISC-V specific files have been moved to the subdirectory FreeRTOS/portable. Timer and software interrupts are dedicated to FreeRTOS to provide context switching. To modify the reference to the current task, two additional functions (void StoreStackPointerInCurrentTCB(uintptr_t stack) and uintptr_t LoadStackPointerFromCurrentTCB()) were added in task.h and tasks.c.

  • Page 19: Adding A Second Uart To Qsys

    RISC-V on MAX10 User Guide 5.3.2 Adding a second Uart to Qsys Note: This section uses the Spider_S project, there may be small differences between projects that have to be transfered. Open the Qsys system in Intel Platform Designer. Search in the IP Catalog for “uart”, select the UART (RS-232 Serial Port) Intel FPGA IP and press Add.

  • Page 20: Contents

    RISC-V on MAX10 User Guide Modify the component instantiation, this example routes the Uart signals to PMod: component qsys0 port map clk_clk => clk25, reset_reset_n => resetn, gpio_export => gpio, uart_rxd => uart_rx, uart_txd => uart_tx, uart2_rxd => pmod_j3(1), uart2_txd =>...

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