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OVERVIEW 2.1 M100PF The M100PF is based on the PolarFire FPGA family by Microchip. The SoM targets demanding industrial and medical applications and offers the full flexibility of the populated FPGAs. The populated FPGAs deliver the industry’s lowest power at mid-range densities with exceptional security and reliability. The FPGA SoM for Embedded Applications spans from 100K logic elements (LEs) to 300K LEs, features 12.7G...
The populated Samtec connectors require certain mechanical force to insert the SoM into its mating base- board con- nectors. To avoid mechanical damage to the components populated on M100PF it is strongly recommended not to apply mechanical force on the Ball Grid Array (BGA) components. The BGA compo- nents are marked as shaded in the figure below: Chapter 2.
M100PF Hardware Manual CHAPTER THREE RESOURCES 3.1 Components 3.1.1 FPGA The Polarfire FPGA on the M100PF comes in the FCG484 (23x23, 1.0 mm) package and up provides to 244 User I/O (96 HSIO, 148 GPIO) and 8 XCVRs. Features MPF100T MPF200T MPF300T...
M100PF Hardware Manual 3.1.3 e.MMC Flash M100PF features up to 64 GB of eMMC Flash using Micron MTFC4GACAANA-4M IT. Function FPGA Pin RSTN DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 3.1.4 SPI NOR Flash MT25QU01GBBB8E12 SPI NOR Flash provides 128 MiB of non-volatile storage. On power-up the SPI NOR is connected to the FPGA, allowing the FPGA to load one of multiple configuration images stored on the SPI Flash.
The RTCC is connected to I2C using address 0x6F, the EEPROM uses address 0x57. Function FPGA Pin Description RTC_MFP RTC multi function pin 3.1.9 SERDES M100PF provides 8 SERDES lanes each with up to 12.7 Gbps datarate. Function FPGA Pin Connector Function FPGA Pin Connector...
If the FPGA is configured as SPI slave, then its data directions are swapped. 3.3 Clocking The clocking scheme on the M100PF is generated by an IDT 5P49V6965 Clock Generator (PLL). Its base is sourced from a 25 MHz oscillator to generate the required clocks for the board’s components. The IDT 5P49V6965 is accessible from FPGA on the I2C 1 bus at address 0xD4 for reconfiguration.
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M100PF Hardware Manual I2C 1 Device Description dress 0xD4 5P49V6965 Clock Generator Allows reconfiguration of the clocks present on M100PF 0x57 MCP794xx EEPROM of the RTCC 0x6F MCP794xx Real Time Clock Calendar Master Polarfire FPGA Connected to FPGA Pins J4 (SCL) and H4 (SDA)
M100PF Hardware Manual 3.5 JTAG The M100PFEVP Baseboard provides a JTAG header for the FlashPro programmer to programm the FPGA using Microchip’s standard tools. The PCAL6408ABS IO-Expander is connected to Test-Reset via bit 0x10. Function FPGA Pin Connector 6 (J1 A)
M100PF Hardware Manual 3.7.2 Ethernet Function FPGA Pin Connector Function FPGA Pin Connector ETH0_MDIO 115 (J2 B) ETH1_MDIO 164 (J1 C) ETH0_MDC 112 (J2 B) ETH1_MDC 161 (J1 C) ETH0_GTXCLK 113 (J2 B) ETH1_GTXCLK 159 (J1 C) ETH0_TX_EN 114 (J2 B)
M100PF Hardware Manual 3.7.4 GPIO The following pins are available for GPIO: FPGA Connector FPGA Connector FPGA Connector FPGA Connector 30 (J1 A) 149 (J2 C) 147 (J2 C) 80 (J2 B) 54 (J1 A) 153 (J2 C) 131 (J2 C)
M100PF Hardware Manual 3.7.5 Samtec Connector M100PF uses two Samtec QSH-090-01-F-D-A connectors to supply its signals to a baseboard. Below are tables with the pins of the connectors and their corresponding function. 3.7.6 Connector J1 Connector J1 A Function Function...
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M100PF Hardware Manual Connector J1 B Function Function Function Function GPIO_G2 GPIO_H2 GPIO_J2 GPIO_L2 GPIO_M2 GPIO_H1 UART1_TX GPIO_J1 UART1_RX GPIO_K1 ETH1_RXC GPIO_F1 GPIO_T5 GPIO_R3 GPIO_T1 GPIO_R1 Ground Plate Ground Plate Ground Plate Ground Plate Connector J1 C Function Function Function...
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