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Asus AAEON PICO-APL3-SEMI User Manual
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Asus AAEON PICO-APL3-SEMI User Manual

Asus AAEON PICO-APL3-SEMI User Manual

Pico-semi system
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PICO-APL3-SEMI
PICO-SEMI System
th
User's Manual 7
Ed
Last Updated: April 9, 2024

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Summary of Contents for Asus AAEON PICO-APL3-SEMI

  • Page 1 PICO-APL3-SEMI PICO-SEMI System User’s Manual 7 Last Updated: April 9, 2024...
  • Page 2 Copyright Notice This document is copyrighted, 2024. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of the original manufacturer.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows® is a registered trademark of Microsoft Corp. ⚫ Intel®, Celeron® and Pentium® are registered trademarks of Intel Corporation ⚫ ITE is a trademark of Integrated Technology Express, Inc. ⚫...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity PICO-APL3-SEMI ⚫ If any of these items are missing or damaged, please contact your distributor or sales representative immediately. Preface...
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document.
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON System QO4-381 Rev.A0 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯 醚(PBDE) (Pb) (Hg) (Cd) (Cr(VI)) (PBB) 印刷电路板 × ○ ○ ○ ○ ○ 及其电子组件 外部信号 × ○ ○ ○ ○ ○ 连接器及线材 ○ ○...
  • Page 10 China RoHS Requirement (EN) Hazardous and Toxic Materials List AAEON System QO4-381 Rev.A0 Hazardous or Toxic Materials or Elements Component Name PCB and Components Wires & Connectors for Ext.Connections Chassis CPU & RAM HDD Drive LCD Module Optical Drive Touch Control Module Battery This form is prepared in compliance with the provisions of SJ/T 11364.
  • Page 11 Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Block Diagram ......................5 Chapter 2 – Hardware Information ..................6 Dimensions ....................... 7 Jumpers and Connectors ..................12 List of Jumpers ......................13 2.3.1 Auto Power Button Enable/Disable Selection (JP6) ....... 13 2.3.2 Clear CMOS Jumper (JP7) ................
  • Page 12 Setup Submenu: Main ................... 31 Setup Submenu: Advanced ................. 32 3.4.1 Trusted Computing ..................33 3.4.2 CPU configuration ..................35 3.4.3 SATA Configuration ..................36 3.4.4 Hardware Monitor ..................38 3.4.4.1 CPU Smart Fan Mode Configuration ..........39 3.4.5 SIO Configuration ..................40 3.4.5.1 Serial Port 1 Configuration ...............41 3.4.5.2...
  • Page 13 Appendix D – Programming Digital IO ................68 Digital I/O Register ....................69 Digital I/O Sample Program ................70 Preface XIII...
  • Page 14 Chapter 1 Chapter 1 - Product Specifications...
  • Page 15 Specifications System Form Factor PICO-SEMI Processor Intel® Pentium® Processor N4200 (4C, 1.1 GHz, up to 2.5 GHz, TDP 6W) Intel® Celeron® Processor N3350 (2C, 1.1 GHz, up to 2.4 GHz, TDP 6W) Chipset Integrated with Intel® SoC Memory Type Onboard DDR3L 1866, Single Channel, Non-ECC, Max 4GB BIOS UEFI...
  • Page 16 Power Connector DC Jack Connector Power Consumption Intel® Pentium® Processor N4200, DDR3L 8GB x 1, 1.08A, eMMC 32GB @+12V (Typical) Display Controller Intel® HD Graphics 500/505 LVDS/eDP — Display Interface HDMI 1.4 x 1, 3840 x 2160 @30Hz Multiple Display —...
  • Page 17 Internal I/O DIO/GPIO — SMBus/I2C — — Front Panel HDD LED, PWR LED, Power Button, Buzzer, Reset Others — Expansion Mini PCIe/mSATA — M.2 2230 E-Key x 1 (PCIe 3.0 [x1] + USB 2.0) M.2 2280 B-Key x 1 (SATA + USB 2.0) Others —...
  • Page 18 Block Diagram Chapter 1 – Product Specifications...
  • Page 19 Chapter 2 Chapter 2 – Hardware Information...
  • Page 20 Dimensions Chapter 2 – Hardware Information...
  • Page 21 System with Heatsink Chapter 2 – Hardware Information...
  • Page 22 Heatsink Assembly Chapter 2 – Hardware Information...
  • Page 23 Board Com ponent Side Chapter 2 – Hardware Information...
  • Page 24 Solder Side Solder Side Chapter 2 – Hardware Information...
  • Page 25 Jumpers and Connectors Component Side Solder Side Com ponent Side Chapter 2 – Hardware Information...
  • Page 26 List of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Label Function Auto Power Button Enable/Disable Selection Clear CMOS Jumper 2.3.1 Auto Power Button Enable/Disable Selection (JP6) 1 2 3 Disable Enable (Default) Disable Auto Power Button JP6 (1-2): Need to use power button JP6 (1-2) to power on...
  • Page 27 List of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function DC Jack SATA RTC Battery CN10 RJ-45 LAN CN11 USB 3.2 Gen 1 Ports 0 and 1 CN12 Line In/Line out/Mic In CN13...
  • Page 28 2.4.1 DC Jack (CN1) Pin Name Signal Type Signal Level +12V +12V 2.4.2 SATA (CN8) Pin 1 Pin 7 Pin Name Signal Type Signal Level SATA_TX- DIFF SATA_TX- DIFF SATA_RX- DIFF SATA_RX+ DIFF Chapter 2 – Hardware Information...
  • Page 29 2.4.3 Battery (CN9) Pin Name Signal Type Signal Level +BAT_RTC 3.3V 2.4.4 RJ-45 LAN Port (CN10) Pin Name Signal Type Signal Level MDI0+ DIFF MDI0- DIFF MDI1+ DIFF MDI2+ DIFF MDI2- DIFF MDI1- DIFF MDI3+ DIFF MDI3- DIFF Chapter 2 – Hardware Information...
  • Page 30 2.4.5 USB 3.2 Gen 1 Ports 0 and 1 (CN11) Port 1 11 12 13 Port 0 2 3 4 Pin Name Signal Type Signal Level +5VA USB0_D- DIFF USB0_D+ DIFF USB0_SSRX− DIFF USB0_SSRX+ DIFF USB0_SSTX− DIFF USB0_SSTX+ DIFF +5VA USB1_D- DIFF USB1_D+...
  • Page 31 2.4.6 Audio I/O Port (CN12) Pin Name Signal Type Signal Level MIC_L Audio MIC_R Audio GND_AUDIO AGND LINE_L_IN Audio LINE_R_IN Audio GND_AUDIO AGND LEFT_OUT Audio GND_AUDIO AGND RIGHT_OUT Audio Chapter 2 – Hardware Information...
  • Page 32 2.4.7 HDMI Port (CN13) Pin Name Signal Type Signal Level TMDS_DAT2+ DIFF TMDS_DAT2- DIFF TMDS_DAT1+ DIFF TMDS_DAT1- DIFF TMDS_DAT0+ DIFF TMDS_DAT0- DIFF TMDS_CLK+ DIFF TMDS_CLK- DIFF DDC_CLK DDC_DATA HPLG_DETECT 2.4.8 I2S/I2C Connector (CN37) Pin Name Signal Type Signal Level +V3.3A 3.3V I2S1_SYNC Signal...
  • Page 33 Pin Name Signal Type Signal Level I2S1_SDO Signal I2S1_MCLK Signal I2S1_BCLK Signal I2C2_SCL Signal I2C2_SDA Signal 2.4.9 SATA Power (CN39) Pin Name Signal Type Signal Level +12V +12V Chapter 2 – Hardware Information...
  • Page 34 2.4.10 COM Port (RS-232) (CN51/CN61) Pin Name Signal Type Signal Level IN/ PWR Chapter 2 – Hardware Information...
  • Page 35 2.4.11 Front Panel Header (CN53) Pin Name Pin Name PWR Button FP_IDELED# +3.3V FP_BUZZER RESET Button 2.4.12 M.2 2230 E-Key (CN55) Pin Name Signal Type Signal Level +3.3VA 3.3V USB+ DIFF +3.3VA 3.3V USB- DIFF Chapter 2 – Hardware Information...
  • Page 36 Pin Name Signal Type Signal Level PCIE_TXP DIFF PCIE_TXN DIFF PCIE_RXP DIFF PCIE_RXN DIFF CLK_PCIE_P DIFF CLK_PCIE_N DIFF Chapter 2 – Hardware Information...
  • Page 37 Pin Name Signal Type Signal Level RST# PCIE_CLKREQ# BT_DISABLE# PCIE_WAKE# WIFI_DISABLE# +3.3VA 3.3V +3.3VA 3.3V 2.4.13 M.2 2280 B-Key (CN56) Pin Name Signal Type Signal Level +3.3V 3.3V Chapter 2 – Hardware Information...
  • Page 38 Pin Name Signal Type Signal Level +3.3V 3.3V USB_DP DIFF USB_DN DIFF 3.3V USB3_RX_N (Reserved) Diff USB3_RX_P (Reserved) Diff USB3_TX_N (Reserved) Diff Chapter 2 – Hardware Information...
  • Page 39 Pin Name Signal Type Signal Level USB3_TX_P (Reserved) Diff SATA_RXP DIFF SATA_RXN DIFF SATA_TXN DIFF SATA_TXP DIFF Chapter 2 – Hardware Information...
  • Page 40 Pin Name Signal Type Signal Level +3.3V 3.3V +3.3V 3.3V +3.3V 3.3V Chapter 2 – Hardware Information...
  • Page 41 Chapter 3 Chapter 3 - AMI BIOS Setup...
  • Page 42 System Test and Initialization These routines test and initialize board hardware. If the routines encounter an error during the tests, you will either hear a few short beeps or see an error message on the screen. There are two kinds of errors: fatal and non-fatal. The system can usually continue the boot up sequence with non-fatal errors.
  • Page 43 AMI BIOS Setup AMI BIOS ROM has a built-in Setup program that allows users to modify the basic system configuration. This type of information is stored in battery-backed CMOS RAM and BIOS NVRAM so that it retains the Setup information when the power is turned off. Entering Setup Power on the computer and press <Del>or <ESC>...
  • Page 44 Setup Submenu: Main Press “Delete” to enter Setup. Chapter 3 – AMI BIOS Setup...
  • Page 45 Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup...
  • Page 46 3.4.1 Trusted Computing Options Summary Security Device Support Disable Enable Optimal Default, Failsafe Default Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. SHA-1 PCR Bank Disable Enable Optimal Default, Failsafe Default...
  • Page 47 Options Summary Platform Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or disable Platform Hierarchy. Storage Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Storage Hierarchy. Endorsement Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Endorsement Hierarchy. TPM2.0 UEFI Spec Version TCG_1_2 TCG_2...
  • Page 48 3.4.2 CPU configuration Options Summary C-States Disabled Enabled Optimal Default, Failsafe Default Enable/Disable C States. EIST™ Disabled Enabled Optimal Default, Failsafe Default Enable/Disable Intel SpeedStep. Turbo Mode Disabled Enabled Optimal Default, Failsafe Default Turbo Mode. Power Limit 1 Enable Disabled Optimal Default, Failsafe Default Enabled Enable/Disable Power Limit 1.
  • Page 49 Options Summary When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology. VT-d Disabled Optimal Default, Failsafe Default Enabled Enable/Disable CPU VT-d. 3.4.3 SATA Configuration Options Summary Chipset SATA Disabled Enabled Optimal Default, Failsafe Default Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports the 2 black internal SATA ports (up to 3Gb/s supported per port).
  • Page 50 Options Summary SATA Port 0 Hot Plug Disabled Optimal Default, Failsafe Default Capability Enabled If enabled, SATA port will be reported as Hot Plug capable. Port 1 Disabled Enabled Optimal Default, Failsafe Default Enable or Disable SATA Port. SATA Port 0 Hot Plug Disabled Optimal Default, Failsafe Default Capability...
  • Page 51 3.4.4 Hardware Monitor Chapter 3 – AMI BIOS Setup...
  • Page 52 3.4.4.1 CPU Smart Fan Mode Configuration Options Summary CPU Smart Fan Control Full Mode Optimal Default, Failsafe Default Manual Mode by PWM Auto Mode by PWM PWM signal Non-inverting Inverting Optimal Default, Failsafe Default Select output PWM of inverting or non-inverting signal. Monitor Thermal THERMAL_SRC1(T1) Optimal Default, Failsafe Default...
  • Page 53 Options Summary Slope (PWM) 1 (PWM) Optimal Default, Failsafe Default Slope (PWM). 3.4.5 SIO Configuration Chapter 3 – AMI BIOS Setup...
  • Page 54 3.4.5.1 Serial Port 1 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=3F8h; IRQ=4 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.
  • Page 55 3.4.5.2 Serial Port 2 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=2F8h; IRQ=3 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.
  • Page 56 3.4.6 Power Management Options Summary Power Mode ATX Type Optimal Default, Failsafe Default AT Type Select system power mode. Restore AC Power Loss Last State Optimal Default, Failsafe Default Always On Always Off RTC wake system from S5 Disable Optimal Default, Failsafe Default Fixed Time Fixed Time: System will wake on the hr::min::sec specified.
  • Page 57 3.4.7 Digital IO Port Configuration Options Summary DIO Port* Output Input Set DIO as Input or Output. Output Level High Optimal Default, Failsafe Default Set output level when DIO pin is output. Chapter 3 – AMI BIOS Setup...
  • Page 58 Setup Submenu: Chipset Chapter 3 – AMI BIOS Setup...
  • Page 59 3.5.1 North Bridge Chapter 3 – AMI BIOS Setup...
  • Page 60 Setup Submenu: Security Change User/Supervisor Password You can install a Supervisor password, and if you install a supervisor password, you can then install a user password. A user password does not provide access to many of the features in the Setup utility. If you highlight these items and press Enter, a dialog box appears which lets you enter a password.
  • Page 61 Setup Submenu: Boot Options Summary Quiet Boot Disabled Enabled Optimal Default, Failsafe Default EnableDisable showing boot logo. Monitor Mwait Disable Enabled Auto Optimal Default, Failsafe Default Enable/Disable Monitor Mwait. To install Linux OS, please set this item to disable. Ipv4 PXE Support Disabled Optimal Default, Failsafe Default Enabled...
  • Page 62 Setup Submenu: Exit Chapter 3 – AMI BIOS Setup...
  • Page 63 Chapter 4 Chapter 4 – Drivers Installation...
  • Page 64 Driver Download/Installation Drivers for the PICO-APL3-SEMI can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/pico-itx-boards-pico-apl3-semi Download the driver(s) you need and follow the steps below to install them. Install Chipset Driver Open the Chipset Driver folder and open the SetupChipset.exe file Follow the instructions Drivers will be installed automatically Install Graphic Driver...
  • Page 65 Install TXE Driver Open the ME & TXE Driver folder and open the SetupTXE.exe file Follow the instructions Driver will be installed automatically Install Serial IO Driver Open the COM Port Driver folder and open the SetupSerialIO.exe file Follow the instructions Driver will be installed automatically Chapter 4 –...
  • Page 66 Appendix A Appendix A - Watchdog Timer Programming...
  • Page 67 Watchdog Timer Registers Table 1: Embedded BRAM Relative Register Table Default Value Note Index 0x284(Note1) BRAM Index Register Data 0x285(Note2) BRAM Data Register Logical Device Number 0xA8(Note3) Watch dog Logical Device Number Function and Device Number 0x00(Note4) Watch dog Function/Device Number Table 2: Watchdog Relative Register Table Option BitNum...
  • Page 68 ************************************************************************************ // Embedded BRAM relative definition (Please reference to Table 1) #define byte EcBRAMIndex //This parameter is represented from Note1 #define byte EcBRAMData //This parameter is represented from Note2 #define byte BRAMLDNReg //This parameter is represented from Note3 #define byte BRAMFnDataReg //This parameter is represented from Note4 #define byte EcBRAMReadByte(byte Offset);...
  • Page 69 ************************************************************************************ VOID Main(){ // Procedure : AaeonWDTConfig // (byte)Timer : Time of WDT timer.(0x00~0xFF) // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. AaeonWDTEnable(); ************************************************************************************ Appendix A – Watchdog Timer Programming...
  • Page 70 ************************************************************************************ // Procedure : AaeonWDTEnable VOID AaeonWDTEnable (){ WDTEnableDisable(1); // Procedure : AaeonWDTConfig VOID AaeonWDTConfig (){ // Disable WDT ounting WDTEnableDisable(0); // WDT relative parameter setting WDTParameterSetting(); VOID WDTEnableDisable(byte Value){ ECBRAMWriteByte(TimerReg , Value); VOID WDTParameterSetting(){ By te TempByte; // Watchdog Timer counter setting ECBRAMWriteByte(TimerReg , TimerVal);...
  • Page 71 ************************************************************************************ VOID ECBRAMWriteByte(byte OPReg, byte OPBit, byte Value){ IOWriteByte(EcBRAMIndex, 0x10); IOWriteByte(EcBRAMData, BRAMLDNReg); IOWriteByte(EcBRAMIndex, 0x11); IOWriteByte(EcBRAMData, BRAMFnDataReg); IOWriteByte(EcBRAMIndex, 0x13 + OPReg); IOWriteByte(EcBRAMData, Value); IOWriteByte(EcBRAMIndex, 0x12); IOWriteByte(EcBRAMData, 0x30); //Write start Byte ECBRAMReadByte(byte OPReg){ IOWriteByte(EcBRAMIndex, 0x10); IOWriteByte(EcBRAMData, BRAMLDNReg); IOWriteByte(EcBRAMIndex, 0x11); IOWriteByte(EcBRAMData, BRAMFnDataReg); IOWriteByte(EcBRAMIndex, 0x12); IOWriteByte(EcBRAMData, 0x10);...
  • Page 72 Appendix B Appendix B - I/O Information...
  • Page 73 I/O Address Map Appendix B – I/O Information...
  • Page 74 Memory Address Map Appendix B – I/O Information...
  • Page 75 IRQ Mapping Chart Appendix B – I/O Information...
  • Page 76 Appendix B – I/O Information...
  • Page 77 Appendix B – I/O Information...
  • Page 78 Appendix B – I/O Information...
  • Page 79 Appendix C Appendix C – Mating Connectors...
  • Page 80 List of Mating Connectors and Cables The table notes mating connectors and available cables. Connector Mating Connector Function Available Cable Cable P/N Label Vendor Model no Hirose FX18-80S-0.8SV20 N/A Connector Battery Molex 51021-0200 Battery Cable 175011301C CN12 Audio Molex 51021-1000 Audio Cable 1709100254 External...
  • Page 81 Appendix D Appendix D – Programming Digital IO...
  • Page 82 Digital I/O Register Table 1: Embedded BRAM Relative Register Table Default Value Note Index 0x284(Note1) BRAM Index Register Data 0x285(Note2) BRAM Data Register Logical Device Number 0xA2(Note3) Watch dog Logical Device Number IO DirectionFunction and 0x00(Note4) DIO Input/Output Function/Device Device Number Number IO Vaule/Status Function and 0x01(Note5)
  • Page 83 Digital I/O Sample Program ************************************************************************************ // Embedded BRAM relative definition (Please reference to Table 1) #define byte EcBRAMIndex //This parameter is represented from Note1 #define byte EcBRAMData //This parameter is represented from Note2 #define byte BRAMLDNReg //This parameter is represented from Note3 #define byte BRAMFnData0Reg //This parameter is represented from Note4 #define byte BRAMFnData1Reg //This parameter is represented from Note5 #define void EcBRAMWriteByte(byte Offset, byte Value);...
  • Page 84 ************************************************************************************ VOID Main(){ Boolean PinStatus ; // Procedure : AaeonReadPinStatus // Input : Example, Read Digital I/O Pin 1 status // Output : InputStatus : 0: Digital I/O Pin level is low 1: Digital I/O Pin level is High PinStatus = AaeonReadPinStatus(DIO0ToDIO7Reg, DIO1Bit); // Procedure : AaeonSetOutputLevel // Input : Example, Set Digital I/O Pin 1...
  • Page 85 ************************************************************************************ Boolean AaeonReadPinStatus(byte OptionReg, byte BitNum){ Byte TempByte; TempByte = ECBRAMReadByte(BRAMFnData1Reg, OptionReg); If (TempByte & BitNum == 0) Return 0; Return 1; VOID AaeonSetOutputLevel(byte OptionReg, byte BitNum, byte Value){ Byte TempByte; TempByte = ECBRAMReadByte(BRAMFnData1Reg, OptionReg); TempByte |= (Value << BitNum); ECBRAMWriteByte(OptionReg, BitNum, Value);...
  • Page 86 ************************************************************************************ VOID ECBRAMWriteByte(byte OPReg, byte OPBit, byte Value){ IOWriteByte(EcBRAMIndex, 0x10); IOWriteByte(EcBRAMData, BRAMLDNReg); IOWriteByte(EcBRAMIndex, 0x11); IOWriteByte(EcBRAMData, BRAMFnDataReg); IOWriteByte(EcBRAMIndex, 0x13 + OPReg); IOWriteByte(EcBRAMData, Value); IOWriteByte(EcBRAMIndex, 0x12); IOWriteByte(EcBRAMData, 0x30); //Write start Byte ECBRAMReadByte(byte FnDataReg, byte OPReg){ IOWriteByte(EcBRAMIndex, 0x10); IOWriteByte(EcBRAMData, BRAMLDNReg); IOWriteByte(EcBRAMIndex, 0x11); IOWriteByte(EcBRAMData, FnDataReg); IOWriteByte(EcBRAMIndex, 0x12);...