Asus AAEON FWS-7831 User Manual
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Asus AAEON FWS-7831 User Manual

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FWS-7831
Network Appliance
User's Manual 1
Ed
st
Last Updated: June 11, 2019

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Summary of Contents for Asus AAEON FWS-7831

  • Page 1 FWS-7831 Network Appliance User’s Manual 1 Last Updated: June 11, 2019...
  • Page 2 Copyright Notice This document is copyrighted, 2019. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of the original manufacturer.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp.  Intel, Pentium, Celeron, and Xeon are registered trademarks of Intel Corporation  Core, Atom are trademarks of Intel Corporation ...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity FWS-7831  If any of these items are missing or damaged, please contact your distributor or sales representative immediately. Preface...
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document.
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. All cables and adapters supplied by AAEON are certified and in accordance with the material safety laws and regulations of the country of sale.
  • Page 7 As most electronic components are sensitive to static electrical charge, be sure to ground yourself to prevent static charge when installing the internal components. Use a grounding wrist strap and contain all electronic components in any static-shielded containers. If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii.
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) Preface...
  • Page 10 China RoHS Requirement (EN) Preface...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Chapter 2 – Hardware Information ..................5 Dimensions ....................... 6 Jumpers and Connectors ..................9 List of Jumpers ......................11 2.3.1 RTC Reset (JP1) .................... 11 2.3.2 Auto Power Button (JP2) ................11 List of Connectors ....................
  • Page 12 3.4.2 Advanced: PCH-FW Configuration ............38 3.4.2.1 Firmware Update Configuration ............ 39 3.4.3 Advanced: Trusted Computing ............... 40 3.4.4 Advanced: SATA And RST Configuration ..........41 3.4.5 Advanced: Hardware Monitor ..............42 3.4.5.1 Smart Fan Function................43 3.4.6 Advanced: SIO Configuration ..............45 3.4.6.1 Serial Port Configuration ..............
  • Page 13 I/O Address Map ....................75 Memory Address Map ..................77 IRQ Mapping Chart ....................78 Appendix C – Standard LAN Bypass Platform Setting ............79 Status LED ....................... 80 C.1.1 Status LED Configuration ................. 80 C.1.2 Sample Code ....................81 LAN Bypass ......................

  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 15: Specifications

    Specifications Platform Form Factor 1U Rackmount Network Platform Processor Intel® Xeon® E-2100 family (C246 Chipset) Intel® Core™/ Celeron® (H310 Chipset) Chipset Intel®C246/H310 System Memory 2x DDR4 SO DIMM/ECC Up to 32GB DDR4 1600/1866/2133 SO DIMM/ECC Up to 32GB 260-pin DIMM x 2 Network Ethernet Intel®...
  • Page 16 Storage HDDs Internal 2.5” HDD bay x 2 or ( 3.5” HDD bay x 1 can’t use with NIM Optional ) CF/CFast/mSATA mSATA Expansion / Internal Interface NIM Slot x 1 PCIe slot Mini-Card x 1 (PCIe[x1]+mSATA) Mini-PCIe slot Keyboard and Mouse USB 3.0 x 2 Universal Serial Bus Miscellaneous...
  • Page 17 Environmental Parameters and Dimension Power Requirement 220W ATX PSU Operation Temp. 32°F ~ 104°F (0°C ~ 40°C) Storage Temp. -4°F ~ 140°F (-20°C ~ 60°C) Operating Humidity 10%~80% relative humidity, non-condensing Storage Humidity 10%~80% @40°C; non-condensing Vibration 0.5 g rms/ 5 ~ 500Hz / operation (2.5” Hard Disk Drive) 1.5 g rms/ 5 ~ 500Hz / non operation Shock...

  • Page 18: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 19: Dimensions

    Dimensions System Chapter 2 – Hardware Information...
  • Page 20 Component Side Chapter 2 – Hardware Information...
  • Page 21 Solder Side Chapter 2 – Hardware Information...

  • Page 22: Jumpers And Connectors

    Jumpers and Connectors Component Side Chapter 2 – Hardware Information...
  • Page 23 Solder Side Chapter 2 – Hardware Information...

  • Page 24: List Of Jumpers

    List of Jumpers The FWS-7831 system board is configured with a number of jumpers which can be configured for your application. This section details those jumpers and their settings. Label Function RTC Reset Auto Power Button 2.3.1 RTC Reset (JP1) Normal (Default) Clear CMOS 2.3.2...

  • Page 25: List Of Connectors

    List of Connectors The FWS-7831 system board is configured with a number of connectors which can be used for configuring your system and connecting with external modules. This section details those connectors and settings. Label Function CN4 & CN5 HDD Power Connector mSATA SOCKET CN17 Digital I/O...

  • Page 26: Hdd Power Connector (Cn4 & Cn5)

    2.4.1 HDD Power Connector (CN4 & CN5) Signal Signal Type +12V 2.4.2 Digital I/O (CN17) Signal Signal Type DIO0 Input / Output DIO1 Input / Output DIO2 Input / Output DIO3 Input / Output DIO4 Input / Output DIO5 Input / Output DIO6 Input / Output DIO7...

  • Page 27: Lcm Connector (Cn18)

    2.4.3 LCM Connector (CN18) Signal Signal Type LCMGND LCMVCC SLIN# Output INIT# Output AFD# Output DATA0 Input / Output DATA1 Input / Output DATA2 Input / Output DATA3 Input / Output DATA4 Input / Output DATA5 Input / Output DATA6 Input / Output DATA7 Input / Output...

  • Page 28: Com Port (Com2)

    2.4.5 COM Port (COM2) RS-232 Signal Signal Type Input Input Output Output Input Output Input Input N.C. 2.4.6 Front Panel Pin Header (FP1) Signal Signal Type Power On Input Button(+) Power On Button(-) Reset Switch (+) Input Reset Switch (-) Power LED(+) POWER Power LED(-)

  • Page 29: Usb 3.0 Port (Usb1)

    2.4.7 USB 3.0 Port (USB1) Signal Signal Type +5V_USB USB3_RX1_DN DIFF USB3_RX1_DP DIFF USB3_TX1_DN DIFF USB3_TX1_DP DIFF USBP_0N DIFF USBP_0P DIFF USBP_1P DIFF USBP_1N DIFF USB3_TX2_DP DIFF USB3_TX2_DN DIFF USB3_RX2_DP DIFF USB3_RX2_DN DIFF +5V_USB Chapter 2 – Hardware Information...

  • Page 30: 3.5" Hard Drive Installation

    3.5” Hard Drive Installation This section details the steps of how to install a 3.5” hard drive for the FWS-7831. Remove the screws securing the top cover, then remove the cover. Install the bracket cushions on the hard drive brackets as shown. Chapter 2 –...
  • Page 31 Install brackets onto hard drive with screws. Chapter 2 – Hardware Information...
  • Page 32 Fasten the assembled hard drive and brackets to the chassis with screws. Connect the SATA cable and power cable to the hard drive and system board. Chapter 2 – Hardware Information...

  • Page 33: Hard Drive Installation

    2.5” Hard Drive Installation This section details the steps of how to install a 2.5” hard drive for the FWS-7831. This section includes steps for installing one or two 2.5” hard drives. Remove the screws securing the top cover, then remove the cover. Install the bracket cushions on the hard drive brackets as shown.
  • Page 34 Install brackets onto hard drive with screws. Repeat Steps 2 & 3 with the second set of brackets if you are installing two hard drives. Attach SATA and power cables to system board as shown for the first hard drive. Chapter 2 –...
  • Page 35 Attach SATA and power cables to system board as shown for the second hard drive (skip this step if only installing one hard drive). Place first hard drive assembly onto installation brackets as shown. Note: Make sure that SATA and power cables are under the hard drive. Chapter 2 –...
  • Page 36 Connect SATA and power cable to first hard drive as shown. Place the second hard drive onto installation brackets as shown. Note: Make sure that SATA and power cables are under the hard drive. Chapter 2 – Hardware Information...
  • Page 37 Connect SATA and power cable to the second hard drive as shown. Chapter 2 – Hardware Information...

  • Page 38: Cpu And Heat Sink Installation

    CPU and Heat Sink Installation This section details the steps of how to install the CPU and heat sink for the FWS-7831. Remove the screws securing the top cover, then remove the cover. Remove the highlighted screw, then remove the fan duct. Chapter 2 –...
  • Page 39 Open the CPU bracket. Chapter 2 – Hardware Information...
  • Page 40 Remove the pin cover and place the CPU into the socket. Use the notches to ensure proper alignment. Note: The CPU should fit into the socket easily. DO NOT force the CPU into the socket. Pushing on the CPU can cause damage to the CPU pins or socket.
  • Page 41 Close the bracket and lock the bracket pole into position. Note: Please ensure you have applied thermal paste according to CPU manufacturer’s guidelines before installing the heat sink. Place the heatsink onto the CPU and fasten the heatsink screws. Make sure the heatsink is aligned with the airflow of the fan.
  • Page 42 Replace the fan cover and secure with the fastening screw. Chapter 2 – Hardware Information...

  • Page 43: Installing Nim

    Installing NIM This section details the steps of how to install NIM modules for the FWS-7831. This applies for new installation, or removal/replacement of modules. Remove the highlighted screw on the chassis bottom. Remove the null module cover or existing module. Chapter 2 –...
  • Page 44 Insert the new module (or null module cover) firmly and secure with the screw. Chapter 2 – Hardware Information...

  • Page 45: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 46: System Test And Initialization

    System Test and Initialization The system uses certain routines to perform testing and initialization during the boot up sequence. If an error, fatal or non-fatal, is encountered, the system will output a few short beeps or an error message. The board can usually continue the boot up sequence with non-fatal errors.

  • Page 47: Ami Bios Setup

    AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press <Del>...

  • Page 48: Setup Submenu: Main

    Setup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 49: Setup Submenu: Advanced

    Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 50: Advanced: Cpu Configuration

    3.4.1 Advanced: CPU Configuration Options Summary Active Processor Optimal Default, Failsafe Default Cores Other Core numbers Number of cores to enable in each processor package. Hyper-Threading Disabled Enabled Optimal Default, Failsafe Default Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and Disabled for other OS (OS not optimized for Hyper-Threading Technology).

  • Page 51: Advanced: Pch-Fw Configuration

    3.4.2 Advanced: PCH-FW Configuration Chapter 3 – AMI BIOS Setup...

  • Page 52: Firmware Update Configuration

    3.4.2.1 Firmware Update Configuration Options Summary Me FW Image Disabled Optimal Default, Failsafe Default Re-Flash Enabled Enable/Disable Me FW Image Re-Flash function. Local FW Update Disabled Enabled Optimal Default, Failsafe Default Options for Local FW Update function. Chapter 3 – AMI BIOS Setup...

  • Page 53: Advanced: Trusted Computing

    3.4.3 Advanced: Trusted Computing Options Summary Security Device Disabled Support Enabled Optimal Default, Failsafe Default Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. TPM State Disabled Enabled Optimal Default, Failsafe Default...

  • Page 54: Advanced: Sata And Rst Configuration

    3.4.4 Advanced: SATA And RST Configuration Options Summary SATA Controller(s) Enabled Optimal Default, Failsafe Default Disabled Enable/Disable SATA Device. SATA Mode AHCI Optimal Default, Failsafe Default Selection Intel RST Premium With Intel Optane System Acceleration Determines how SATA controller(s) operate. Hot Plug Disabled Optimal Default, Failsafe Default...

  • Page 55: Advanced: Hardware Monitor

    3.4.5 Advanced: Hardware Monitor Chapter 3 – AMI BIOS Setup...

  • Page 56: Smart Fan Function

    3.4.5.1 Smart Fan Function Options Summary CPU Fan 1 / 2 Smart Disabled Control Enabled Optimal Default, Failsafe Default Enable/Disable CPU Fan Smart Control Enabled: FAN operates in accordance with user settings Disabled: FAN always operates at full speed FAN Control Mode Manual Mode Automatic Mode Optimal Default, Failsafe Default...
  • Page 57 Options Summary Off Control Optimal Default, Failsafe Default Temperature Temperature Value for FAN Off Note: Some fans have the minimum speed even if the PWM value is 0 Start Control Optimal Default, Failsafe Default Temperature Temperature Value for FAN Start Full Speed Optimal Default, Failsafe Default Temperature...

  • Page 58: Advanced: Sio Configuration

    3.4.6 Advanced: SIO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 59: Serial Port Configuration

    3.4.6.1 Serial Port Configuration Chapter 3 – AMI BIOS Setup...
  • Page 60 Options Summary Use This Device Disabled Enabled Optimal Default, Failsafe Default Enable/Disable this Logical Device Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=3F8; IRQ=4; IO=2F8; IRQ=3; Allow user to change Device’s Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 61: Parallel Port Configuration

    3.4.6.2 Parallel Port Configuration Options Summary Use This Device Disabled Enabled Optimal Default, Failsafe Default Enable/Disable this Logical Device Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=378; IRQ=5; IO=378; IRQ=5,6,7,9,10,11,12; IO=278; IRQ=5,6,7,9,10,11,12; IO=3BC; IRQ=5,6,7,9,10,11,12; Allow user to change Device’s Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 62: Advanced: Serial Port Console Redirection

    3.4.7 Advanced: Serial Port Console Redirection Options Summary COM0 Console Disabled Redirection Enabled Optimal Default, Failsafe Default Enable or Disable Console Redirection Serial Port for Out-of-Band Management/ Windows Emergency Management Services (EMS) Console Redirection Disabled Optimal Default, Failsafe Default Enabled Enable or Disable Console Redirection.

  • Page 63: Com0 Console Redirection

    3.4.7.1 COM0 Console Redirection Options Summary Terminal Type VT100 VY100+ Optimal Default, Failsafe Default VT-UTF8 ANSI Emulation : ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes. Bits per second 9600 19200...
  • Page 64 Options Summary Data Bits Optimal Default, Failsafe Default Data Bits Parity None Optimal Default, Failsafe Default Even Mark Space A Parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the number of 1’s in the data bits is even. Odd: parity bit is 0 if the number of 1’s in the data bits is odd.

  • Page 65: Legacy Console Redirection Settings

    3.4.7.2 Legacy Console Redirection Settings Options Summary Redirection COM COM0 Optimal Default, Failsafe Default Port Select a COM port to display redirection of Legacy OS and Legacy OPROM Messages. Resolution 80x24 Optimal Default, Failsafe Default 80x25 On Legacy OS, the Number of Rows and Columns supported redirection. Redirection After Always Enable Optimal Default, Failsafe Default...

  • Page 66: Advanced: Power Management

    3.4.8 Advanced: Power Management Options Summary Power Mode ATX Type Optimal Default, Failsafe Default AT Type Select power supply mode. Restore AC Power Last State Optimal Default, Failsafe Default Loss Always On Always Off Select power state when power is re-applied after a power failure. RTC wake system Disabled Optimal Default, Failsafe Default...

  • Page 67: Advanced: Digital Io Port Configuration

    3.4.9 Advanced: Digital IO Port Configuration Options Summary DIO Port1~4 Output Optimal Default, Failsafe Default Input Set DIO as Input or Output Output Level High Optimal Default, Failsafe Default Set output level when DIO pin is output DIO Port5~8 Output Input Optimal Default, Failsafe Default Set DIO as Input or Output...

  • Page 68: Advanced: Lan Bypass Configuration

    3.4.10 Advanced: LAN Bypass Configuration Options Summary Configure LAN LED OFF Optimal Default, Failsafe Default Bypass Status LED RED LED ON RED LED BLINK RED LED FAST BLINK GREEN LED ON GREEN LED BLINK GREEN LED FAST BLINK LAN Bypass Status LED Mode for Power-on ByPass PassTru Optimal Default, Failsafe Default...

  • Page 69: Advanced: Network Stack Configuration

    3.4.11 Advanced: Network Stack Configuration Options Summary Network Stack Disabled Optimal Default, Failsafe Default Enabled Enable/Disable UEFI Network Stack Ipv4 PXE Support Disabled Enabled Optimal Default, Failsafe Default Enable/Disable IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available.

  • Page 70: Setup Submenu: Chipset

    Setup submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 71: Chipset: System Agent (Sa) Configuration

    3.5.1 Chipset: System Agent (SA) Configuration Options Summary VT-d Disabled Enabled Optimal Default, Failsafe Default VT-d capability Primary Display Auto Optimal Default, Failsafe Default IGFX Select which of IGFX/PEG/PCI Graphics device should be Primary Display Or select SG for Switchable Gfx. Chapter 3 –...

  • Page 72: Setup Submenu: Security

    Setup submenu: Security Change User/Administrator Password You can set an Administrator Password or User Password. An Administrator Password must be set before you can set a User Password. The password will be required during boot up, or when the user enters the Setup utility. A User Password does not provide access to many of the features in the Setup utility.

  • Page 73: Security: Secure Boot

    3.6.1 Security: Secure Boot Options Summary Secure Boot Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled, and the System is in User mode. The mode change requires platform reset Secure Boot Mode Standard Custom Optimal Default, Failsafe Default...

  • Page 74: Secure Boot: Key Management

    3.6.1.1 Secure Boot: Key Management Options Summary Factory Key Disabled Optimal Default, Failsafe Default Provision Enabled Install factory default Secure Boot keys after the platform reset and while the System is in Setup mode Restore Factory Press ‘Yes’ to restore factory default Keys keys Force System to User Mode.
  • Page 75 Options Summary Enroll Efi Image Select a File system to enroll Efi image into Authorized Signature Database. Allow the image to run in Secure Boot mode. Enroll SHA256 Hash certificate of a PE image into Authorized Signature Database (db) Remove 'UEFI CA' from DB Device Guard ready system must not list 'Microsoft UEFI CA' Certificate in Authorized Signature database (db)

  • Page 76: Setup Submenu: Boot

    Setup submenu: Boot Options Summary Quiet Boot Disabled Enabled Optimal Default, Failsafe Default Enable / Disable Quiet Boot option. CSM Support Disabled Optimal Default, Failsafe Default Enabled Enable/Disable CSM Support. Launch PXE ROM Do not launch Optimal Default, Failsafe Default UEFI Legacy Controls the execution of UEFI and Legacy Network OpROM...

  • Page 77: Setup Submenu: Save & Exit

    Setup submenu: Save & Exit Chapter 3 – AMI BIOS Setup...

  • Page 78: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 79: Drivers Download And Installation

    Drivers Download and Installation Drivers for the FWS-7831 can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/rackmount-network-appliance-fws-7831 Download the driver(s) you need and follow the steps below to install them. Step 1 – LAN Drivers Open the Step 1 - LAN folder.

  • Page 80: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...

  • Page 81: Watchdog Timer Initial Program

    Watchdog Timer Initial Program Table 1 : SuperIO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2 : Watchdog relative register table Register BitNum Value...
  • Page 82 ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Watch Dog relative definition (Please reference to Table 2) #define byte TimerLDN //This parameter is represented from Note3 #define byte TimerReg //This parameter is represented from Note4 #define byte TimerVal // This parameter is represented from Note24...
  • Page 83 ************************************************************************************ Main VOID // Procedure : AaeonWDTConfig // (byte)Timer : Time of WDT timer.(0x00~0xFF) // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. AaeonWDTEnable(); ************************************************************************************ Appendix A – Watchdog Timer Programming...
  • Page 84 ************************************************************************************ // Procedure : AaeonWDTEnable AaeonWDTEnable () VOID WDTEnableDisable( EnableLDN, EnableReg, EnableBit, 1 // Procedure : AaeonWDTConfig AaeonWDTConfig () VOID // Disable WDT counting WDTEnableDisable( EnableLDN, EnableReg, EnableBit, 0 // Clear Watchdog Timeout Status WDTClearTimeoutStatus(); // WDT relative parameter setting WDTParameterSetting();...
  • Page 85 ************************************************************************************ SIOEnterMBPnPMode() VOID Switch(SIOIndex){ Case 0x2E: IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x01); IOWriteByte(SIOIndex, 0x55); IOWriteByte(SIOIndex, 0x55); Break; Case 0x4E: IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x01); IOWriteByte(SIOIndex, 0x55); IOWriteByte(SIOIndex, 0xAA); Break; SIOExitMBPnPMode() VOID IOWriteByte(SIOIndex, 0x02); IOWriteByte(SIOData, 0x02); SIOSelectLDN(byte LDN) VOID IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN);...
  • Page 86 ************************************************************************************ SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value) VOID Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData); TmpValue &= ~(1 << BitNum); TmpValue |= (Value << BitNum); IOWriteByte(SIOData, TmpValue); SIOExitMBPnPMode(); SIOByteSet(byte LDN, byte Register, byte Value) VOID SIOEnterMBPnPMode(); SIOSelectLDN(LDN);...

  • Page 87: Appendix B - I/O Information

    Appendix B Appendix B - I/O Information...

  • Page 88: I/O Address Map

    I/O Address Map Appendix B – I/O Information...
  • Page 89 Appendix B – I/O Information...

  • Page 90: Memory Address Map

    Memory Address Map Appendix B – I/O Information...

  • Page 91: Irq Mapping Chart

    IRQ Mapping Chart Appendix B – I/O Information...

  • Page 92: Appendix C - Standard Lan Bypass Platform Setting

    Appendix C Appendix C – Standard LAN Bypass Platform Setting...

  • Page 93: Status Led

    Status LED The FWS-7831 features a Status LED indicator which can be configured using the AAEON SDK. The Status LED can be programed to indicate different system statuses. This section provides information on how to program and configure the Status LED. C.1.1 Status LED Configuration Table 1 : Truth Table of Status LED...

  • Page 94: Sample Code

    C.1.2 Sample Code ********************************************************************************************** #define Byte CPLD_SLAVE_ADDRESS //This parameter is represented from Note1 #define Byte OFFSET //This parameter is represented from Note2 ********************************************************************************************** bData = aaeonSmbusReadByte(CPLD_SLAVE_ADDRESS, OFFSET); switch( LED_FLAG) case 0: //LED Off //BIT2=0, BIT1=0, BIT0=0 bData = bData & 0xF8; break;...
  • Page 95 //BIT2=1, BIT1=1, BIT0=1 bData = (bData & 0xF8) | 0x07; break; case 5: //Green LED Blink //BIT2=1, BIT1=0, BIT0=1 bData = (bData & 0xF8) | 0x05; break; case 6: //Green LED Fast Blink //BIT2=1, BIT1=1, BIT0=0 bData = (bData & 0xF8) | 0x06; break;...

  • Page 96: Lan Bypass

    LAN Bypass The FWS-7831 provides a LAN Bypass kit, allowing uninterrupted network traffic even if a single in-line appliance is shut down or hangs. This section details how to configure and program the LAN Bypass. C.2.1 LAN Bypass Configuration Table 1 : ID Select table of LAN kit LAN_ID3 LAN_ID2 LAN_ID1...
  • Page 97 Table 3 : LAN Bypass relative register mapping table CPLD Slave Address 0x90 (Note1) Attribute Offset(SMBUS) BitNum Value LAN_ID3 0x01(Note2) (Table 1) LAN_ID2 0x01(Note2) (Table 1) LAN_ID1 0x01(Note2) (Table 1) LAN_ID0 0x01(Note2) (Table 1) PWR_ON 0x01(Note2) (Table 2) PWR_OFF 0x01(Note2) (Table 2) WDT_EN 0x01(Note2)

  • Page 98: Sample Code

    C.2.2 Sample Code ********************************************************************************************** #define Byte CPLD_SLAVE_ADDRESS //This parameter is represented from Note1 #define Byte OFFSET //This parameter is represented from Note2 ********************************************************************************************** // Select Lan Pair BYTE bLanSel = LAN_PAIR; BYTE bData = SmbusReadByte(CPLD_SLAVE_ADDRESS, OFFSET); // Set Reg01h bit3 if(bLanSel &...
  • Page 99 bData = bData | 0x20; // WDT Action (Reg01h bit4) if(SET_WDT_RESET) // Reset bData = bData & 0xEF; else // Bypass bData = bData | 0x10; SmbusWriteByte(CPLD_SLAVE_ADDRESS, OFFSET, bData); // Apply Settings (Reg01h bit7) bData = SmbusReadByte(CPLD_SLAVE_ADDRESS, OFFSET); SmbusWriteByte(CPLD_SLAVE_ADDRESS, OFFSET, bData & 0x7F); Sleep(500);...

  • Page 100: Software Reset Button (General Propose Input)

    Software Reset Button (General Propose Input) The FWS-7831 provides a general purpose input button which can be configured by the AAEON SDK. This section details how to configure and program this feature. C.3.1 Software Reset Button Configuration Table 2 : Software Reset Button register table Function Description Reading this register returns the pin level status which is...

  • Page 101: Sample Code

    C.3.2 Sample Code ************************************************************************************ #define Word BTN_STS //This parameter is represented from Note1 #define Byte BTN_STS_R //This parameter is represented from Note2 ************************************************************************************ GET_Value (Word IoAddr, Byte BitNum,Byte Value) Byte BYTE TmpValue; TmpValue = inportb (IoAddr); return (TmpValue & (1 << BitNum)) ************************************************************************************ Main VOID...

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