Section 7. Memory; Overview / Description; Dimms Supported - Dell POWEREDGE R710 Series Technical Manualbook

Dell™ PowerEdge™ R710 Technical Guidebook
CPU Power Voltage Regulation Modules (EVRD 11.1)
Voltage regulation to the 5500 series 2S processor (Nehalem EP) is provided by EVRD (Enterprise
Voltage Regulator-Down). EVRDs are embedded on the planar. CPU core voltage is not shared between
processors. EVRDs support static phase shedding and power management via the PMBus.

sectiOn 7. memORy

a. Overview / Description
The PowerEdge R710 utilizes DDR3 memory providing a high performance, high-speed memory
interface capable of low latency response and high throughput. The PE R710 supports Registered
ECC DDR3 DIMMs (RDIMM) or Unbuffered ECC DDR3 DIMMs (UDIMM).
Key features of the PowerEdge R710 memory system include:
• R egistered (RDIMM) and Unbuffered (UDIMM) ECC DDR3 technology
• E ach channel carries 64 data and eight ECC bits support for up to 96GB of RDIMM memory
(with twelve 8GB RDIMMs)
• S upport for up to 24GB of UDIMM memory (with twelve 2GB UDIMMs)
• S upport for 1066/1333MHz single- and dual-rank DIMMs
• S upport for 1066MHz quad rank DIMMs
• Single DIMM configuration only with DIMM in socket A1
• S upport ODT (On Die Termination) Clock gating (CKE) to conserve power when DIMMs
are not accessed
• D IMMs enter a low-power self-refresh mode
• I C access to SPD EEPROM for access to RDIMM thermal sensors
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• S ingle Bit Error Correction
• S DDC (Single Device Data Correction – x4 or x8 devices)
• S upport for Closed Loop
• T hermal Management on RDIMMs and UDIMMs
• Multi Bit Error Detection Support for Memory Optimized Mode
• S upport for Advanced ECC mode
• S upport for Memory Mirroring
b. Dimms supported
The DDR3 memory interface consists of three channels, with up to two RDIMMs or UDIMMs per
channel for single-/dual-rank and up to two RDIMMs per channel for quad rank. The interface uses 2GB,
4GB, or 8GB RDIMMs. 1GB or 2GB UDIMMs are also supported. The memory mode is dependent on how
the memory is populated in the system:
Three channels per CPU populated identically:
• T ypically, the system will be set to run in Memory Optimized (Independent Channel) mode in
this configuration. This mode offers the most DIMM population flexibility and system memory
capacity, but offers the least number of RAS (reliability, availability, service) features.
• A ll three channels must be populated identically.
• U sers wanting memory sparing must also populate the DIMMs in this method, but one channel
is the spare and is not accessible as system memory until it is brought online to replace a failing
channel.
• T he first two channels per CPU populated identically with the third channel unused
• T ypically, two channels operate in Advanced ECC (Lockstep) mode with each other by
having the cache line split across both channels. This mode provides improved RAS
features (SDDC support for x8-based memory).
• F or Memory Mirroring, two channels operate as mirrors of each other — writes go to
both channels and reads alternate between the two channels.
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