PLL CIRCUIT BLOCK DIAGRAM
MAIN LOOP
۱
۱
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| [
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-
۷۷۷۸۸۱4
fy: 70.9515—
100.4515 MHz
1st LO to
MAIN UNIT
№
1 |
a- m a a
a- a
oo
aa ae
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| но: 62.05--
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6256199 MHz
i
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ሀልፐል
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E=
ыды
2 mme me imm nm mm num] ли!
BUFFER
SUB LOOP
Q34
REFERENCE
OSCILLATOR
x2 በ
2nd LO
61.44 MHz
30.72 MHz
Fig. 6
4-4 LOGIC CIRCUITS
4-4-1 BAND SELECTION DATA (PLL UNIT)
To select the correct bandpass filter, the low-pass filter and
VCOs on the MAIN and PLL UNITS, the CPU outputs the
following data.
R29~R40 and D29~D35 convert the "ВО"--"В?" signals
into a band voltage (0— 7.5 V) for external equipment.
11.0—14.999
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