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IXYS Z8 Encore! F0830 Series Product Specification

High-performance 8-bit microcontrollers
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High-Performance 8-Bit Microcontrollers
®
Z8 Encore!
F0830 Series
Product Specification
PS025112-1011
®
Copyright ©2011 Zilog
, Inc. All rights reserved.
www.zilog.com

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Summary of Contents for IXYS Z8 Encore! F0830 Series

  • Page 1 High-Performance 8-Bit Microcontrollers ® Z8 Encore! F0830 Series Product Specification PS025112-1011 ® Copyright ©2011 Zilog , Inc. All rights reserved. www.zilog.com...
  • Page 2 ® Z8 Encore! F0830 Series Product Specification DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. Warning: LIFE SUPPORT POLICY ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.

  • Page 3: Revision History

    ® Z8 Encore! F0830 Series Product Specification Revision History Each instance in this document’s revision history reflects a change from its previous edi- tion. For more details, refer to the corresponding page(s) or appropriate links furnished in the table below. Revision Page Date...

  • Page 4: Table Of Contents

    ® Z8 Encore! F0830 Series Product Specification Table of Contents Revision History ............iii List of Figures .
  • Page 5 ® Z8 Encore! F0830 Series Product Specification Voltage Brown-Out Reset ..........24 Watchdog Timer Reset .
  • Page 6 ® Z8 Encore! F0830 Series Product Specification Master Interrupt Enable ..........55 Interrupt Vectors and Priority .
  • Page 7 ® Z8 Encore! F0830 Series Product Specification Calibration and Compensation ........101 ADC Control Register Definitions .
  • Page 8 ® Z8 Encore! F0830 Series Product Specification viii Operation ............134 NVDS Code Interface .
  • Page 9 ® Z8 Encore! F0830 Series Product Specification Electrical Characteristics ........... 184 Absolute Maximum Ratings .

  • Page 10: List Of Figures

    List of Figures Figure 1. Z8 Encore! F0830 Series Block Diagram ......3 Figure 2.
  • Page 11 ® Z8 Encore! F0830 Series Product Specification Figure 31. ICC Versus System Clock Frequency (HALT Mode) ....187 Figure 32. ICC Versus System Clock Frequency (NORMAL Mode) ... . 188 Figure 33.
  • Page 12 Acronyms and Expansions ........6 Table 3. Z8 Encore! F0830 Series Package Options ......7 Table 4.
  • Page 13 Comparator Control Register (CMP0) ......107 Table 69. Z8 Encore! F0830 Series Flash Memory Configuration ....108 PS025112-1011...
  • Page 14 ® Z8 Encore! F0830 Series Product Specification Table 70. Z8F083 Flash Memory Area Map ....... 112 Table 71.
  • Page 15 ® Z8 Encore! F0830 Series Product Specification Table 106. Bit Manipulation Instructions ........167 Table 107.
  • Page 16 ® Z8 Encore! F0830 Series Product Specification Table 141. Timer 1 Reload Low Byte Register (T1RL) ..... . . 211 Table 142.
  • Page 17 ® Z8 Encore! F0830 Series Product Specification xvii Table 177. Port C GPIO Address Register (PCADDR) ..... . . 224 Table 178.

  • Page 18: Overview

    Zilog’s Z8 Encore! MCU family of products are the first in a line of Zilog microcontroller products based on the 8-bit eZ8 CPU. The Z8 Encore! F0830 Series products expand on Zilog’s extensive line of 8-bit microcontrollers. The Flash in-circuit programming capabil- ity allows for faster development time and program changes in the field.

  • Page 19: Part Selection Guide

    Table 1 lists the basic features available for each device within the Z8 Encore! F0830 Series product line. See the Ordering Information chapter on page 200 for details. Table 1. Z8 Encore! F0830 Series Family Part Selection Guide Part Flash NVDS...

  • Page 20: Block Diagram

    ® Z8 Encore! F0830 Series Product Specification Block Diagram Figure 1 displays a block diagram of the Z8 Encore! F0830 Series architecture System Oscillator XTAL/RC Clock Control Oscillator Internal Precision Oscillator Low Power On-Chip RC Oscillator Debugger POR/VBO & Reset...

  • Page 21: Cpu And Peripheral Overview

    (UM0128), which is available for download on www.zilog.com. General Purpose Input/Output The Z8 Encore! F0830 Series features up to 25 port pins (Ports A–D) for general-purpose input/output (GPIO). The number of GPIO pins available is a function of package. Each pin is individually programmable.

  • Page 22: Nonvolatile Data Storage

    OUTPUT Modes. Interrupt Controller The Z8 Encore! F0830 Series products support seventeen interrupt sources with sixteen interrupt vectors: up to five internal peripheral interrupts and up to twelve GPIO inter- rupts. These interrupts have three levels of programmable interrupt priority.

  • Page 23: Reset Controller

    Product Specification Reset Controller The Z8 Encore! F0830 Series products are reset using any one of the following: the RESET pin, Power-On Reset, Watchdog Timer (WDT) time-out, STOP Mode exit or Volt- age Brown-Out (VBO) warning signal. The RESET pin is bidirectional; i.e., it functions as a reset source as well as a reset indicator.

  • Page 24: Pin Description

    Product Specification Pin Description The Z8 Encore! F0830 Series products are available in a variety of package styles and pin configurations. This chapter describes the signals and the pin configurations for each of the package styles. For information about the physical package specifications, see the Packaging chapter on page 199.

  • Page 25: Figure 2. Z8F0830 Series In 20-Pin Soic, Ssop, Pdip Package

    ® Z8 Encore! F0830 Series Product Specification The analog supply pins (AV and AV ) are also not available on these parts and are replaced by PB6 and PB7. At reset, by default, all pins of Port A, B and C are in Input state. The alternate functional- ity is also disabled, so the pins function as general purpose input ports until programmed otherwise.

  • Page 26: Figure 4. Z8F0830 Series In 20-Pin Qfn Package

    ® Z8 Encore! F0830 Series Product Specification PC3/COUT/LED PA7/T1OUT PA7/T1OUT   PB0/ANA0 PA6/T1IN/T1OUT PA6/T1IN/T1OUT   PB1/ANA1 PA5 PA5   20-Pin QFN PB2/ANA2 PA4 PA4   PB3/CLKIN/ANA3 Figure 4. Z8F0830 Series in 20-Pin QFN Package PS025112-1011 Pin Configurations...

  • Page 27: Figure 5. Z8F0830 Series In 28-Pin Qfn Package

    ® Z8 Encore! F0830 Series Product Specification PC3/COUT/LED PA7/T1OUT PB0/ANA0 PC5/LED PB1/ANA1 PC4/LED PB2/ANA2 PA6/T1IN/T1OUT 28-Pin QFN PB4/ANA7 PB5/V PB3/CLKIN/ANA3 Figure 5. Z8F0830 Series in 28-Pin QFN Package PS025112-1011 Pin Configurations...

  • Page 28: Signal Descriptions

    ® Z8 Encore! F0830 Series Product Specification Signal Descriptions Table 4 describes the Z8 Encore! F0830 Series signals. See the Pin Configurations section on page 7 to determine the signals available for each specific package style. Table 4. Signal Descriptions...
  • Page 29 ® Z8 Encore! F0830 Series Product Specification Table 4. Signal Descriptions (Continued) Signal Mnemonic Description Oscillators External crystal input. This is the input pin to the crystal oscillator. A crystal can be connected between it and the XOUT pin to form the oscillator. In addition, this pin is used with external RC networks or external clock drivers to provide the system clock.

  • Page 30: Pin Characteristics

    ® Z8 Encore! F0830 Series Product Specification Pin Characteristics Table 5 provides detailed characteristics of each pin available on the Z8 Encore! F0830 Series 20- and 28-pin devices. Data in Table 5 are sorted alphabetically by the pin symbol mnemonic. Table 5.

  • Page 31: Address Space

    ® Z8 Encore! F0830 Series Product Specification Address Space The eZ8 CPU can access the following three distinct address spaces: The register file addresses access for the general purpose registers and the eZ8 CPU, • peripheral and general purpose I/O port control registers The program memory addresses access for all of the memory locations having execut- •...

  • Page 32: Program Memory

    . Writing to these unimplemented program memory addresses produces no effect. Table 6 shows a program memory map for the Z8 Encore! F0830 Series products. Table 6. Z8 Encore! F0830 Series Program Memory Maps Program Memory Address (Hex) Function Z8F0830 and Z8F0831 Products 0000–0001...

  • Page 33: Data Memory

    F0830 Series Product Specification Data Memory The Z8 Encore! F0830 Series does not use the eZ8 CPU’s 64 KB data memory address space. Flash Information Area Table 7 maps the Z8 Encore! F0830 Series Flash information area. The 128-byte informa- tion area is accessed, by setting bit 7 of the Flash Page Select Register to 1.

  • Page 34: Register Map

    Table 8 provides an address map of the Z8 Encore! F0830 Series register file. Not all devices and package styles in the Z8 Encore! F0830 Series support the ADC or all of the GPIO ports. Consider registers for unimplemented peripherals as reserved.
  • Page 35 ® Z8 Encore! F0830 Series Product Specification Table 8. Register File Address Map (Continued) Address (Hex) Register Description Mnemonic Reset (Hex) Page No. Analog-to-Digital Converter (ADC, cont’d) ADC data low bits ADCD_L ADC sample settling time ADCSST ADC sample time ADCST Reserved —...
  • Page 36 ® Z8 Encore! F0830 Series Product Specification Table 8. Register File Address Map (Continued) Address (Hex) Register Description Mnemonic Reset (Hex) Page No. Interrupt Controller (cont’d) Shared interrupt select IRQSS Interrupt control IRQCTL GPIO Port A Port A address PAADDR Port A control PACTL Port A input data...
  • Page 37 ® Z8 Encore! F0830 Series Product Specification Table 8. Register File Address Map (Continued) Address (Hex) Register Description Mnemonic Reset (Hex) Page No. Trim Bit Control Trim bit address TRMADR Trim data TRMDR Flash Memory Controller Flash control FCTL Flash status FSTAT Flash page select Flash sector protect...

  • Page 38: Reset And Stop Mode Recovery

    F0830 Series Product Specification Reset and Stop Mode Recovery The reset controller in the Z8 Encore! F0830 Series controls RESET and Stop Mode Recovery operations. In a typical operation, the following events can cause a reset: Power-On Reset (POR) •...

  • Page 39: Table 9. Reset And Stop Mode Recovery Characteristics And Latency

    OSC_CTL registers During a system RESET or Stop Mode Recovery, the Z8 Encore! F0830 Series device is held in reset for about 66 cycles of the Internal Precision Oscillator. If the crystal oscillator is enabled in the Flash option bits, the reset period is increased to about 5000 IPO cycles.

  • Page 40: Reset Sources

    POR counter has timed out. If the crystal oscillator is enabled by the option bits, the time- out is longer. After the Z8 Encore! F0830 Series device exits the Power-On Reset state, the eZ8 CPU fetches the reset vector. Following the Power-On Reset, the POR status bit in the Reset Status (RSTSTAT) Register is set to 1.

  • Page 41: Voltage Brown-Out Reset

    Figure 6. Power-On Reset Operation Voltage Brown-Out Reset The devices in the Z8 Encore! F0830 Series provide low Voltage Brown-Out (VBO) pro- tection. The VBO circuit forces the device to the Reset state, when the supply voltage drops below the VBO threshold voltage (unsafe level). While the supply voltage remains...

  • Page 42: Watchdog Timer Reset

    ® Z8 Encore! F0830 Series Product Specification The Voltage Brown-Out circuit can be either enabled or disabled during STOP Mode. Operations during STOP Mode is set by the VBO_AO Flash option bit. See the Flash Option Bits chapter on page 124 for information about configuring VBO_AO. = 3.3V = 3.3V Program...

  • Page 43: External Reset Indicator

    While the RESET input pin is asserted low, the Z8 Encore! F0830 Series devices remain in the Reset state. If the RESET pin is held low beyond the system reset time-out, the device exits the Reset state on the system clock rising edge following RESET pin deasser- tion.

  • Page 44: Stop Mode Recovery Using Wdt Time-Out

    1. If the Watchdog Timer is configured to generate an interrupt upon time-out and the Z8 Encore! F0830 Series device is configured to respond to interrupts, the eZ8 CPU services the WDT interrupt request following the normal Stop Mode Recovery sequence.

  • Page 45: Stop Mode Recovery Using The External Reset Pin

    Stop Mode Recovery Using the External RESET Pin When the Z8 Encore! F0830 Series device is in STOP Mode and the external RESET pin is driven low, a system reset occurs. Because of a glitch filter operating on the RESET pin, the low pulse must be greater than the minimum width specified about 12 ns or it is ignored.

  • Page 46: Table 12. Por Indicator Values

    ® Z8 Encore! F0830 Series Product Specification Table 12. Reset Status Register (RSTSTAT) Field STOP Reserved RESET See Table 13 Address FF0H Description [7] Power-On Reset Indicator This bit is set to 1 if a Power-On Reset event occurs and is reset to 0, if a WDT time-out or Stop Mode Recovery occurs.

  • Page 47: Low-Power Modes

    F0830 Series Product Specification Low-Power Modes The Z8 Encore! F0830 Series products contain power saving features. The highest level of power reduction is provided by the STOP Mode. The next level of power reduction is pro- vided by the HALT Mode.

  • Page 48: Halt Mode

    Peripheral Level Power Control In addition to the STOP and HALT modes, it is possible to disable each peripheral on each of the Z8 Encore! F0830 Series devices. Disabling a given peripheral minimizes its power consumption. Power Control Register Definitions...

  • Page 49: Table 14. Power Control Register 0 (Pwrctl0)

    ® Z8 Encore! F0830 Series Product Specification This register is only reset during a Power-On Reset sequence. Other system reset events do Note: not affect it. Table 14. Power Control Register 0 (PWRCTL0) Field Reserved Reserved Reserved COMP Reserved RESET Address F80H Description...

  • Page 50: General Purpose Input/Output

    Product Specification General Purpose Input/Output The Z8 Encore! F0830 Series products support a maximum of 25 port pins (Ports A–D) for General Purpose Input/Output (GPIO) operations. Each port contains control and data registers. The GPIO control registers determine data direction, open-drain, output drive current, programmable pull-ups, Stop Mode Recovery functionality and alternate pin functions.

  • Page 51: Architecture

    ® Z8 Encore! F0830 Series Product Specification Architecture Figure 8 displays a simplified block diagram of a GPIO port pin. In this figure, the ability to accommodate alternate functions and variable port current drive strength is not dis- played. Port Input Schmitt Trigger Data Register System...

  • Page 52: Direct Led Drive

    ® Z8 Encore! F0830 Series Product Specification PA0 and PA6 contain two different Timer functions, a timer input and a complementary timer output. Both of these functions require the same GPIO configuration, the selection between the two is based on the TIMER mode. For more details, see the Timers chapter on page 68.

  • Page 53: External Clock Setup

    ® Z8 Encore! F0830 Series Product Specification External Clock Setup For systems using an external TTL drive, PB3 is the clock source for 20- and 28-pin devices. In this case, configure PB3 for Alternate function CLKIN. Write to the Oscillator Control Register (see the Oscillator Control Register Definitions section on page 154) to...
  • Page 54 ® Z8 Encore! F0830 Series Product Specification Table 16. Port Alternate Function Mapping (Continued) Alternate Function Port Mnemonic Alternate Function Description Set Register AFS1 Port B Reserved AFS1[0]: 0 ANA0 ADC analog input AFS1[0]: 1 Reserved AFS1[1]: 0 ANA1 ADC analog input AFS1[1]: 1 Reserved AFS1[2]: 0...
  • Page 55 ® Z8 Encore! F0830 Series Product Specification Table 16. Port Alternate Function Mapping (Continued) Alternate Function Port Mnemonic Alternate Function Description Set Register AFS1 Port C Reserved AFS1[0]: 0 ANA4/CINP ADC or comparator input AFS1[0]: 1 Reserved AFS1[1]: 0 ANA5/CINN ADC or comparator input AFS1[1]: 1 Reserved...

  • Page 56: Gpio Interrupts

    ® Z8 Encore! F0830 Series Product Specification GPIO Interrupts Many of the GPIO port pins can be used as interrupt sources. Some port pins can be con- figured to generate an interrupt request on either the rising edge or falling edge of the input pin signal.

  • Page 57: Port A-D Address Registers

    ® Z8 Encore! F0830 Series Product Specification Port A–D Address Registers The Port A–D Address registers select the GPIO port functionality accessible through the Port A–D Control registers. The Port A–D Address and Control registers combine to pro- vide access to all GPIO port controls; see Tables 18 and 19. Table 18.

  • Page 58: Port A-D Control Registers

    ® Z8 Encore! F0830 Series Product Specification Port A–D Control Registers The Port A–D Control registers, shown in Table 20, set the GPIO port operation. The value in the corresponding Port A–D Address Register determines which subregister is read from or written to by a Port A–D Control Register transaction. Table 20.

  • Page 59: Port A-D Alternate Function Subregisters

    ® Z8 Encore! F0830 Series Product Specification Port A–D Alternate Function Subregisters The Port A–D Alternate Function Subregister is accessed through the Port A–D Control Register by writing to the Port A–D Address Register. See Table 22 on page 42. The Port A–D Alternate Function subregisters enable the alternate function selection on pins.

  • Page 60: Table 23. Port A-D Output Control Subregisters (Pxoc)

    ® Z8 Encore! F0830 Series Product Specification Port A–D Output Control Subregisters The Port A–D Output Control Subregister, shown in Table 23, is accessed through the Port A–D Control Register by writing to the Port A–D Address Register. Setting the bits in the Port A–D Output Control subregisters to 1 configures the specified port pins for open- drain operation.

  • Page 61: Table 24. Port A-D High Drive Enable Subregisters (Pxhde)

    ® Z8 Encore! F0830 Series Product Specification Port A–D High Drive Enable Subregisters The Port A–D High Drive Enable Subregister, shown in Table 24, is accessed through the Port A–D Control Register by writing to the Port A–D Address Register. Setting the bits in the Port A–D High Drive Enable subregisters to 1 configures the specified port pins for high-output current drive operation.

  • Page 62: Table 25. Port A-D Stop Mode Recovery Source Enable Subregisters (Pxsmre)

    ® Z8 Encore! F0830 Series Product Specification Port A–D Stop Mode Recovery Source Enable Subregisters The Port A–D Stop Mode Recovery Source Enable Subregister, shown in Table 25, is accessed through the Port A–D Control Register by writing to the Port A–D Address Register.

  • Page 63: Table 26. Port A-D Pull-Up Enable Subregisters (Pxpue)

    ® Z8 Encore! F0830 Series Product Specification Port A–D Pull-up Enable Subregisters The Port A–D Pull-Up Enable Subregister is accessed through the Port A–D Control Reg- ister by writing to the Port A–D Address Register. See Table 26. Setting the bits in the Port A–D Pull-Up Enable subregisters enables a weak internal resistive pull-up on the specified port pins.

  • Page 64: Table 27. Port A-D Alternate Function Set 1 Subregisters (Pxafs1)

    ® Z8 Encore! F0830 Series Product Specification Port A–D Alternate Function Set 1 Subregisters The Port A–D Alternate Function Set 1 Subregister, shown in Table 27, is accessed through the Port A–D Control Register by writing to the Port A–D Address Register. The Alternate Function Set 1 subregisters select the alternate function available at a port pin.

  • Page 65: Table 28. Port A-D Alternate Function Set 2 Subregisters (Pxafs2)

    ® Z8 Encore! F0830 Series Product Specification Port A–D Alternate Function Set 2 Subregisters The Port A–D Alternate Function Set 2 Subregister, shown in Table 28, is accessed through the Port A–D Control Register by writing to the Port A–D Address Register. The Alternate Function Set 2 subregisters select the alternate function available at a port pin.

  • Page 66: Port A-C Input Data Registers

    ® Z8 Encore! F0830 Series Product Specification Port A–C Input Data Registers Reading from the Port A–C Input Data registers, shown in Table 29, return the sampled values from the corresponding port pins. The Port A–C Input Data registers are read-only. The value returned for any unused ports is 0.

  • Page 67: Port A-D Output Data Register

    ® Z8 Encore! F0830 Series Product Specification Port A–D Output Data Register The Port A–D Output Data Register, shown in Table 30, controls the output data to the pins. Table 30. Port A–D Output Data Register (PxOUT) Field POUT7 POUT6 POUT5 POUT4 POUT3...

  • Page 68: Led Drive Enable Register

    ® Z8 Encore! F0830 Series Product Specification LED Drive Enable Register The LED Drive Enable Register, shown in Table 31, activates the controlled current drive. The Alternate Function Register has no control over the LED function; therefore, setting the Alternate Function Register to select the LED function is not required. LEDEN bits [7:0] correspond to Port C bits [7:0], respectively.

  • Page 69: Led Drive Level Low Register

    ® Z8 Encore! F0830 Series Product Specification LED Drive Level Low Register The LED Drive Level Low Register, shown in Table 33, contains two control bits for each Port C pin. These two bits select one of four programmable current drive levels for each Port C pin.

  • Page 70: Interrupt Controller

    ® Z8 Encore! F0830 Series Product Specification Interrupt Controller ® The Interrupt Controller on the Z8 Encore! F0830 Series products prioritize the interrupt requests from the on-chip peripherals and the GPIO port pins. The features of the Interrupt Controller include: Seventeen interrupt sources using sixteen unique interrupt vectors: •...

  • Page 71: Table 34. Trap And Interrupt Vectors In Order Of Priority

    ® Z8 Encore! F0830 Series Product Specification Table 34. Trap and Interrupt Vectors in Order of Priority Program Memory Priority Vector Address Interrupt or Trap Source Highest 0002H Reset (not an interrupt) 0004H Watchdog Timer (see Watchdog Timer chapter) 003AH Primary oscillator fail trap (not an interrupt) 003CH Watchdog Oscillator fail trap (not an interrupt)

  • Page 72: Architecture

    ® Z8 Encore! F0830 Series Product Specification Architecture Figure 9 displays the Interrupt Controller block diagram. High Port Interrupts Priority Vector Priority IRQ Request Medium Priority Internal Interrupts Priority Figure 9. Interrupt Controller Block Diagram Operation This section describes the operational aspects of the following functions. Master Interrupt Enable: see page 55 Interrupt Vectors and...

  • Page 73: Interrupt Vectors And Priority

    ® Z8 Encore! F0830 Series Product Specification Writing 1 to the IRQE bit in the Interrupt Control Register • Interrupts are globally disabled by any of the following actions: Execution of a (disable interrupt) instruction • eZ8 CPU acknowledgement of an interrupt service request from the Interrupt Control- •...

  • Page 74: Software Interrupt Assertion

    ® Z8 Encore! F0830 Series Product Specification LDX r0, IRQ0 AND r0, MASK LDX IRQ0, r0 To avoid missing interrupts, use the coding style in Example 2 to clear bits in the Interrupt Request 0 Register: A good coding style that avoids lost interrupt requests: Example 2.

  • Page 75: Interrupt Request 0 Register

    ® Z8 Encore! F0830 Series Product Specification Interrupt Request 0 Register The Interrupt Request 0 (IRQ0) Register, shown in Table 35 stores the interrupt requests for both vectored and polled interrupts. When a request is sent to the Interrupt Controller, the corresponding bit in the IRQ0 Register becomes 1.

  • Page 76: Interrupt Request 1 Register

    ® Z8 Encore! F0830 Series Product Specification Interrupt Request 1 Register The Interrupt Request 1 (IRQ1) Register, shown in Table 36, stores interrupt requests for both vectored and polled interrupts. When a request is sent to the Interrupt Controller, the corresponding bit in the IRQ1 Register becomes 1.

  • Page 77: Interrupt Request 2 Register

    ® Z8 Encore! F0830 Series Product Specification Interrupt Request 2 Register The Interrupt Request 2 (IRQ2) Register, shown in Table 37, stores interrupt requests for both vectored and polled interrupts. When a request is sent to the Interrupt Controller, the corresponding bit in the IRQ2 Register becomes 1.

  • Page 78: Table 39. Irq0 Enable Low Bit Register (Irq0Enl)

    ® Z8 Encore! F0830 Series Product Specification Table 39. IRQ0 Enable High Bit Register (IRQ0ENH) Field Reserved T1ENH T0ENH Reserved ADCENH RESET Address FC1H Description Reserved This bit is reserved and must be programmed to 0. [6] Timer 1 Interrupt Request Enable High Bit T1ENH [5]...

  • Page 79: Irq1 Enable High And Low Bit Registers

    ® Z8 Encore! F0830 Series Product Specification IRQ1 Enable High and Low Bit Registers Table 41 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit reg- isters, shown in Tables 42 and 43, form a priority-encoded enabling service for interrupts in the Interrupt Request 1 Register.

  • Page 80: Irq2 Enable High And Low Bit Registers

    ® Z8 Encore! F0830 Series Product Specification Table 43. IRQ1 Enable Low Bit Register (IRQ1ENL) Field PA7ENL PA6CENL PA5ENL PA4ENL PA3ENL PA2ENL PA1ENL PA0ENL RESET Address FC5H Description [7] Port A Bit[7] Interrupt Request Enable Low Bit PA7ENL [6] Port A Bit[7] or Comparator Interrupt Request Enable Low Bit PA6CENL [5:0]...

  • Page 81: Table 45. Irq2 Enable Low Bit Register (Irq2Enl)

    ® Z8 Encore! F0830 Series Product Specification Table 45. IRQ2 Enable High Bit Register (IRQ2ENH) Field Reserved C3ENH C2ENH C1ENH C0ENH RESET Address FC7H Description [7:4] Reserved These registers are reserved and must be programmed to 0000. [3] Port C3 Interrupt Request Enable High Bit C3ENH [2]...

  • Page 82: Interrupt Edge Select Register

    ® Z8 Encore! F0830 Series Product Specification Interrupt Edge Select Register The interrupt edge select (IRQES) register determines whether an interrupt is generated for the rising edge or falling edge on the selected GPIO Port A or Port D input pin. See Table 47.

  • Page 83: Shared Interrupt Select Register

    ® Z8 Encore! F0830 Series Product Specification Shared Interrupt Select Register The shared interrupt select (IRQSS) register determines the source of the PADxS inter- rupts. See Table 48. The shared interrupt select register selects between Port A and alter- nate sources for the individual interrupts. Because these shared interrupts are edge-triggered, it is possible to generate an interrupt just by switching from one shared source to another.

  • Page 84: Interrupt Control Register

    ® Z8 Encore! F0830 Series Product Specification Interrupt Control Register The Interrupt Control (IRQCTL) Register, shown in Table 49, contains the master enable bit for all interrupts. Table 49. Interrupt Control Register (IRQCTL) Field IRQE Reserved RESET Address FCFH Description [7]...

  • Page 85: Timers

    F0830 Series Product Specification Timers The Z8 Encore! F0830 Series products contain up to two 16-bit reloadable timers that can be used for timing, event counting or generation of pulse width modulated (PWM) signals. The timers feature include: 16-bit reload counter •...

  • Page 86: Operation

    ® Z8 Encore! F0830 Series Product Specification Timer Block Timer Data Control Block Control Timer 16-Bit Interrupt, Interrupt Reload Register PWM, Timer Timer Output Output System Control Timer Clock 16-Bit Counter Output with Prescaler Timer Complement Input Gate 16-Bit Input PWM/Compare Capture Input...
  • Page 87 ® Z8 Encore! F0830 Series Product Specification reload. For the timer output to make a state change at a ONE-SHOT time-out (rather than a single cycle pulse), first set the TPOL bit in the Timer Control Register to the start value before enabling ONE-SHOT Mode.
  • Page 88 ® Z8 Encore! F0830 Series Product Specification Disable the timer – Configure the timer for CONTINUOUS Mode – Set the prescale value – If using the timer output A lternate function, set the initial output level (High or – Low) 2.
  • Page 89 ® Z8 Encore! F0830 Series Product Specification is enabled, the timer output pin changes state (from Low to High or from High to Low) at timer reload. Observe the following steps for configuring a timer for COUNTER Mode and for initiat- ing the count: 1.
  • Page 90 ® Z8 Encore! F0830 Series Product Specification The frequency of the comparator output signal must not exceed one-fourth the system Caution: clock frequency. After reaching the reload value stored in the Timer Reload High and Low Byte registers, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to and counting resumes.
  • Page 91 ® Z8 Encore! F0830 Series Product Specification PWM SINGLE OUTPUT Mode In PWM SINGLE OUTPUT Mode, the timer outputs a pulse width modulated (PWM) output signal through a GPIO port pin. The timer input is the system clock. The timer first counts up to 16-bit PWM match value stored in the timer PWM High and Low Byte regis- ters.
  • Page 92 ® Z8 Encore! F0830 Series Product Specification Reload Value Prescale  PWM Period (s) ------------------------------------------------------------------------ System Clock Frequency (Hz) If an initial starting value other than is loaded into the Timer High and Low Byte 0001H registers, use the ONE-SHOT Mode equation to determine the first PWM time-out period. If TPOL bit is set to 0, the ratio of the PWM output high time to the total period is repre- sented by: Reload Value PWM Value...
  • Page 93 ® Z8 Encore! F0830 Series Product Specification Observe the following steps for configuring a timer for PWM DUAL OUTPUT Mode and for initiating the PWM operation: 1. Write to the Timer Control Register to: Disable the timer – Configure the timer for PWM DUAL OU TPUT Mode; setting the mode also –...
  • Page 94 ® Z8 Encore! F0830 Series Product Specification Reload Value PWM Value – -------------------------------------------------------------------- - PWM Output High Time Ratio (%)  Reload Value is set to 1, the ratio of the PWM output high time to the total period is represented TPOL PWM Value --------------------------------...
  • Page 95 ® Z8 Encore! F0830 Series Product Specification 5. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both input capture and Reload events. If appropriate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting the TICONFIG field of the TxCTL1 Register.
  • Page 96 ® Z8 Encore! F0830 Series Product Specification 3. Write to the Timer Reload High and Low Byte registers to set the reload value. 4. Clear the timer PWM High and Low Byte registers to . This allows user soft- 0000H ware to determine if interrupts are generated by either a capture event or a reload.
  • Page 97 ® Z8 Encore! F0830 Series Product Specification 4. Enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the timer output function, configure the associated GPIO port pin for the timer output alternate function.
  • Page 98 ® Z8 Encore! F0830 Series Product Specification tion and reload events. The user can configure the timer interrupt to be generated only at the input deassertion event or the reload event by setting the TICONFIG field of the TxCTL1 Register. 5.

  • Page 99: Reading The Timer Count Values

    ® Z8 Encore! F0830 Series Product Specification 6. Write to the Timer Control Register to enable the timer. 7. Counting begins on the first appropriate transition of the timer input signal. No inter- rupt is generated by the first edge. In CAPTURE/COMPARE Mode, the elapsed time from timer start to capture event can be calculated using the following equation: Capture Value Start Value...

  • Page 100: Timer Control Register Definitions

    ® Z8 Encore! F0830 Series Product Specification Timer Control Register Definitions This section defines the features of the following Timer Control registers. Timer 0–1 High and Low Byte Registers: see page 83 Timer Reload High and Low Byte Registers: see page 85 Timer 0–1 PWM High and Low Byte Registers: see page 86 Timer 0–1 Control...
  • Page 101 ® Z8 Encore! F0830 Series Product Specification Description [7:0] Timer High and Low Bytes TH, TL These 2 bytes, {TH[7:0], TL[7:0]}, contain the current 16-bit timer count value. PS025112-1011 Timer Control Register Definitions...

  • Page 102: Timer Reload High And Low Byte Registers

    ® Z8 Encore! F0830 Series Product Specification Timer Reload High and Low Byte Registers The Timer 0–1 Reload High and Low Byte (TxRH and TxRL) registers, shown in Tables 52 and 53, store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer Reload High Byte Register are stored in a temporary holding register.

  • Page 103: Timer 0-1 Pwm High And Low Byte Registers

    ® Z8 Encore! F0830 Series Product Specification Timer 0–1 PWM High and Low Byte Registers The Timer 0–1 PWM High and Low Byte (TxPWMH and TxPWML) registers, shown in Tables 54 and 55, control PWM operations. These registers also store the capture values for the CAPTURE and CAPTURE/COMPARE modes.

  • Page 104: Timer 0-1 Control Registers

    ® Z8 Encore! F0830 Series Product Specification Timer 0–1 Control Registers The Timer Control registers are 8-bit read/write registers that control the operation of their associated counter/timers. Time 0–1 Control Register 0 The Timer Control 0 (TxCTL0) and Timer Control 1 (TxCTL1) registers determine the timer operating mode.

  • Page 105: Table 57. Timer 0-1 Control Register 1 (Txctl1)

    ® Z8 Encore! F0830 Series Product Specification Description (Continued) [0] Input Capture Event INPCAP This bit indicates whether the most recent timer interrupt is caused by a timer input capture event. 0 = Previous timer interrupt is not caused by timer input capture event. 1 = Previous timer interrupt is caused by timer input capture event.
  • Page 106 ® Z8 Encore! F0830 Series Product Specification Description (Continued) [6] Timer Input/Output Polarity TPOL Operation of this bit is a function of the current operating mode of the timer. ONE-SHOT Mode When the timer is disabled, the timer output signal is set to the value of this bit. When the timer is enabled, the timer output signal is complemented on timer reload.
  • Page 107 ® Z8 Encore! F0830 Series Product Specification Description (Continued) [6] PWM DUAL OUTPUT Mode TPOL 0 = Timer output is forced Low (0) and timer output complement is forced High (1), when the (cont’d) timer is disabled. When enabled and the PWM count matches, the timer output is forced High (1) and forced Low (0) when enabled and reloaded.
  • Page 108 ® Z8 Encore! F0830 Series Product Specification Description (Continued) [2:0] Timer Mode TMODE This field along with the TMODEHI bit in TxCTL0 register determines the operating mode of the timer. TMODEHI is the most significant bit of the timer mode selection value. 0000 = ONE-SHOT Mode.

  • Page 109: Watchdog Timer

    Watchdog Timer The Watchdog Timer (WDT) protects from corrupted or unreliable software, power faults and other system-level problems which can place the Z8 Encore! F0830 Series devices into unsuitable operating states. The features of the Watchdog Timer include: On-chip RC oscillator •...

  • Page 110: Watchdog Timer Refresh

    WDT reload value stored in the Watchdog Timer Reload registers. Counting resumes following the Reload operation. When the Z8 Encore! F0830 Series devices are operating in DEBUG Mode (using the On- Chip Debugger), the Watchdog Timer must be continuously refreshed to prevent any WDT time-outs.

  • Page 111: Watchdog Timer Reload Unlock Sequence

    ® Z8 Encore! F0830 Series Product Specification WDT Reset in Normal Operation If configured to generate a reset when a time-out occurs, the Watchdog Timer forces the device into the System Reset state. The WDT status bit in the Watchdog Timer Control Register is set to 1.

  • Page 112: Watchdog Timer Control Register Definitions

    ® Z8 Encore! F0830 Series Product Specification Watchdog Timer Control Register Definitions This section defines the features of the following Watchdog Timer Control registers. Watchdog Timer Control Register (WDTCTL): see page 95 Watchdog Timer Reload Low Byte Register (WDTL): see page 97 Watchdog Timer Reload Upper Byte Register (WDTU): see page 96 Watchdog Timer Reload High Byte Register...

  • Page 113: Watchdog Timer Reload Upper, High And Low Byte Registers

    ® Z8 Encore! F0830 Series Product Specification Watchdog Timer Reload Upper, High and Low Byte Registers The Watchdog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) regis- ters, shown in Tables 60 through 62, form the 24-bit reload value that is loaded into the Watchdog Timer when a WDT instruction executes.

  • Page 114: Table 62. Watchdog Timer Reload Low Byte Register (Wdtl)

    ® Z8 Encore! F0830 Series Product Specification Table 62. Watchdog Timer Reload Low Byte Register (WDTL) Field WDTL RESET R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Address FF3H Note: *A read returns the current WDT count value; a write sets the appropriate reload value. Description [7:0]...

  • Page 115: Analog-To-Digital Converter

    ® Z8 Encore! F0830 Series Product Specification Analog-to-Digital Converter The Z8 Encore! MCU includes an eight-channel Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The ADC converts an analog input signal to a 10-bit binary number. The features of the SAR ADC include: Eight analog input sources multiplexed with general purpose I/O ports •...

  • Page 116: Operation

    ® Z8 Encore! F0830 Series Product Specification REFEN Sel 28 Package Internal Voltage RBUF Reference Generator Analog Input Multiplexer Analog-to-Digital ANA0 Converter ANA1 Reference Input ANA2 Data ANA3 Output Sample-and-Hold ANA4 Analog Input Amplifier BUSY ANA5 ANA6 ANA7 ADCLK ANAIN[2:0] ADCEN SAMPLE/HOLD START...

  • Page 117: Adc Timing

    ® Z8 Encore! F0830 Series Product Specification ADC Timing Each ADC measurement consists of three phases: 1. Input sampling (programmable, minimum of 1.0 µs) 2. Sample-and-hold amplifier settling (programmable, minimum of 0.5 µs) 3. Conversion is 13 ADCLK cycles Figures 12 and 13 display the timing of an ADC conversion. conversion period START 1.0µs min...

  • Page 118: Adc Interrupt

    ® Z8 Encore! F0830 Series Product Specification ADC Interrupt The ADC can generate an interrupt request when a conversion has been completed. An interrupt request that is pending when the ADC is disabled is not cleared automatically. Reference Buffer The reference buffer, RBUF, supplies the reference voltage for the ADC. When enabled, the internal voltage reference generator supplies the ADC.

  • Page 119: Adc Control Register 0

    ® Z8 Encore! F0830 Series Product Specification ADC Control Register 0 The ADC Control 0 Register, shown in Table 63, initiates an A/D conversion and provides ADC status information. Table 63. ADC Control Register 0 (ADCCTL0) Field START Reserved REFEN ADCEN Reserved ANAIN[2:0]...

  • Page 120: Adc Data High Byte Register

    ® Z8 Encore! F0830 Series Product Specification ADC Data High Byte Register The ADC Data High Byte Register, listed in Table 64, contains the upper eight bits of the ADC output. Access to the ADC Data High Byte Register is read-only. Reading the ADC Data High Byte Register latches data in the ADC Low Bits Register.

  • Page 121: Sample Settling Time Register

    ® Z8 Encore! F0830 Series Product Specification Sample Settling Time Register The Sample Settling Time Register, shown in Table 66, is used to program a delay after the SAMPLE/HOLD signal is asserted and before the START signal is asserted; an ADC conversion then begins.

  • Page 122: Sample Time Register

    ® Z8 Encore! F0830 Series Product Specification Sample Time Register The Sample Time Register, shown in Table 67, is used to program the length of active time for a sample after a conversion has begun by setting the START bit in the ADC Control Register.

  • Page 123: Comparator

    ® Z8 Encore! F0830 Series Product Specification Comparator The Z8 Encore! F0830 Series devices feature a general purpose comparator that compares two analog input signals. A GPIO ( ) pin provides the positive comparator input. The CINP negative input (...

  • Page 124: Comparator Control Register Definitions

    ® Z8 Encore! F0830 Series Product Specification Comparator Control Register Definitions The Comparator Control Register (CMP0) configures the comparator inputs and sets the value of the internal voltage reference. The GPIO pin is always used as positive compara- tor input. Table 68.

  • Page 125: Flash Memory

    Product Specification Flash Memory The products in the Z8 Encore! F0830 Series features either 1 KB (1024 bytes with NVDS), 2 KB (2048 bytes with NVDS), 4 KB (4096 bytes with NVDS), 8 KB (8192 bytes with NVDS) or 12 KB (12288 bytes with no NVDS) of nonvolatile Flash memory with read/write/erase capability.

  • Page 126: Figure 15. 2K Flash With Nvds

    ® Z8 Encore! F0830 Series Product Specification 07FFH 07FFH Sector 3 Page 3 0600H 0600H 05FFH 05FFH Sector 2 Page 2 0400H 0400H 03FFH 03FFH Sector 1 Page 1 0200H 0200H 01FFH 01FFH Sector 0 Page 0 0000H 0000H Figure 15. 2K Flash with NVDS 0FFFH 0FFFH Page 7...

  • Page 127: Figure 17. 8K Flash With Nvds

    ® Z8 Encore! F0830 Series Product Specification 1FFFH Page 15 1FFFH 1E00H 1DFFH Page 14 Sector 7 1C00H 1C00H 1BFFH Page 13 18FFH 1A00H 19FFH Page 12 Sector 6 1800H 1800H 17FFH Page 11 17FFH 1600H Sector 5 15FFH Page 10 1400H 1400H 13FFH...

  • Page 128: Data Memory Address Space

    ® Z8 Encore! F0830 Series Product Specification 2FFFH 2FFFH Page 23 2E00H Sector 7 2A00H 2DFFH Page 22 29FFH 2C00H Sector 6 2BFFH Page 21 1600H 2A00H 23FFH Page 20 Sector 5 1E00H 1DFFH Sector 4 1800H 17FFH Sector 3 1200H 11FFH Sector 2...

  • Page 129: Operation

    ® Z8 Encore! F0830 Series Product Specification Flash information area is mapped into program memory and overlays the 128 bytes in the address range . When the information area access is enabled, all reads FE00H FE7FH from these program memory addresses return the information area data rather than the program memory data.

  • Page 130: Figure 19. Flash Controller Operation Flow Chart

    ® Z8 Encore! F0830 Series Product Specification Reset Lock State 0 Write Page Select Register Write FCTL Lock State 1 Writes to Page Select Register in Lock State 1 result in a return to Lock State 0 Write FCTL Write Page Select Register Page Select values match?

  • Page 131: Flash Operation Timing Using The Flash Frequency Registers

    Caution: 10 kHz or above 20 MHz. The Flash Frequency High and Low Byte registers must be loaded with the correct value to ensure operation of the Z8 Encore! F0830 Series devices. Flash Code Protection Against External Access The user code contained within Flash memory can be protected against external access by using the On-Chip Debugger.

  • Page 132: Table 71. Flash Code Protection Using The Flash Option Bits

    Flash memory, unless this value is smaller than the page size, in which case the sector and page sizes are equal. On Z8 Encore! F0830 Series devices, the sector size is varied according to the Z8 Encore! F0830 Series Flash Memory Configura-...

  • Page 133: Byte Programming

    ® Z8 Encore! F0830 Series Product Specification bits can only be set to 1. Thus, sectors can be protected, but not unprotected, via register write operations. Writing a value other than to the Flash Control Register deselects the Flash Sector Protect Register and reenables access to the Page Select Register. Observe the following procedure to setup the Flash Sector Protect Register from user code: 1.

  • Page 134: Page Erase

    ® Z8 Encore! F0830 Series Product Specification Page Erase Flash memory can be erased one page (512 bytes) at a time. Page erasing Flash memory sets all bytes in that page to the value . The Flash Page Select Register identifies the page to be erased.

  • Page 135: Nvds Operational Requirements

    ® Z8 Encore! F0830 Series Product Specification The Flash Sector Protect Register is ignored for programming and Erase operations. • Programming operations are not limited to the page selected in the page select register. • Bits in the Flash Sector Protect Register can be written to one or zero. •...

  • Page 136: Flash Control Register

    ® Z8 Encore! F0830 Series Product Specification Flash Control Register The Flash Controller must be unlocked using the Flash Control Register before program- ming or erasing Flash memory. Writing the sequence , sequentially, to the Flash 73H 8CH Control Register unlocks the Flash Controller. When the Flash Controller is unlocked, Flash memory can be enabled for mass erase or page erase by writing the appropriate enable command to the FCTL.

  • Page 137: Flash Status Register

    ® Z8 Encore! F0830 Series Product Specification Flash Status Register The Flash Status Register indicates the current state of the Flash Controller. This register can be read at any time. The read-only Flash Status Register shares its register file address with the write-only Flash Control Register.

  • Page 138: Flash Page Select Register

    ® Z8 Encore! F0830 Series Product Specification Flash Page Select Register The Flash Page Select Register shares address space with the Flash Sector Protect Regis- ter. Unless the Flash Controller is locked and written with , any writes to this address will target the Flash Page Select Register.

  • Page 139: Flash Sector Protect Register

    ® Z8 Encore! F0830 Series Product Specification Flash Sector Protect Register The Flash Sector Protect Register is shared with the Flash Page Select Register. When the Flash Control Register is locked and written with , the next write to this address tar- gets the Flash Sector Protect Register.

  • Page 140: Flash Frequency High And Low Byte Registers

    ® Z8 Encore! F0830 Series Product Specification Flash Frequency High and Low Byte Registers The Flash Frequency High and Low Byte registers, shown in Tables 76 and 77, combine to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. The 16-bit binary Flash frequency value must contain the system clock frequency (in kHz) and is calculated using the following equation: System Clock Frequency...

  • Page 141: Flash Option Bits

    Flash option bits are automatically read from Flash program memory and written to the Option Configuration registers, which control Z8 Encore! F0830 Series device operation. Option bit control is established before the device exits reset and the eZ8 CPU begins code execution.

  • Page 142: Option Bit Types

    ® Z8 Encore! F0830 Series Product Specification Option Bit Types This section describes the two types of Flash option bits offered in the F0830 Series. User Option Bits The user option bits are contained in the first two bytes of program memory. User access to these bits is provided because these locations contain application specific device config- urations.

  • Page 143: Flash Option Bit Control Register Definitions

    ® Z8 Encore! F0830 Series Product Specification Flash Option Bit Control Register Definitions This section briefly describes the features of the Trim Bit Address and Data registers. Trim Bit Address Register The Trim Bit Address Register, shown in Table 78, contains the target address to access the trim option bits.

  • Page 144: Flash Option Bit Address Space

    ® Z8 Encore! F0830 Series Product Specification Table 80. Trim Bit Data Register (TRMDR) Field TRMDR: Trim Bit Data RESET Address FF7H Flash Option Bit Address Space The first two bytes of Flash program memory at addresses are reserved 0000H 0001H for the user-programmable Flash option bits.

  • Page 145: Table 82. Flash Options Bits At Program Memory Address 0001H

    ® Z8 Encore! F0830 Series Product Specification Description (Continued) [3] Voltage Brown-Out Protection Always On VBO_AO 0 = Voltage Brown-Out protection is disabled in STOP Mode to reduce total power con- sumption. 1 = Voltage Brown-Out protection is always enabled, even during STOP Mode. This setting is the default setting for unprogrammed (erased) Flash.

  • Page 146: Trim Bit Address Space

    ® Z8 Encore! F0830 Series Product Specification Description (Continued) [4] State of the Crystal Oscillator at Reset XTLDIS This bit enables only the crystal oscillator. Selecting the crystal oscillator as the system clock must be performed manually. 0 = The crystal oscillator is enabled during reset, resulting in longer reset timing. 1 = The crystal oscillator is disabled during reset, resulting in shorter reset timing.

  • Page 147: Table 83. Trim Option Bits At 0000H (Adcref)

    ® Z8 Encore! F0830 Series Product Specification Table 83. Trim Bit Address Space Address Function ADC reference voltage ADC and comparator Internal Precision Oscillator Oscillator and VBO ClkFltr Table 84. Trim Option Bits at 0000H (ADCREF) Field ADCREF_TRIM Reserved RESET Address Information Page Memory 0020H Note: U = Unchanged by Reset.

  • Page 148: Table 86. Trim Option Bits At 0002H (Tipo)

    ® Z8 Encore! F0830 Series Product Specification The bit values used in Table 85 are set at the factory; no calibration is required. Note: Table 86. Trim Option Bits at 0002H (TIPO) Field IPO_TRIM RESET Address Information Page Memory 0022H Note: U = Unchanged by Reset.

  • Page 149: Table 88. Vbo Trim Definition

    ® Z8 Encore! F0830 Series Product Specification The bit values used in Table 87 are set at the factory; no calibration is required. Note: Table 88. VBO Trim Definition Trigger Voltage VBO_TRIM Level On-chip Flash memory is only guaranteed to perform write operations when voltage sup- plies exceed 2.7 V.

  • Page 150: Table 90. Clkflt Delay Control Definition

    ® Z8 Encore! F0830 Series Product Specification Description (Continued) [1:0] Filter Select FilterSely 2-bit selection for the clock filter mode. 00 = No filter. 01 = Filter low level noise on high level signal. 10 = Filter high level noise on low level signal. 11 = Filter both.

  • Page 151: Nonvolatile Data Storage

    Flash. The products in the Z8 Encore! F0830 Series feature multiple NVDS array sizes. See the Note: Z8 Encore! F0830 Series Family Part Selection Guide section on page 2 for details.

  • Page 152: Byte Write

    ® Z8 Encore! F0830 Series Product Specification Byte Write To write a byte to the NVDS array, the user code must first push the address, then the data byte onto the stack. The user code issues a instruction to the address of the Byte CALL Write routine ( ).

  • Page 153: Byte Read

    ® Z8 Encore! F0830 Series Product Specification Byte Read To read a byte from the NVDS array, user code must first push the address onto the stack. User code issues a instruction to the address of the byte-read routine ( ).

  • Page 154: Power Failure Protection

    ® Z8 Encore! F0830 Series Product Specification Power Failure Protection NVDS routines employ error-checking mechanisms to ensure that any power failure will only endanger the most recently written byte. Bytes previously written to the array are not perturbed. For this protection to function, the VBO must be enabled (see the Low-Power Modes chapter on page 30) and configured for a threshold voltage of 2.4 V or greater (see...
  • Page 155 ® Z8 Encore! F0830 Series Product Specification Because the minimum read time is much less than the write time, however, actual speed benefits are not always realized. 2. Use as few unique addresses as possible to optimize the impact of refreshing. PS025112-1011 NVDS Code Interface...

  • Page 156: On-Chip Debugger

    ® Z8 Encore! F0830 Series Product Specification On-Chip Debugger The Z8 Encore! devices contain an integrated On-Chip Debugger (OCD) that provides the following advanced debugging features: Reading and writing of the register file • Reading and writing of program and data memory •...

  • Page 157: Operation

    ® Z8 Encore! F0830 Series Product Specification Operation The following section describes the operation of the On-Chip Debugging function. OCD Interface The On-Chip Debugger uses the DBG pin for communication with an external host. This one-pin interface is a bidirectional open-drain interface that transmits and receives data. Data transmission is half-duplex, which means that transmission and data retrieval cannot occur simultaneously.

  • Page 158: Debug Mode

    ® Z8 Encore! F0830 Series Product Specification RS-232 10KΩ Transceiver Open-Drain Buffer RS-232 TX DBG Pin RS-232 RX Figure 22. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, #2 of 2 DEBUG Mode The operating characteristics of the devices in DEBUG Mode are: The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to ex- •...

  • Page 159: Ocd Data Format

    ® Z8 Encore! F0830 Series Product Specification Watchdog Timer reset • Asserting the RESET pin Low to initiate a reset • Driving the DBG pin Low while the device is in STOP Mode initiates a system reset • OCD Data Format The OCD interface uses the asynchronous data format defined for RS-232.

  • Page 160: Ocd Serial Errors

    ® Z8 Encore! F0830 Series Product Specification If the OCD receives a serial break (nine or more continuous bits low), the autobaud detec- tor/generator resets. Reconfigure the autobaud detector/generator by sending OCD Serial Errors The OCD can detect any of the following error conditions on the DBG pin: Serial break (a minimum of nine continuous bits Low) •...

  • Page 161: Runtime Counter

    Flash read protect option bit (FRP). The FRP prevents the code in memory from being read out of the Z8 Encore! F0830 Series products. When this option is enabled, several of the OCD commands are disabled.
  • Page 162 ® Z8 Encore! F0830 Series Product Specification Table 95. On-Chip Debugger Command Summary (Continued) Command Enabled when not Disabled by Debug Command Byte in DEBUG Mode? Flash Read Protect Option Bit Read Program Memory CRC – – Reserved – – Step Instruction –...
  • Page 163 ® Z8 Encore! F0830 Series Product Specification The read OCD Control Register command reads the Read OCD Control Register (05H). value of the OCDCTL register. ← 05H → OCDCTL[7:0] The write program counter command, writes the data that Write Program Counter (06H). follows to the eZ8 CPU’s program counter (PC).
  • Page 164 ® Z8 Encore! F0830 Series Product Specification ← 0AH ← Program Memory Address[15:8] ← Program Memory Address[7:0] ← Size[15:8] ← Size[7:0] ← 1–65536 data bytes The read program memory command, reads data from Read Program Memory (0BH). program memory. This command is equivalent to the LDC and LDCI instructions. Data can be read 1–65536 bytes at a time (65536 bytes can be read by setting size to 0).

  • Page 165: On-Chip Debugger Control Register Definitions

    The OCD Control Register controls the state of the On-Chip Debugger. This register is used to enter or exit DEBUG Mode and to enable the instruction. It can also reset the Z8 Encore! F0830 Series device. A reset and stop function can be achieved by writing to this register. A reset and go function can be achieved by writing to this register.

  • Page 166: Table 96. Ocd Control Register (Ocdctl)

    Flash read protect option bit is enabled, this bit can only be cleared by resetting the device. It cannot be written to 0. 0 = The Z8 Encore! F0830 Series device is operating in NORMAL Mode. 1 = The Z8 Encore! F0830 Series device is in DEBUG Mode.

  • Page 167: Ocd Status Register

    ® Z8 Encore! F0830 Series Product Specification OCD Status Register The OCD Status Register reports status information about the current state of the debugger and the system. Table 97. OCD Status Register (OCDSTAT) Field HALT FRPENB Reserved RESET Description [7] Debug Status 0 = NORMAL Mode.

  • Page 168: Oscillator Control

    ® Z8 Encore! F0830 Series Product Specification Oscillator Control The Z8 Encore! F0830 Series device uses five possible clocking schemes. Each one of these is user-selectable. On-chip precision trimmed RC oscillator • On-chip oscillator using off-chip crystal or resonator •...

  • Page 169: Table 98. Oscillator Configuration And Selection

    ® Z8 Encore! F0830 Series Product Specification Table 98. Oscillator Configuration and Selection Clock Source Characteristics Required Setup Internal precision • 32.8 kHz or 5.53 • Unlock and write to the Oscillator Con- RC oscillator • ± 4% accuracy when trimmed trol Register (OSCCTL) to enable and •...

  • Page 170: Clock Failure Detection And Recovery

    ® Z8 Encore! F0830 Series Product Specification When selecting a new clock source, the primary oscillator failure detection circuitry and the Watchdog Timer Oscillator failure circuitry must be disabled. If POFEN and WOFEN are not disabled prior to a clock switch-over, it is possible to generate an interrupt for a failure of either oscillator.

  • Page 171: Oscillator Control Register Definitions

    It is possible to disable the clock failure detection circuitry as well as all functioning Caution: clock sources. In this case, the Z8 Encore! F0830 Series device ceases functioning and can only be recovered by power-on-reset. Oscillator Control Register Definitions The following section provides the bit definitions for the Oscillator Control Register.
  • Page 172 ® Z8 Encore! F0830 Series Product Specification Description (Continued) [4] Primary Oscillator Failure Detection Enable POFEN 1 = Failure detection and recovery of primary oscillator is enabled. 0 = Failure detection and recovery of primary oscillator is disabled. [3] Watchdog Timer Oscillator Failure Detection Enable WDFEN 1 = Failure detection of Watchdog Timer Oscillator is enabled.

  • Page 173: Figure 24. Oscillator Control Clock Switching Flow Chart

    ® Z8 Encore! F0830 Series Product Specification Normal Running Switch to OSC? Switch to IPO? Switch to WDT? WDT OSC is OSC is enabled? IPO is enabled? enabled? Set bit7 in OSCCTL Set bit6 in Set bit5 in OSCCTL register and wait OSCCTL register register and wait one NOP...

  • Page 174: Crystal Oscillator

    Product Specification Crystal Oscillator The products in the Z8 Encore! F0830 Series contain an on-chip crystal oscillator for use with external crystals with 32 kHz to 20 MHz frequencies. In addition, the oscillator sup- ports external RC networks with oscillation frequencies up to 4 MHz or ceramic resonators with frequencies up to 8 MHz.

  • Page 175: Figure 25. Recommended 20 Mhz Crystal Oscillator Configuration

    ® Z8 Encore! F0830 Series Product Specification ister, the user code must wait at least 5000 IPO cycles for the crystal to stabilize. After this period, the crystal oscillator may be selected as the system clock. Figure 25 displays a recommended configuration for connection with an external funda- mental-mode, parallel-resonant crystal operating at 20 MHz.

  • Page 176: Oscillator Operation With An External Rc Network

    ® Z8 Encore! F0830 Series Product Specification Oscillator Operation with an External RC Network Figure 26 displays a recommended configuration for connection with an external resistor- capacitor (RC) network. Figure 26. Connecting the On-Chip Oscillator to an External RC Network An external resistance value of 45 kΩ...

  • Page 177: Figure 27. Typical Rc Oscillator Frequency As A Function Of External Capacitance

    ® Z8 Encore! F0830 Series Product Specification 4000 3750 3500 3250 3000 2750 2500 2250 2000 1750 1500 1250 1000 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500 C (pF) Figure 27.

  • Page 178: Internal Precision Oscillator

    ® Z8 Encore! F0830 Series Product Specification Internal Precision Oscillator The Internal Precision Oscillator (IPO) is designed for use without external components. The user can either manually trim the oscillator for a nonstandard frequency or use the automatic factory-trimmed version to achieve a 5.53 MHz frequency with ± 4% accuracy and 45%~55% duty cycle over the operating temperature and supply voltage of the device.

  • Page 179: Ez8 Cpu Instruction Set

    ® Z8 Encore! F0830 Series Product Specification eZ8 CPU Instruction Set This chapter describes the following features of the eZ8 CPU instruction set: Assembly Language Programming Introduction: see page 162 Assembly Language Syntax: see page 163 eZ8 CPU Instruction Notation: see page 164 eZ8 CPU Instruction Classes: see page 166 eZ8 CPU Instruction...

  • Page 180: Assembly Language Syntax

    ® Z8 Encore! F0830 Series Product Specification Assembly Language Source Program Example ; Everything after the semicolon is a comment. JP START ; A label called “START”. The first instruction (JP START) in this START: ; example causes program execution to jump to the point within the ;...

  • Page 181: Ez8 Cpu Instruction Notation

    ® Z8 Encore! F0830 Series Product Specification Example 2 In general, when an instruction format requires an 8-bit register address, the address can specify any register location in the range 0–255 or, using escaped mode addressing, a working register R0–R15. If the contents of register and working register R8 are added and the result is stored in , the assembly syntax and resulting object code is:...

  • Page 182: Table 104. Additional Symbols

    ® Z8 Encore! F0830 Series Product Specification Table 103. Notational Shorthand (Continued) Notation Description Operand Range Register Reg. represents a number in the range of 00H to FFH Relative Address X represents an index in the range of +127 to – 128 which is an offset relative to the address of the next instruction Working Register Pair...

  • Page 183: Ez8 Cpu Instruction Classes

    ® Z8 Encore! F0830 Series Product Specification This example indicates that the source data is added to the destination data; the result is stored in the destination location. eZ8 CPU Instruction Classes eZ8 CPU instructions can be divided functionally into the following groups: Arithmetic •...

  • Page 184: Table 106. Bit Manipulation Instructions

    ® Z8 Encore! F0830 Series Product Specification Table 105. Arithmetic Instructions (Continued) Mnemonic Operands Instruction INCW Increment Word MULT Multiply dst, src Subtract with Carry SBCX dst, src Subtract with Carry using Extended Addressing dst, src Subtract SUBX dst, src Subtract using Extended Addressing Table 106.

  • Page 185: Table 108. Cpu Control Instructions

    ® Z8 Encore! F0830 Series Product Specification Table 108. CPU Control Instructions Mnemonic Operands Instruction — Atomic Execution — Complement Carry Flag — Disable Interrupts — Enable Interrupts HALT — HALT Mode — No Operation — Reset Carry Flag — Set Carry Flag Set Register Pointer STOP...

  • Page 186: Table 110. Rotate And Shift Instructions

    ® Z8 Encore! F0830 Series Product Specification Table 110. Logical Instructions Mnemonic Operands Instruction dst, src Logical AND ANDX dst, src Logical AND using Extended Addressing Complement dst, src Logical OR dst, src Logical OR using Extended Addressing dst, src Logical Exclusive OR XORX dst, src...
  • Page 187 ® Z8 Encore! F0830 Series Product Specification Table 112. Rotate and Shift Instructions (Continued) Mnemonic Operands Instruction Rotate Right Rotate Right through Carry Shift Right Arithmetic Shift Right Logical SWAP Swap Nibbles PS025112-1011 eZ8 CPU Instruction Classes...

  • Page 188: Ez8 Cpu Instruction Summary

    ® Z8 Encore! F0830 Series Product Specification eZ8 CPU Instruction Summary Table 113 summarizes the eZ8 CPU instructions. The table identifies the addressing modes employed by the instruction, the effect upon the Flags register, the number of CPU clock cycles required for the instruction fetch and the number of CPU clock cycles required for the instruction execution.
  • Page 189 ® Z8 Encore! F0830 Series Product Specification Table 113. eZ8 CPU Instruction Summary (Continued) Address Mode Flags Assembly Code(s) Fetch Instr. Mnemonic Symbolic Operation (Hex) C Z S V D H Cycles Cycles dst ← dst AND src AND dst, src –...
  • Page 190 ® Z8 Encore! F0830 Series Product Specification Table 113. eZ8 CPU Instruction Summary (Continued) Address Mode Flags Assembly Code(s) Fetch Instr. Mnemonic Symbolic Operation (Hex) C Z S V D H Cycles Cycles dst ← 00H CLR dst – – – –...
  • Page 191 ® Z8 Encore! F0830 Series Product Specification Table 113. eZ8 CPU Instruction Summary (Continued) Address Mode Flags Assembly Code(s) Fetch Instr. Mnemonic Symbolic Operation (Hex) C Z S V D H Cycles Cycles dst ← dst – 1 DJNZ dst, RA 0A–FA –...
  • Page 192 ® Z8 Encore! F0830 Series Product Specification Table 113. eZ8 CPU Instruction Summary (Continued) Address Mode Flags Assembly Code(s) Fetch Instr. Mnemonic Symbolic Operation (Hex) C Z S V D H Cycles Cycles dst ← src LD dst, rc 0C–FC –...
  • Page 193 ® Z8 Encore! F0830 Series Product Specification Table 113. eZ8 CPU Instruction Summary (Continued) Address Mode Flags Assembly Code(s) Fetch Instr. Mnemonic Symbolic Operation (Hex) C Z S V D H Cycles Cycles dst ← src LDX dst, src – –...
  • Page 194 ® Z8 Encore! F0830 Series Product Specification Table 113. eZ8 CPU Instruction Summary (Continued) Address Mode Flags Assembly Code(s) Fetch Instr. Mnemonic Symbolic Operation (Hex) C Z S V D H Cycles Cycles dst ← @SP POPX dst – – – –...
  • Page 195 ® Z8 Encore! F0830 Series Product Specification Table 113. eZ8 CPU Instruction Summary (Continued) Address Mode Flags Assembly Code(s) Fetch Instr. Mnemonic Symbolic Operation (Hex) C Z S V D H Cycles Cycles SRA dst – – D7 D6 D5 D4 D3 D2 D1 D0 SRL dst 1F C0 –...
  • Page 196 ® Z8 Encore! F0830 Series Product Specification Table 113. eZ8 CPU Instruction Summary (Continued) Address Mode Flags Assembly Code(s) Fetch Instr. Mnemonic Symbolic Operation (Hex) C Z S V D H Cycles Cycles TM dst, src dst AND src – –...

  • Page 197: Op Code Maps

    ® Z8 Encore! F0830 Series Product Specification Op Code Maps A description of the opcode map data and the abbreviations are provided in Figure 28. Table 114 on page 181 lists opcode map abbreviations. Op Code Lower Nibble Fetch Cycles Instruction Cycles Op Code Upper Nibble...

  • Page 198: Table 114. Op Code Map Abbreviations

    ® Z8 Encore! F0830 Series Product Specification Table 114. Op Code Map Abbreviations Abbreviation Description Abbreviation Description Bit position Indirect Register Pair Condition code Polarity (0 or 1) 8-bit signed index or displace- 4-bit Working Register ment Destination address 8-bit register Extended Addressing Register r1, R1, Ir1, Irr1, Destination address...

  • Page 199: Figure 29. First Op Code Map

    ® Z8 Encore! F0830 Series Product Specification Figures 29 and 30 provide information about each of the eZ8 CPU instructions. Lower Nibble (Hex) ADDX ADDX DJNZ r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM IR1,IM ER2,ER1 IM,ER1 r1,X cc,X r1,IM cc,DA See 2nd ADCX ADCX Op Code...

  • Page 200: Figure 30. Second Op Code Map After 1Fh

    ® Z8 Encore! F0830 Series Product Specification Lower Nibble (Hex) CPCX CPCX r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM IR1,IM ER2,ER1 IM,ER1 5, 4 LDWX ER2,ER1 Figure 30. Second Op Code Map after 1FH PS025112-1011 Op Code Maps...

  • Page 201: Electrical Characteristics

    ® Z8 Encore! F0830 Series Product Specification Electrical Characteristics The data in this chapter represents all known data prior to qualification and characteriza- tion of the F0830 Series of products, and is therefore subject to change. Additional electri- cal characteristics may be found in the individual chapters of this document. Absolute Maximum Ratings Stresses greater than those listed in Table 115 may cause permanent damage to the device.

  • Page 202: Dc Characteristics

    Z8 Encore! F0830 Series Product Specification DC Characteristics Table 116 lists the DC characteristics of the Z8 Encore! F0830 Series products. All volt- ages are referenced to V , the primary system ground. Table 116. DC Characteristics = 0°C to +70°C = –40°C to +105°C...
  • Page 203 ® Z8 Encore! F0830 Series Product Specification Table 116. DC Characteristics (Continued) = 0°C to +70°C = –40°C to +105°C Symbol Parameter Units Conditions Controlled See GPIO section on Current Drive LED description 10.5 19.5 GPIO Port Pad – – Capacitance XIN Pad –...

  • Page 204: Figure 31. Icc Versus System Clock Frequency (Halt Mode)

    ® Z8 Encore! F0830 Series Product Specification Figure 31 displays the typical current consumption while operating at 25 ºC, 3.3 V, versus the system clock frequency in HALT Mode. Figure 31. I Versus System Clock Frequency (HALT Mode) PS025112-1011 DC Characteristics...

  • Page 205: Figure 32. Icc Versus System Clock Frequency (Normal Mode)

    ® Z8 Encore! F0830 Series Product Specification Figure 32 displays the typical current consumption versus the system clock frequency in NORMAL Mode. Figure 32. I Versus System Clock Frequency (NORMAL Mode) PS025112-1011 DC Characteristics...

  • Page 206: Ac Characteristics

    ® Z8 Encore! F0830 Series Product Specification AC Characteristics The section provides information about the AC characteristics and timing. All AC timing information assumes a standard load of 50 pF on all outputs. Table 117. AC Characteristics = 2.7 to 3.6 V = 2.7 to 3.6 V = –40°C to = 0°C to +70°C...

  • Page 207: On-Chip Peripheral Ac And Dc Electrical Characteristics

    ® Z8 Encore! F0830 Series Product Specification Table 117. AC Characteristics (Continued) = 2.7 to 3.6 V = 2.7 to 3.6 V = –40°C to = 0°C to +70°C +105°C Symbol Parameter Units Conditions System Clock Rise – = 50 ns XINR Time System Clock Fall...
  • Page 208 ® Z8 Encore! F0830 Series Product Specification Table 118. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing = –40°C to = 0°C to +70°C +105°C Symbol Parameter Units Conditions Power-On Reset µs 66 Internal Preci- Digital Delay sion Oscillator cycles Power-On Reset 5000 Internal Pre-...

  • Page 209: Table 119. Flash Memory Electrical Characteristics And Timing

    ® Z8 Encore! F0830 Series Product Specification Table 119. Flash Memory Electrical Characteristics and Timing = 2.7 to 3.6 V = 2.7 to 3.6 V = 0°C to +70°C = –40°C to +105°C Parameter Units Notes Flash Byte Read – –...

  • Page 210: Table 121. Nonvolatile Data Storage

    ® Z8 Encore! F0830 Series Product Specification Table 121. Nonvolatile Data Storage = 2.7 to 3.6 V = 2.7 to 3.6 V = 0°C to +70°C = –40°C to +105°C Parameter Units Notes NVDS Byte Read – µs With system clock at Time 20 MHz NVDS Byte Pro-...

  • Page 211: Table 123. Comparator Electrical Characteristics

    ® Z8 Encore! F0830 Series Product Specification Table 122. Analog-to-Digital Converter Electrical Characteristics and Timing (Continued) = 2.7 to 3.6 V = 2.7 to 3.6 V = 0°C to +70°C = –40°C to +105°C Symbol Parameter Units Conditions Input Impedance MΩ...

  • Page 212: General Purpose I/O Port Input Data Sample Timing

    ® Z8 Encore! F0830 Series Product Specification General Purpose I/O Port Input Data Sample Timing Figure 33 displays timing of the GPIO port input sampling. The input value on a GPIO port pin is sampled on the rising edge of the system clock. The port value is available to the eZ8 CPU on the second rising clock edge following the change of the port value.

  • Page 213: General Purpose I/O Port Output Timing

    ® Z8 Encore! F0830 Series Product Specification General Purpose I/O Port Output Timing Figure 34 and Table 125 provide timing information for the GPIO port pins. TCLK Port Output Figure 34. GPIO Port Output Timing Table 125. GPIO Port Output Timing Delay (ns) Parameter Abbreviation...

  • Page 214: On-Chip Debugger Timing

    ® Z8 Encore! F0830 Series Product Specification On-Chip Debugger Timing Figure 35 and Table 126 provide timing information for the DBG pin. The DBG pin tim- ing specifications assume a 4 ns maximum rise and fall time. TCLK Output Data (Output) Input Data (Input)

  • Page 215: Figure 36. Flash Current Diagram

    ® Z8 Encore! F0830 Series Product Specification Table 127. Power Consumption Reference Table Power Consumption Category Block Typical Maximum Logic CPU/Peripherals @ 20 MHz 5 mA Flash Flash @ 20 MHz 12 mA ADC @ 20 MHz 4 mA 4.5 mA 350 µA 400 µA Comparator @ 10 MHz...

  • Page 216: Packaging

    ® Z8 Encore! F0830 Series Product Specification Packaging Zilog’s F0830 Series of MCUs includes the Z8F0130, Z8F0131, Z8F0230, Z8F0231, Z8F1232 and Z8F1233 devices, which are available in the following packages: 20-Pin Quad Flat No-Lead Package (QFN) • 20-pin Small Outline Integrated Circuit Package (SOIC) •...

  • Page 217: Ordering Information

    Zilog website lists all regional offices. Table 128. Z8 Encore! XP F0830 Series Ordering Matrix Part Number Flash NVDS Channels Description Z8 Encore! F0830 Series MCUs with 12 KB Flash Standard Temperature: 0°C to 70°C Z8F1232SH020SG 12 KB SOIC 20-pin Z8F1232HH020SG...
  • Page 218 ® Z8 Encore! F0830 Series Product Specification Table 128. Z8 Encore! XP F0830 Series Ordering Matrix Part Number Flash NVDS Channels Description Z8F1233QH020EG 12 KB QFN 20-pin Z8F1232SJ020EG 12 KB SOIC 28-pin Z8F1232HJ020EG 12 KB SSOP 28-pin Z8F1232PJ020EG 12 KB PDIP 28-pin Z8F1232QJ020EG 12 KB...
  • Page 219 ® Z8 Encore! F0830 Series Product Specification Table 128. Z8 Encore! XP F0830 Series Ordering Matrix Part Number Flash NVDS Channels Description Z8F0831HH020EG 8 KB SSOP 20-pin Z8F0831PH020EG 8 KB PDIP 20-pin Z8F0831QH020EG 8 KB QFN 20-pin Z8F0830SJ020EG 8 KB SOIC 28-pin Z8F0830HJ020EG 8 KB...
  • Page 220 ® Z8 Encore! F0830 Series Product Specification Table 128. Z8 Encore! XP F0830 Series Ordering Matrix Part Number Flash NVDS Channels Description Z8F0430QH020EG 4 KB QFN 20-pin Z8F0431SH020EG 4 KB SOIC 20-pin Z8F0431HH020EG 4 KB SSOP 20-pin Z8F0431PH020EG 4 KB PDIP 20-pin Z8F0431QH020EG 4 KB...
  • Page 221 ® Z8 Encore! F0830 Series Product Specification Table 128. Z8 Encore! XP F0830 Series Ordering Matrix Part Number Flash NVDS Channels Description Extended Temperature: –40°C to 105°C Z8F0230SH020EG 2 KB SOIC 20-pin Z8F0230HH020EG 2 KB SSOP 20-pin Z8F0230PH020EG 2 KB PDIP 20-pin Z8F0230QH020EG 2 KB...
  • Page 222 ® Z8 Encore! F0830 Series Product Specification Table 128. Z8 Encore! XP F0830 Series Ordering Matrix Part Number Flash NVDS Channels Description Z8F0131PJ020SG 1 KB PDIP 28-pin Z8F0131QJ020SG 1 KB QFN 28-pin Extended Temperature: –40°C to 105°C Z8F0130SH020EG 1 KB SOIC 20-pin Z8F0130HH020EG 1 KB...

  • Page 223: Part Number Suffix Designations

    ® Z8 Encore! F0830 Series Product Specification Part Number Suffix Designations Zilog part numbers consist of a number of components, as indicated in the following example. Part number Z8F0830SH020SG is an 8-bit 20 MHz Flash MCU with 8 KB Pro- Example.

  • Page 224: Table 129. Package And Pin Count Description

    ® Z8 Encore! F0830 Series Product Specification Table 129 lists the pin count by package. Table 129. Package and Pin Count Description Pin Count Package √ √ PDIP √ √ √ √ SOIC √ √ SSOP PS025112-1011 Part Number Suffix Designations...

  • Page 225: Appendix A. Register Tables

    ® Z8 Encore! F0830 Series Product Specification Appendix A. Register Tables For the reader’s convenience, this appendix lists all F0830 Series registers numerically by hexadecimal address. General Purpose RAM In the F0830 Series, the hexadecimal address range is partitioned for general- 000–EFF purpose random access memory, as follows.

  • Page 226: Table 131. Timer 0 Low Byte Register (T0L)

    ® Z8 Encore! F0830 Series Product Specification Hex Address: F01 Table 131. Timer 0 Low Byte Register (T0L) Field RESET Address F01H Hex Address: F02 Table 132. Timer 0 Reload High Byte Register (T0RH) Field RESET Address F02H Hex Address: F03 Table 133.

  • Page 227: Table 135. Timer 0 Pwm Low Byte Register (T0Pwml)

    ® Z8 Encore! F0830 Series Product Specification Hex Address: F05 Table 135. Timer 0 PWM Low Byte Register (T0PWML) Field PWML RESET Address F05H Hex Address: F06 Table 136. Timer 0 Control Register 0 (T0CTL0) Field TMODEHI TICONFIG Reserved PWMD INPCAP RESET Address...

  • Page 228: Table 139. Timer 1 Low Byte Register (T1L)

    ® Z8 Encore! F0830 Series Product Specification Hex Address: F09 Table 139. Timer 1 Low Byte Register (T1L) Field RESET Address F09H Hex Address: F0A Table 140. Timer 1 Reload High Byte Register (T1RH) Field RESET Address F0AH Hex Address: F0B Table 141.

  • Page 229: Table 143. Timer 1 Pwm Low Byte Register (T1Pwml)

    ® Z8 Encore! F0830 Series Product Specification Hex Address: F0D Table 143. Timer 1 PWM Low Byte Register (T1PWML) Field PWML RESET Address F0DH Hex Address: F0E Table 144. Timer 1 Control Register 0 (T1CTL0) Field TMODEHI TICONFIG Reserved PWMD INPCAP RESET Address...

  • Page 230: Analog-To-Digital Converter

    ® Z8 Encore! F0830 Series Product Specification Analog-to-Digital Converter For more information about these ADC registers, see the ADC Control Register Defini- tions section on page 101. Hex Address: F70 Table 146. ADC Control Register 0 (ADCCTL0) Field START Reserved REFEN ADCEN Reserved...

  • Page 231: Table 147. Adc Data High Byte Register (Adcd_H)

    ® Z8 Encore! F0830 Series Product Specification Hex Address: F71 This address range is reserved. Hex Address: F72 Table 147. ADC Data High Byte Register (ADCD_H) Field ADCDH RESET Address F72H Description [7:0] ADC High Byte 00h–FFh = The last conversion output is held in the data registers until the next ADC conver- sion is completed.

  • Page 232: Table 149. Adc Sample Settling Time (Adcsst)

    ® Z8 Encore! F0830 Series Product Specification Hex Address: F74 Table 149. ADC Sample Settling Time (ADCSST) Field Reserved RESET Address F74H Description [7:4] Reserved These bits are reserved and must be programmed to 0000. [3:0] Sample Settling Time 0h–Fh = Number of system clock periods to meet 0.5 µs minimum. Hex Address: F75 Table 150.

  • Page 233: Low Power Control

    ® Z8 Encore! F0830 Series Product Specification Low Power Control For more information about the Power Control Register, see the Power Control Register Definitions section on page 31. Hex Address: F80 Table 151. Power Control Register 0 (PWRCTL0) Field Reserved Reserved Reserved COMP Reserved...

  • Page 234: Oscillator Control

    ® Z8 Encore! F0830 Series Product Specification Hex Address: F83 Table 153. LED Drive Level High Register (LEDLVLH) Field LEDLVLH[7:0] RESET Address F83H Hex Address: F84 Table 154. LED Drive Level Low Register (LEDLVLL) Field LEDLVLL[7:0] RESET Address F84H Hex Address: F85 This address range is reserved.

  • Page 235: Comparator 0

    ® Z8 Encore! F0830 Series Product Specification Hex Addresses: F87–F8F This address range is reserved. Comparator 0 For more information about the Comparator Register, see the Comparator Control Regis- ter Definitions section on page 107. Hex Address: F90 Table 156. Comparator Control Register (CMP0) Field Reserved INNSEL...

  • Page 236: Table 158. Irq0 Enable High Bit Register (Irq0Enh)

    ® Z8 Encore! F0830 Series Product Specification Hex Address: FC1 Table 158. IRQ0 Enable High Bit Register (IRQ0ENH) Field Reserved T1ENH T0ENH Reserved Reserved Reserved Reserved ADCENH RESET Address FC1H Hex Address: FC2 Table 159. IRQ0 Enable Low Bit Register (IRQ0ENL) Field Reserved T1ENL...

  • Page 237: Table 162. Irq1 Enable Low Bit Register (Irq1Enl)

    ® Z8 Encore! F0830 Series Product Specification Hex Address: FC5 Table 162. IRQ1 Enable Low Bit Register (IRQ1ENL) Field PA7ENL PA6CENL PA5ENL PA4ENL PA3ENL PA2ENL PA1ENL PA0ENL RESET Address FC5H Hex Address: FC6 Table 163. Interrupt Request 2 Register (IRQ2) Field Reserved PC3I...

  • Page 238: Table 166. Interrupt Edge Select Register (Irqes)

    ® Z8 Encore! F0830 Series Product Specification Hex Addresses: FC9–FCC This address range is reserved. Hex Address: FCD Table 166. Interrupt Edge Select Register (IRQES) Field IES7 IES6 IES5 IES4 IES3 IES2 IES1 IES0 RESET Address FCDH Hex Address: FCE Table 167.

  • Page 239: Gpio Port A

    ® Z8 Encore! F0830 Series Product Specification GPIO Port A For more information about the GPIO registers, see the GPIO Control Register Definitions section on page 39. Hex Address: FD0 Table 169. Port A GPIO Address Register (PAADDR) Field PADDR[7:0] RESET Address FD0H...

  • Page 240: Table 172. Port A Output Data Register (Paout)

    ® Z8 Encore! F0830 Series Product Specification Hex Address: FD3 Table 172. Port A Output Data Register (PAOUT) Field POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 RESET Address FD3H Hex Address: FD4 Table 173. Port B GPIO Address Register (PBADDR) Field PADDR[7:0] RESET...

  • Page 241: Table 176. Port B Output Data Register (Pbout)

    ® Z8 Encore! F0830 Series Product Specification Hex Address: FD7 Table 176. Port B Output Data Register (PBOUT) Field POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 RESET Address FD7H Hex Address: FD8 Table 177. Port C GPIO Address Register (PCADDR) Field PADDR[7:0] RESET...

  • Page 242: Table 180. Port C Output Data Register (Pcout)

    ® Z8 Encore! F0830 Series Product Specification Hex Address: FDB Table 180. Port C Output Data Register (PCOUT) Field POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 RESET Address FDBH Hex Address: FDC Table 181. Port D GPIO Address Register (PDADDR) Field PADDR[7:0] RESET...

  • Page 243: Watchdog Timer

    ® Z8 Encore! F0830 Series Product Specification Hex Address: FDF Table 183. Port D Output Data Register (PDOUT) Field POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 RESET Address FDFH Hex Addresses: FE0–FEF This address range is reserved. Watchdog Timer For more information about the Watchdog Timer registers, see the Watchdog Timer Con- trol Register Definitions...

  • Page 244: Table 186. Watchdog Timer Reload Upper Byte Register (Wdtu)

    ® Z8 Encore! F0830 Series Product Specification Hex Address: FF1 Table 186. Watchdog Timer Reload Upper Byte Register (WDTU) Field WDTU RESET R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Address FF1H Note: *Read returns the current WDT count value; write sets the appropriate reload value. Hex Address: FF2 Table 187.

  • Page 245: Trim Bit Control

    ® Z8 Encore! F0830 Series Product Specification Trim Bit Control For more information about the Trim Bit Control registers, see the Flash Option Bit Con- trol Register Definitions section on page 126. Hex Address: FF6 Table 189. Trim Bit Address Register (TRMADR) Field TRMADR - Trim Bit Address (00H to 1FH) RESET...

  • Page 246: Table 192. Flash Status Register (Fstat)

    ® Z8 Encore! F0830 Series Product Specification Hex Address: FF8 Table 192. Flash Status Register (FSTAT) Field Reserved FSTAT RESET Address FF8H Hex Address: FF9 The Flash Page Select Register is shared with the Flash Sector Protect Register. Table 193. Flash Page Select Register (FPS) Field INFO_EN PAGE...

  • Page 247: Table 196. Flash Frequency Low Byte Register (Ffreql)

    ® Z8 Encore! F0830 Series Product Specification Hex Address: FFB Table 196. Flash Frequency Low Byte Register (FFREQL) Field FFREQL RESET Address FFBH PS025112-1011 Flash Memory Controller...

  • Page 248: Index

    ® Z8 Encore! F0830 Series Product Specification Index binary number suffix 165 Numerics BIT 167 10-bit ADC 4 bit 164 clear 167 manipulation instructions 167 set 167 absolute maximum ratings 184 set or clear 167 AC characteristics 189 swap 167 ADC 166 test and jump 169 block diagram 99...
  • Page 249 ® Z8 Encore! F0830 Series Product Specification complement 169 electrical noise 98 complement carry flag 167, 168 enable interrupt 168 condition code 164 ER 164 continuous mode 89 extended addressing register 164 Control Registers 14, 17 external pin reset 25 counter modes 89 eZ8 CPU features 4 CP 166...
  • Page 250 ® Z8 Encore! F0830 Series Product Specification indirect working register 164 indirect working register pair 164 gated mode 89 instruction set, ez8 CPU 162 general-purpose I/O 33 instructions GPIO 4, 33 ADC 166 alternate functions 34 ADCX 166 architecture 34 ADD 166 control register definitions 39 ADDX 166...
  • Page 251 ® Z8 Encore! F0830 Series Product Specification LDE 168 interrupt vectors and priority 56 LDEI 167 operation 55 LDX 168 register definitions 57 LEA 168 software interrupt assertion 57 load 168 interrupt edge select register 65 logical 169 interrupt request 0 register 58 MULT 167 interrupt request 1 register 59 NOP 168...
  • Page 252 ® Z8 Encore! F0830 Series Product Specification load instructions 168 IR 164 load using extended addressing 168 Ir 164 logical AND 169 IRR 164 logical AND/extended addressing 169 Irr 164 logical exclusive OR 169 p 164 logical exclusive OR/extended addressing 169 R 165 logical instructions 169 r 164...
  • Page 253 ® Z8 Encore! F0830 Series Product Specification stuff instruction (11H) 148 program counter 165 write data memory (0CH) 147 program memory 15 write OCD control register (04H) 145 PUSH 168 write program counter (06H) 146 push using extended addressing 168 write program memory (0AH) 146 PUSHX 168 write register (08H) 146...
  • Page 254 ® Z8 Encore! F0830 Series Product Specification registers sources 26 ADC channel 1 102 using a GPIO port pin transition 27, 28 ADC data high byte 103 using watch-dog timer time-out 27 ADC data low bit 103, 104, 105 SUB 167 reset subtract 167 and stop mode characteristics 22...
  • Page 255 ® Z8 Encore! F0830 Series Product Specification control registers 87, 88 XORX 169 high and low byte registers 83, 86 TM 167 TMX 167 TRAP 169 Z8 Encore! block diagram 3 features 1 part selection guide 2 vector 165 voltage brown-out reset (VBR) 24 voltage measurement timing diagram 100 watch-dog timer approximate time-out delay 92...

  • Page 256: Customer Support

    ® Z8 Encore! F0830 Series Product Specification Customer Support To share comments, get your technical questions answered or report issues you may be experiencing with our products, please visit Zilog’s Technical Support page at  http://support.zilog.com. To learn more about this product, find additional documentation or to discover other facets about Zilog product offerings, please visit the Zilog Knowledge Base at http://zilog.com/ or consider participating in the Zilog Forum at http://zilog.com/forum.

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