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AN625
User's guide to BGT60LTR11AIP
60 GHz Radar
About this document
Scope and purpose
This application note is intended to provide more details on how to use BGT60LTR11AIP in an actual user guide
in addition to the datasheet.
Since the datasheet gives only technical data and limits of the device itself, this user's guide is explaining how
to operate the device in greater detail, and describes:
•
All different building blocks
•
How to operate the different blocks
•
Settings of the SPI registers are grouped on topic, including truth tables
Intended audience
This document serves as a primer for firmware or software engineers who want to get started with hardware
design for Infineon's 60 GHz BGT60LTR11AIP and its derivatives BGT60LTR11SAIP and BGT60LTR11BAIP.
Application Note
www.infineon.com
Please read the sections "Important notice" and "Warnings" at the end of this document
V1.5
2022-08-01
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Table of Contents
Related Manuals for Infineon BGT60LTR11AIP
Summary of Contents for Infineon BGT60LTR11AIP
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Page 1: About This Document
About this document Scope and purpose This application note is intended to provide more details on how to use BGT60LTR11AIP in an actual user guide in addition to the datasheet. Since the datasheet gives only technical data and limits of the device itself, this user's guide is explaining how to operate the device in greater detail, and describes: •... -
Page 2: Table Of Contents
User's guide to BGT60LTR11AIP 60 GHz Radar Table of contents Table of contents About this document ..............1 Table of contents . - Page 3 User's guide to BGT60LTR11AIP 60 GHz Radar Table of contents 3.2.14 Register Reg12 – BITE ..............37 3.2.15...
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Page 4: Introduction
It is designed to operate as a Doppler motion sensor in the frequency band from 61 GHz to 61.5 GHz for the BGT60LTR11AIP and BGT60LTR11SAIP versions, and from 60.5 GHz to 61 GHz for the BGT60LTR11BAIP version. -
Page 5: Main Controller
N.A. Departing high Approaching The BGT60LTR11AIP provides four quad state inputs QS1-4. With one quad state input it is possible to get four states from one input pin. These pins are used for configuration of the chip. Application Note V1.5... -
Page 6: Quad State Inputs And "Advance Mode
User's guide to BGT60LTR11AIP 60 GHz Radar 2 Main controller Quad state inputs and “Advance mode” On reset of the digital main controller and during the init sequence some chip input pins are sampled to determine the configuration the chip should start with. -
Page 7: Qs2
User's guide to BGT60LTR11AIP 60 GHz Radar 2 Main controller Table 4 (continued) QS1 Operating mode open Autonomous pulsed mode 100 kΩ to V SPI mode with external 9.6 MHz clock enabled SPI mode Not a normal working mode. Only for test purpose, e.g. FCC, ETSI. -
Page 8: Qs3
User's guide to BGT60LTR11AIP 60 GHz Radar 2 Main controller 2.1.5 QS3 is used to select the hold time of the TDet output, this defines how long the output status will be kept after a target is detected, it is written into register Reg10 described in Register Reg10 –... -
Page 9: Qs4
60 GHz Radar 2 Main controller 2.1.6 QS4 is used to select the device operating frequency by configuring the PLL. Frequency is also dependent on version of the chip: BGT60LTR11AIP and BGT60LTR11SAIP, or BGT60LTR11BAIP. Table 7 VCO frequency BGT60LTR11AIP and BGT60LTR11SAIP ground 61.1 GHz... -
Page 10: Power-Up
User's guide to BGT60LTR11AIP 60 GHz Radar 2 Main controller 2.2.1 Power-up Figure 4 shows internal signals relevant for power-up. Figure 4 Power-up Supply ramp needs to be shorter than 400 µs. The bias_en is connected directly to the supply therefore it ramps simultaneously. - Page 11 User's guide to BGT60LTR11AIP 60 GHz Radar 2 Main controller The init sequence starts directly after power-up/reset. It consists of the following steps: Read quad state inputs, which needs 200 μs for analog settling, to know the selected operation mode. If...
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Page 12: Autonomous Pulsed Mode Sequence
User's guide to BGT60LTR11AIP 60 GHz Radar 2 Main controller Table 8 (continued) Init sequence in detail Command Description write Reg1 0x1037 Set bb_sample_en wait 5 ms Wait time for baseband settling end for autonomous CW End init sequence if mode = autonomous CW mode... - Page 13 User's guide to BGT60LTR11AIP 60 GHz Radar 2 Main controller Table 9 (continued) Autonomous pulsed mode sequence in detail Command Description write Reg0 0x393F Reset pll_active, pll_clk_gate_en Wait 100 ns write Reg0 0x391F Reset mpa_en Wait 100 ns write Reg1 0x0092...
- Page 14 User's guide to BGT60LTR11AIP 60 GHz Radar 2 Main controller For the init phase, PLL and RF are switched off in the following order: Sample&Hold / MPA / PLL / Divider bias / RF, each step has to take 100 ns. A time t is required after MPA is disabled.
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Page 15: Autonomous Cw Mode Sequence
User's guide to BGT60LTR11AIP 60 GHz Radar 2 Main controller 2.2.4 Autonomous CW mode sequence In autonomous continuous wave mode, the device is active as configured with quad state inputs. The main controller only uses the sensor ADC and evaluates the IF signals in the digital detector. The init sequence was left at the right step, so the CW mode sequence itself contains only two entries as only one control signal has to be switched off and the digital part of the detector has to be switched on. -
Page 16: Spi Mode Sequence
User's guide to BGT60LTR11AIP 60 GHz Radar 2 Main controller 2.2.5 SPI mode sequence This is the manual mode, main controller is inactive and Reg0/1 are set to all off by main controller. The SPI sequence just has to switch off quad state inputs. Depending on quad state input QS1, external 9.6 MHz clock is enabled (QS1="10") or not (QS1="11"). - Page 17 User's guide to BGT60LTR11AIP 60 GHz Radar 2 Main controller Table 12 (continued) Overview dynamic control signals Autonomous pulsed mode Autonomous CW mode SPI mode bb_sample_en toggling Dynamic control signals are used to switch on/off analog and also digital blocks. They are located in the direct access registers (=register 0/1).
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Page 18: Spi Interface
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface SPI interface SPI – Serial Peripheral Interface • 7-bit continues address space • Fixed payload of 16-bits • Chip-Select (Slave Select) active in low state Has to be “1” unless an SPI access is done by external SPI master. Such an access is recommended only in SPI mode. -
Page 19: Spi Interface Description
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface SPI interface description The SPI command is read via the data input SPIDI (serial data in), which is synchronized with the clock input SPICLK provided by the master. The output word appears synchronously at the data output SPIDO (serial data out). -
Page 20: Spi Burst Mode
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface 3.1.3 SPI burst mode The burst mode can be used to read or write out several registers instead of reading just single registers. The burst mode command consists of several bit fields and is shown in... -
Page 21: Spi Registers
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface SPI registers 3.2.1 Register overview Table 14 Register overview Register Mode Contents Reset value Value after init sequence (pulsed sleep/CW) Reg0 Control bits 0x0000 0x0900 / 0x373F Reg1 Control bits... -
Page 22: Direct Access Register
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface 3.2.2 Direct access register Reg0 and Reg1 are direct access registers shown in Figure 13. These bits can be controlled directly by the main controller. All other registers need to be programmed by SPI from external optional microcontroller or internally from the main controller at power-up. - Page 23 User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface Table 15 (continued) Register map Reg6 [15:8] pll_ld_tw_sel pll_ld_le pll_ld_en reserved [7:0] reserved Reg7 [15:8] reserved dc_rep_rate dc_on_pulse_len [7:0] reserved vco2pll_d mpa2sh_dly pd_en mpa_ctrl Reg8 [15:8] reserved [7:0] reserved div_sel...
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Page 24: Register Reg0 - Direct Access Register
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface Table 15 (continued) Register map Reg38 [15:0] ADC result register channel 0 - 15 Reg53 Reg56 [15:8] qs1_s init_done qs2_s qs3_s qs4_s [7:0] qs4_s advance_ reserved pll_lock_ chip_version mode detect... - Page 25 User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface (continued) Field Bits Type Description pll_clk_gate_en Enable PLL clock gating Activates clock for digital portion of the pll. Synchronized within : PLL dig clock off : PLL dig clock on...
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Page 26: Register Reg1 - Direct Access Register
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface 3.2.5 Register Reg1 – Direct access register Value after init sequence: 0x0092 for pulsed mode Value after init sequence: 0x10B3 for CW mode DAR_REG1_REG Address: 0x01 Register assignment of Reg1... -
Page 27: Register Reg2 - Threshold
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface (continued) Field Bits Type Description bb_strup_hp Baseband startup boost mode : Startup boost mode disabled : Startup boost mode enabled bb_amp_en Enable baseband amplifier : Baseband amplifier disabled : Baseband amplifier enabled... -
Page 28: Register Reg4 - Pll Config 1
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface (continued) Field Bits Type Description thrs 12:0 Detector threshold level Default after init sequence (dep. on QS2) This is internally divided by 32 and then corresponds to LSB of the ADC results of the IF signals. - Page 29 User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface (continued) Field Bits Type Description pll_bias_dis Disable PLL bias Default after init sequence: 0 Disables bandgap in PLL and V2I converter (=PLL biasing). Can be set to further reduce current consumption in SPI mode. Also disables clock for internal main controller therefore pulsing is not possible if PLL biasing is switched off.
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Page 30: Register Reg5 - Pll Config 2
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface (continued) Field Bits Type Description pll_cp_icp_sel Charge pump current setting Default after init sequence: 7 : 20 µA : 25 µA : 30 µA : 35 µA : 40 µA : 45 µA... -
Page 31: Register Reg6 - Pll Config 3
60 GHz Predefined settings for Japan mode (BGT60LTR11BAIP): 0xEA2: 60.6 GHz 0xECC: 60.7 GHz 0xEF5: 60.8 GHz 0xF1F: 60.9 GHz Predefined settings for Europe mode (BGT60LTR11AIP and BGT60LTR11SAIP): 0xF72: 61.1 GHz 0xF9C: 61.2 GHz 0xFC6: 61.3 GHz 0xFEF: 61.4 GHz 3.2.9... -
Page 32: Register Reg7 - Duty Cycling, Timing, Pd, Mpa
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface Field Bits Type Description pll_ld_tw_sel 15:13 Lock detection time window Default after init sequence: 3 Accepted phase difference for lock detection condition within comparator (Typical values). : 0.26 ns : 0.5 ns : 1.0 ns... - Page 33 User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface Field Bits Type Description 15:12 Not Used. Do not change reset values. dc_rep_rate 11:10 Duty cycle repetition rate In Advance mode this is defined by inputs SPICLK and SPIDI. See Chapter 2.1.2.
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Page 34: Register Reg8 - Divider
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface (continued) Field Bits Type Description mpa_ctrl Medium power amplifier gain control Default after init sequence: 7 : -34 dBm : -31.5 dBm : -25 dBm : -18 dBm : -11 dBm... -
Page 35: Register Reg9 - Baseband
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface (continued) Field Bits Type Description div_out_en Enable divider out Default: 0 Enables the 2^14, 2^17, 2^21 divider logic. Setting div_out_en provides the divided output frequency from the VCO to Div_O pad based on div_sel value. The div_sel value of “0”... - Page 36 User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface (continued) Field Bits Type Description bb_clk_chop_sel Select clock chop frequency Default: 1 Selects frequency of clock for chopping (input for analog). In ABB it is divided by 2 (to get 50% duty cycle) and by 2 again.
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Page 37: Register Reg10 - Hold Time
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface 3.2.13 Register Reg10 – Hold time Value after init sequence: Depends on QS3 HT_REG10_REG Address: 0x0A Register assignment of Reg10 Reset value: 0x0000 hold hold Field Bits Type Description hold... -
Page 38: Register Reg13 - Algo 1
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface (continued) Field Bits Type Description bb_amux_en Enable analog voltage mux on QS4 pad Default after init sequence: 0 : AMUX off : AMUX on bite_pd_en Enable BITE power detector Default after init sequence: 0... - Page 39 User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface (continued) Field Bits Type Description phase_win_len Phase Window Length Default after init sequence: 0 The phase difference is averaged during a window of this length. This setting is xor-ed with the dc_rep_rate before selection by the...
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Page 40: Register Reg14 - Algo 2
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface 3.2.16 Register Reg14 – Algo 2 Value after init sequence: 0x0000 Can be changed by metal patch ALGO2_REG14_REG Address: 0x0E Register assignment of Reg14 Reset value: 0x0000 thrs_offset autoblind_ dir_hys_dis... -
Page 41: Register Reg15 - Digital Control
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface (continued) Field Bits Type Description pulse_mon Monitor Radar Pulse Default after init sequence: 0 : Output pad PDet used as normal direction indication : Output pad PDet used to monitor internal radar pulse timing... - Page 42 User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface (continued) Field Bits Type Description start_pm Start pulsed mode Default after init sequence: 0 With this bit it is possible to start the SPI pulsed mode (or CW mode). Typical use case is to configure registers and start the pulsed/CW mode afterwards by setting this bit to one.
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Page 43: Register Reg34 - Adc Start
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface (continued) Field Bits Type Description mot_pol Motion polarity Default after init sequence: 0 : TDet is low-active : TDet is high-active dir_pol Direction polarity Default after init sequence: 0 : PDet is low when departing... -
Page 44: Register Reg35 - Adc Convert
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface (continued) Field Bits Type Description adc_en Enable ADC block Default: 0 : ADC disabled : ADC enabled bandgap_en Enable bandgap Default: 0 This bandgap is needed for ADC. : Bandgap disabled... -
Page 45: Register Reg36 - Adc Status
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface (continued) Field Bits Type Description chnr Channel number Default: 0 Analog input channel number selected for sampling. 3.2.20 Register Reg36 – ADC status ADC_STS_REG36_REG Address: 0x24 Register assignment of Reg36... -
Page 46: Register Reg38-53 - Adc Result
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface 3.2.21 Register Reg38–53 – ADC result These are the result registers of the ADC, a result is 10-bit wide, bit 0-9 of each register is occupied. Bits 10-15 are not used. As the ADC is physically an 8-bit ADC also bit 0 and bit 1 are not used. Not used bits will deliver a zero when read. -
Page 47: Register Reg56 - Status And Chip Version
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface 3.2.22 Register Reg56 – Status and chip version Reset value: depending on chip_version and stat_mux (Reg15[3:0]) (here the fields for stat_mux="0" is shown) Value after init sequence: depending on chip_version and QS1, init_done=1, pll_lock_detect=1... - Page 48 User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface (continued) Field Bits Type Description qs4_s Quad state input 4 These bits contain the read value from QS4 input which is read during initial sequence after power-up. : QS4 = GND : QS4 = open : QS4 = 100 kΩ...
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Page 49: Register Gsr0 - Spi Status Register
User's guide to BGT60LTR11AIP 60 GHz Radar 3 SPI interface 3.2.23 Register GSR0 – SPI status register The global status register GSR0 is sent on SPIDO at the same time as the address and the read/write bit is sent on SPIDI, MSB leading. There is only one bit used, it is bit adc_result_ready (GSR0[2]). This is a flag for completed conversion. -
Page 50: Analog To Digital Converter
User's guide to BGT60LTR11AIP 60 GHz Radar 4 Analog to digital converter Analog to digital converter ADC conversion sequence An ADC conversion consists of four different phases detailed below: 4.1.1 Enable bandgap The bandgap is enabled by setting the bandgap_en bit (Reg34[1]). This can be done simultaneously with adc_clk_en (Reg34[0]). -
Page 51: Adc Configuration
User's guide to BGT60LTR11AIP 60 GHz Radar 4 Analog to digital converter ADC configuration 4.2.1 Analog input channel gain By setting bit lv_gain (Reg35[7]) the gain for the analog input channels can be selected as follows: • lv_gain=0: Fullscale analog input voltage = 1.613 V •... -
Page 52: Adc Power-Down Sequence
User's guide to BGT60LTR11AIP 60 GHz Radar 4 Analog to digital converter ADC power-down sequence In case a low current consumption mode is required, a full ADC power-down can be invoked in 2 phases: Disable ADC by setting adc_en to "0". The clock must still be running to enable the FSMs to switch to a defined state Disable clock by setting clock_enable to "0"... -
Page 53: Detector
User's guide to BGT60LTR11AIP 60 GHz Radar 5 Detector Detector Digital evaluation The detector is responsible for evaluating the input from the sensor ADC and for setting of TDet/PDet outputs of the BGT60LTR11AIP. Target detected (TDet) output is used to show if a motion is detected or not. TDet is an active low pin. Thus, it's set low when a motion is detected, otherwise high. -
Page 54: Revision History
User's guide to BGT60LTR11AIP 60 GHz Radar Revision history Revision history Document Date of Description of changes version release V1.0 2020-09-09 First preliminary release V1.1 2020-10-06 Added autonomous mode V1.2 2021-07-15 Changes all over the document V1.3 2021-10-11 Changes all over the document V1.4... -
Page 55: Disclaimer
Infineon Technologies, All Rights Reserved. information given herein in the real application. Infineon Technologies’ products may not be used in Infineon Technologies hereby disclaims any and all any applications where a failure of the product or warranties and liabilities of any kind (including without...