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9.2 POWER SUPPLY CIRCUIT
a. Backup +B
To keep memories, backup +Bis supplied to PD4050B and
PD4022B
even
when
the
ignition
switch
is off. The
+B (14.4V) battery source directly flows through D8 in the
Power Unit and is reduced to 5.3V for Vpd +B by the volt-
age regulator composed
of Q4, D5, D6, etc. This Vop
+B (5V) is applied to pins #7 and #33 (VppD) of PD4050B
and
PD4022B8
and
to
pin
#5
(Vpod)
of
PD7005.
b. Acc
+B
When the ignition switch is turned on, Acc +B (14.4V) is
applied to pins #7 (Vcc1) and #8 (Vcc2) of BA6209 and #5
of PA3009.
c. +B Supply for TAPE
When the TAPE is loaded, the deck controller PD4022B puts
TAPE ON signal (H: 5V) out of #23. This signal turns Q23
and Q6 in Control Unit on.(*1) When Q6 turns on, Acc +B
flows through D24-1, R164 and D26 (zener diode Vz: 6.2V)
and turns Q40 and Q7 on.(* 2) When Q7 turns on, Acc +B
becomes BT +8 and is applied to DC-DC converter L1 #4
for displaying.
This BT +B (14.2V) is reduced to 10V by the voltage regu-
lator composed of Q6, D9, etc. in Power Unit becomes AU
+B (10V) and is applied to each of the PAOOOSA
#16,
HA17358
#8 and PA2014
#1 Vcc terminals. And the AU
+B (10V) flows in D2 and is made 9.4V by D2's forward
voltage drop (VF) and is applied to TA75558P #8
(Vcc). Af-
ter passing Q6, Control Unit, the Acc +B is reduced to TAPE
+B1 (10V) by the regulator composed of Q1, Q2, Q3, D3,
etc. in the Power Unit and is fed to PAQOO8
#10 (Vcc). This
regulator employs a differential amplifier as a voltage sen-
sor to stabilize output voltage and to minimize wow and flut-
ter. If the reference voltage for the circuits which control
the Reel Motor and Capstan Motor fluctuates, the servo cir-
cuits will not work properly and will increase wow and flut-
ter. The TAPE +B1 (9.5V) is further reduced to 5V by the
regulator composed of Q5, D4, D5, etc. in the Power Unit
and is fed to PAOOO2A
#4 (Vcc). The TAPE +81 (10V) goes
through R67 and turns Q2 and Q1 on. Then TAPE +B2 is
fed
to
PA3017
#1(Vcc).
TAPE
+B2
is also
fed
to
TA7705P
#1 (Vcc) via D1.
d. +B Supply for TUNER
When TUNER is turned on
PD4050B #19 puts out TUNER
ON signal {H:5V). This signal turns Q25 and Q24 on. When
Q24 turns on, Acc +8 flows through D24-2, R164 and D26
and turns 040 and Q7 on. The BT +B and AU +B are ap-
plied to each AF IC in the same way as in the mode of TAPE
ON. But, TAPE
+B2 to the Vcc of TA7705 and PA3017,
which have no relation to the Tuner, is blocked by inactive Q1.
*1 The reason for connecting resistors in parallel: ~ -
Some circuits require a large current. This connection allows
a large current to go through resistors of small power
capacity. The power capacity of each chip-resistor is only
1/8W at present and is insufficient to allow a large current.
But by connecting two resistors in parallel the total current
16
can be doubled. Many resistors in other models and equip-
ment have been connected in parallel for this reason.
*2 The role of zener diode D26
The BT +B is used for the SWD (switched) +B of power
amplifier (for example, GM-A120). So, the power amplifier
is turned on and off by BT +B. This SWD
+8 is used also
to mute the audio signal. So, if the falling time of BT +B
is long, it takes a long time to activate muting and allows
a popping noise when the TUNER or TAPE is turned off. To
prevent this, zener diode D26 makes 040 turn off and block
the BT +B quickly after the TUNER or TAPE is turned off.
t
'
{
1
1
1
'
'
'
t
;
Tape dorr
~When D26 is inserted.
Threshold level where Q40 turns off and BT +B is blocked.
Fig. 22 040 OFF timing
02
9.3 BASIC CIRCUIT FOR OPERATING THE
SYSTEM (Fig. 24)
a. System Clock (CL1 & CL2)
The clock generator gives a reference timing to each com-
puter. The resistor and capacitor connected to CL1 and CL2
determine
oscillation
frequency.
The
pins
#7 (X7C),
#6 (X7R) and #8 (X7) of PD7005 work in the same way
as above. The oscillation frequency of all generators is
200kHz. Refer to the circuit diagram for the waveforms at
each terminal.
b. Timing Clock (T OUT)
This circuit generates squarewave synchronizing clock sig-
nal of 100Hz (50% duty factor for operating PD4050B).
PD4022B
#37) (T OUT) feeds PD4050B
#10 (CLK) with
this CLK signal because PD4050B has no timing clock gener-
ator inside.
c. Reset
This circuit resets the initial state of the computer programs
and their Display Controller PD7005. When the backup +B
is connected, this resets the computers and PD7005 by
feeding their RESET terminal (#3) with an H pulse of about
25ms. Without resetting, the computers will work random-
ly and become uncontrollable.
VDD
VDD
Ic2
PD40508
Ici
PD7005
VOD
Display Controller
System Controlier
BT+B
l4v
R167
9.4V
8
lov {16
10vi8
9.7V
91
vec
vcc
vcc
vec
IC2 : TA75558P
IC1 : PAQOOSA
IC4 > HAI7358
Ic4 : PA2O14
Tone
Amp:
Volume
Controi
Buffer Amp:
lsolator
Tape+B2
9.8V
g9.2vil
3.8V11
9.8V
11
vec
vec
vec
wee
C1 2 TAT705P
C2 : PA30I7
IC3 : PA3OI7
Sys)
&
.Z
go) Tape: Ve74
EQ Amp-
Dolby NR Amp:
Dolby NR Amp-
lov 10
singe nes VEC
(C3 : PAOO08
SV} 4
Reel Motor Control)
Capstan
Motor Control
Tuner - |
R204
Tape:
ee
D24—2]Tuner
ON signai(H: 5V)
se
Tape+B! lov 2!
aC 16
Y)
YY)
ES]
RI8 To p4
SRIO Q2
Sriigaie
Leek)
OA
ECA
}PD40228 pin23
R69
Tape ON signal(H : 5V)
tt
cig
RI3
visameT
Gard
A
20
na
CIS
Fig. 23 Power supply circuit
17
Deck Controller
d. Acc
When
PD4050B
#50 (Acc)
is L (OV),
PD4050B
keeps
memory, counts clock, senses low or high Acc input and
TUNER connection, and stops all other functions. To oper-
ate the system the potential at PD4050B
#50 should be
H (5V). When +B is fed from Acc {red line), a current is fed
to Q34-B via D31 and R123. Q34 turns on. Then Q33 turns
off. Vop (5V) is fed to PD4050B
#50 via R122 and R129.
sy Q4 13. 7v RIG
08
Tuner ; 14y
924
Tape : 14V
14.2V
vcC
LMT
RIS9
: PA3009
R200
Capstan
Motor
Drive
Cassette
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