Table of Contents
Advertisement
Chassisplatte / Chassis Board – DVB-S
D201
NC
L208
C214
1NH
J200
1
COAX_F
2
22PF
3
L201
C219
4
27nH
5
0.59A
NC
L221
NC
C222
1nF
C223
100pF
C166
C168
100uF 35V
NC
+
+
C169
470nF 25V
D105
PMEG4010EH
C170
DISEQC_OUT
220nF 50V
R165
0R
D107
PMEG4010EH
1
18
NC
GND
5
2
17
GND
VCC
3
16
LX
VBYP
IC116
LNBH25LPQR
4
15
PGND
GND
L114
10UH
5
14
NC
NC
6
13
ADDR
NC
VCC3V3
R166
10K
R169
10uF 35V
R168
R172
C177
100R
R170
10K
15.4k %1
I2C_S_SCL
100R
R173
I2C_S_SDA
2.2K
VCC1V2_FE
VCC2V5_FE
VCC2V5_FE
VCC3V3_FE_SAT
10K
L224
R200
60R
3A
1uF
C252
L200 NC
VCC5V
L223
60R
1nF
C206
3A
C211
43
L222
2.2NF
44
6.8NH
45
C212
46
1uF
47
48
VCC2V5_FE
R203
49
47R
50
R207
5.6PF
2.2K
C248
51
C247
C213
100nF
52
53
C209
BFG425W
100pF
54
2
C215
55
T200
1uF
56
R205
3PF
C208
C254
1.5K
1.2PF
NC
L220
L219
C218
8.2NH
4.7NH
1.2PF
VCC2V5_FE
R208
4.7K
C228
150pF
C229
3.3NF
TP164
D106
PMEG4010EH
VCC12V
L113
60R
3A
C174
220nF 50V
ADDR
SCL
SDA
C176
DSQIN
220nF 50V
I2C Digital core
DETIN
Tone
DSQOUT
detector
DAC
Drop control
Tone ctrl
FLT
Diagnostics
Protections
BPSW
Current
LNBH25
Linear
Limit
Regulator
selection
Voltage
reference
GND BYP
VCC
ISEL
C201
100nF
VCC1V2_FE
C202
100nF
1.2V-> 500mA
C203
100nF
2.5V->170mA
VCC3V3_FE_SAT
3.3V->10mA
VCC1V2_FE
C204
100nF
C205
R213
100nF
4.7K
DISEQC_OUT
DVBS2_RST
SAT_DEMOD_SDA
SAT_DEMOD_SCL
C207
100nF
C210
100nF
28
ITN
GPIO2
R202 NC
27
ITP
XTALSEL0
26
QTP
TSDATA7
25
QTN
TSDATA6
24
AGCIN
TSDATA5
23
RXREG
TSDATA4
22
IC201
RXVDD
TSDATA3
21
CXD2850ER
ATIN
CVDD
VCC1V2_FE
20
RXGND
DVDD
VCC3V3_FE_SAT
19
RFINP
TSDATA2
18
RFINN
TSDATA1
17
RXGND
TSDATA0
16
VREF10
TSCLK
15
RXGND
TSSYNC
C216
100nF
C217
57
EPAD
100nF
C221
1uF
VCC1V2_FE
VCC3V3_FE_SAT
C224
20
C225
100nF
SAT_DEMOD_SDA
C226
SAT_DEMOD_SCL
100nF
C227
100nF
19
1uF
C242
C243
22PF
22PF
L202
L203
60R 3A
VCC2V5_FE
60R 3A
VCC1V2_FE
VCC2V5
VCC1V25S2
C232
C233
10uF 6V3**
10uF 6V3**
LX
PGND
VUP
VOUT
AGC in
AGC in
AGC Out
GPIO
GPIO
I2C
I2C
DiSEqC
DiSEqC
AGC Ctl
LDPC
LDPC
BCH
BCH
ADC
Decoder
Decoder
Decoder
Decoder
8PSK
IF
IF
/QPSK
Demod
Viterbi
Viterbi
RS
RS
ADC
Decoder
Decoder
Decoder
Decoder
0/90
0/90
DIV
DIV
Clk
Status
Status
OSC
PLL
PLL
Monitor
Monitor
CXD2850
PLL
PLL
9
DVBS2_RST
LOW-> RESET
Slave address:
SLVADR0 Low: 0xD0
SLVADR0 High: 0xD2
27
RP200D
1
8
TS1-D7
TS1-D7
2
7
TS1-D6
TS1-D6
3
6
TS1-D5
TS1-D5
4
5
TS1-D4
TS1-D4
TS1-D3
TS1-D3
RP201C
1
8
2
7
TS1-D2
TS1-D2
3
6
TS1-D1
TS1-D1
4
5
TS1-D0
TS1
TS1-D0
TS1
47R
R206
TS1-CLK
TS1-CLK
RP202B
1
8
2
7
TS1-SYNC
TS1-SYNC
3
6
TS1-VLD
TS1-VLD
4
5
26 25 24
C220
NC
RP203C
1
8
TP162
I2CS
2
7
I2C_S_SDA
I2CS
I2C_S_SDA
4
5
I2C_S_SCL
I2C_S_SCL
3
6
TP163
R204
VCC3V3
4.7K
R209
XO
0r
XI
1
3
X200
27MHZ
C230
C231
22pF
22pF
L204
60R 3A
VCC3V3S
VCC3V3_FE_SAT
C234
10uF 6V3**
TS
TS
TS
TS
Output
Output
Control
Control
5
Switch on (trigger: VCC_AUDIO)
9
≤
∞
§
≥
Advertisement
Table of Contents
