Recalibrate Operation - HP 7925D Service Manual

Theory of Operation
cleared by the controller ifit issues a CLS command on the
tag bus with bit 0 active on the control bus.
The stored offset magnitude is converted into an analog
voltage by the digital to analog converter. The amount of
voltage developed can be observed at the test point on
track follower PCA-A5 labeled "DIS". This voltage is
applied through a FET switch to the summing junction of
the output summing amplifier for a negative offset opera-
tion. In the case of a positive offset operation, this voltage
is inverted by a unity-gain inverting amplifier before it is
applied to the summing junction. The output summing
amplifier exhibits a gain of 0.5 to the offset circuit. The
amount of offset is summed into the
pas
signal to cause
the heads to be repositioned. Figure 1-10 illustrates the
heads centered over cylinder 0, positioned over cylinder 0
with maximum negative offset, and positioned over cylin-
der 0 with maximum positive offset.
The heads will remain settled over their present cylinder
position until a seek, recalibrate, or another set offset
command is decoded, or until they are unloaded when the
RUN/STOP switch is set to STOP or a fault condition is
detected.
1-41.
RECALIBRATE OPERATION. A recali-
brate operation is used to move the heads from their pres-
ent cylinder position to a home position over cylinder O.
The controller issues a recalibrate command to establish a
reference head position. The disc drive can execute a
recalibrate command whenever the heads are positioned
and settled over any legal cylinder (ACRY and SB
=
0).
When the command is decoded, the RH signal will become
active (RH
=
0). This will cause the SKH signal to become
active (SKH
=
0) which will initiate a 1667 millisecond
timeout cycle and direct set the seek home flip-flop. The
servo enable flip-flop is not affected. It remains set from
the initial head load operation. The state of the SKH sig-
nal can be observed at the test point on drive control'
PCA-A4 labeled "SKH".
This signal will also cause the CYL signal to become
active (CYL
=
1) to clear the seek check flip-flop on
va
sector PCA-A2. The state of the CYL signal can be ob-
served at the test point on servo PCA-A3 labeled "CYL".
Clearing the seek check flip-flop clears the seek check
status bit (status bit 8
=
0).
In addition, the COF signal will become active (COF = 0)
to clear the offset magnitude and sign registers on track
follower PCA-A5. This will ensure that any offset infor-
mation stored during a previous offset operation will be
cleared out so that it will not affect the positioning of the
heads.
With the seek home flip-flop set (SKH
=
1 and SKH
=
0),
the new cylinder address register and present cylinder
address counter will be cleared by SKH. Since the new
cylinder address and present cylinder address count both
match (both are zero), the MATCH signal will become
1-22
7925
active (MATCH
=
1). The state of the MATCH signal can
be observed at the test point on servo PCA-A3labeled "M".
With the heads currently positioned over the servo zone,
the AGC signal from track follower PCA-A5 will be active
(AGC
=
1). The reset output from the seek home flip-flop
(SKH
=
0) and the presence of the AGC signal (AGC
=
1)
will activate the -slew FET switch. With this switch
closed, a constant velocity will be commanded and an
appropriate current applied to the linear motor coil. This
current command can be observed at the test point on
servo PCA-A3 labeled "CC".
The carriage assembly will slew in reverse at 3.5 inches
per second. When the outside edge of the outer guard band
is first detected by the servo head, the AGC signal will
become inactive (AGC
=
0) to disable the reverse slew
operation. The set output from the seek home flip-flop
(SKH
=
1) and the absence of the AGC signal (AGC
=
0)
will activate the +slew FET switch. With this switch
closed, a forward slew operation will be initiated to re-
verse the movement of the heads.
When the outside edge of the outer guard band is again
detected by the servo head, the AGC signal will become
active (AGC
=
1) to disable the forward slew operation.
The seek home flip-flop will be clocked clear by the leading
edge of the AGC signal. The set output from the seek home
flip-flop (SKH
=
0) together with the absence of the RET
signal (RET
=
0) and the active MATCH + SKI signal
(MATCH + SKI
=
1), activates the fine position FET
switch. With this switch closed, the current applied to the
linear motor coil will be determined by the
pas
signal.
This signal can be observed at the test point on track
follower PCA-A5 (source) or servo PCA-A3 (destination)
labeled
"pas".
During head movement, the ACRY signal will become
inactive (ACRY
=
1). This will cause the drive busy status
bit to become active (status bit 0
=
1); future seek, recali-
brate, or write operations to be inhibited; and the atten-
tion reset flip-flop to be clocked clear to reset the ACRY
attention and retract attention flip-flops (status bit 7
=
0).
Once the track center of cylinder 0 is detected (TCD and
FINE POSITION
=
1), the SB signal will become active
(SB
=
0). This signal will inhibit tachometer feedback to
the head positioning servo loop. The state of the TCD
signal can be observed at the test point on servo PCA-A3
labeled "TCD". After a 1.3 millisecond delay to allow time
for the heads to settle, the ACRY signal will become active
(ACRY
=
0). The drive ready flip-flop is not affected. It
remains set from the initial head load operation.
When the ACRY signal becomes active (ACRY
=
0), it
cancels the 1667 millisecond timeout cycle; causes the
drive busy status bit to be inactive (status bit 0
=
0);
clocks the ACRY attention flip-flop set; and enables future
seek, recalibrate, or write operations. The state of the
ACRY signal can be observed at the test point on drive
control PCA-A4 labeled "ACRY".