HP 7925D Service Manual page 200

Appendix A
With the drive ready flip-flop cleared (DRDY
=
0 and
DRDY
=
1), the DRIVE READY lamp will be extin-
guished, the AGC and carriage back fault detection cir-
cuits will be disabled, the ACRY signal will become inac-
tive (ACRY
= 1),
and the retract attention flip-flop will be
clocked set (status bit 7
=
1).
The state of the DRDY signal
can be observed at the test point on drive control PCA-A4
labeled "DRDY".
The set output from the retract attention flip-flop causes
the attention status bit to be active (status bit 8
= 1),
This
will notify the controller that the disc drive has initiated a
normal head unload operation. This status bit can be
selectively cleared by the controller if it issues a CLS
command.
When the ACRY signal becomes inactive (ACRY
=
1),
future seek, recalibate, or write operations will be inhib-
ited; and the attention reset flip-flop will be clocked set to
prevent the ACRY and retract attention flip-flops from
being reset. The state of the ACRY signal can be observed
at the test point on drive control PCA-A4labeled "ACRY".
With the -slew FET switch closed, a constant velocity will
be commanded and an appropriate current applied to the
linear motor coil. This current command can be observed
at the test point on servo PCA-A3 labeled "CC". This
current will cause the carriage assembly to slew in reverse
at 3.5 inches per second until it reaches its fully retracted
position (CRB
=
1). When this occurs, the RET and CRB
signals will both be active (RET and CRB
=
1). Together
these signals cancel the 1667 millisecond timeout cycle
and clear the servo enable flip-flop to disable the head
positioning servo loop.
In addition, the CRB and STOP signals will clear the run
spindle flip-flop to issue a stop spindle command (RS
=
1).
The door unlock solenoid will be energized
to
permit pack
access as soon as the spindle has been braked to a stop.
The heads will remain in their fully retracted position
until another head load operation is initiated.
A-46. SEEK OPERATION. A seek operation is
used to move the heads from their present cylinder posi-
tion to some other cylinder position. The disc drive can
execute a seek command whenever the heads are
positioned and settled over any legal cylinder (ACRY and
SB
=
0). The controller issues a seek command with a
cylinder address on the control bus. When the command is
decoded, the SK signal will become active (SK
= D.
This
will initiate a 120 millisecond timeout cycle, direct set the
first clock inhibit flip-flop, and clock the cylinder address
(DO thru D9) into the new cylinder address register pro-
vided it is legal (lCA = 0).
The SK signal will also cause the CYL signal to become
active (CYL
=
1)
to
clear the seek check flip-flop on I/O
sector PCA-A2. The state of the CYL signal can be ob-
served at the test point on servo PCA-A3 labeled "CYL".
Clearing the seek check flip-flop clears the seek check
status bit (status bit 3
=
0).
A-18
7925
In addition, the COF signal will become active (COF
=
0)
to clear the offset magnitude and sign registers on track
follower PCA-A5. This will ensure that any offset infor-
mation stored during a previous offset operation will be
cleared out so that it will not affect the positioning of the
heads.
As previously mentioned, the legal cylinder address
supplied by the controller was stored in the new cylinder
address register when the seek command was decoded.
This address provides destination information to the head
positioning servo loop. In addition, the least significant bit
of the new cylinder address (LSB) is routed to track fol-
lower PCA-A5 where it controls the phase switchable
amplifier and the programmable inverter at the input to
the peak detector circuitry. This bit will be active
(LSB
= 1)
for odd cylinders and inactive (LSB
=
0) for
even cylinders. The use of this bit is discussed in detail in
paragraph A-44. Further, the three most significant bits of
the new cylinder address are inverted and routed to
RlW
preamplifier PCA-A6 as the DWA, DWB, and DWC sig-
nals. These signals are used
to
control the programmable
write current sink.
The cylinder address comparator compares the cylinder
address stored in the 'new cylinder address register with
the count stored in the present cylinder address counter. It
produces a lO-bit digital difference from these two addres-
ses. It also produces a signal which indicates whether a
forward or reverse seek operation is required. If the pres-
ent cylinder address is less than the new cylinder ad-
dress, the forward FET switch will be activated and the
present cylinder address counter will count up (POSITIVE
=
1).
If the present cylinder address is greater than the
new cylinder address, the reverse FET switch will be acti-
vated and the present cylinder address counter will count
down (POSITIVE = 0). Both commands (forward or re-
verse) assume that the addresses do not match
(MATCH
=
1), the seek operation is not inhibited (SKI
=
1), a seek home operation is not commanded (SKH
=
0),
and a retract operation is not commanded (RET
=
m.lfthe
present cylinder address is equal to the new cylinder ad-
dress, the fine position FET switch will be activated and
the current applied to the linear motor coil will be deter-
mined by the POS signal.
In the case of a forward or reverse seek operation, the
digital to analog converter converts the digital difference
from the cylinder address comparator into an analog cur-
rent which is applied to the input of the velocity curve
generator. The velocity curve generator produces a cur-
rent equal to a constant multiplied by the square root of
the analog current from the digital to analog converter.
The VC GAIN potentiometer on servo PCA-A3 provides
the means to adjust the seek time by varying the gain of
the velocity command. The velocity command can be ob-
served at the test point on servo PCA-A3 labeled "VC". If
the reverse FET switch is activated, the velocity command
will be routed to the summing junction of the summing
amplifier. If the forward FET switch is activated, the ve-
locity command will be inverted by a unity-gain, inverting
amplifier before it is applied to the summing junction. The