Pciexpress Root Port Function - JETWAY 945PLDAS User Manual

SDRAM RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T and 3T.

PCIExpress Root Port Function

Please refer to section 3-6-1
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
Video BIOS Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result. The settings
are: Enabled and Disabled.
Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area of
system memory usually discusses their memory requirements. The settings are: Enabled and
Disabled.
3-6-1 PCIExpress Root Port Function
PCIExpress Compliancy Mode
↑ ↓ → ←
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
Phoenix – AwardBIOS CMOS Setup Utility
PCIExpress Root Port Function
v1.0a
F6:Optimized Defaults
Menu Level >>
F7:Standard Defaults
35
Item Help
F1:General Help