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CHAINTECH 9SJD Manual page 11

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Chapter 2
Pin
Definition
1~2
Normal (default)
2~3
Clear CMOS Data
Pin
Definition
1~2
Disable (default)
2~3
Enable
Pin
Definition
1~2
Disable (default)
2~3
Enable
Pin
Definition
1~2
Enable
2~3
Disable
JP24 (Default 100/133MHz)
CPU
SDRAM
A
100
100
1~2
100
133
1~2
100
160
2~3
8
B
C
D
E
2~3
2~3
2~3
2~3
1~2
2~3
2~3
2~3
1~2
1~2
2~3
2~3
or
SW1 (Default 100/133MHz)
CPU
SDRAM
100
100
100
133
100
160
1
2
3
4
OFF
ON
ON
ON
OFF
OFF
ON
ON
ON
OFF
OFF
ON
5
ON
ON
ON

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