Vertex Standard VX-351PMR446 Service Manual page 7

3-2. Drive and Final amplifier
The modulated signal from the VCO Q1049 (Q3049)
(2SC4227) is buffered by Q1042 (Q3042) (2SC5005) and
amplified by Q1031 (Q3031) (2SC5005). Then the signal is
buffered by Q1026 (Q3026) (2SC5998) for the final amplifi-
er driver Q1020 (Q3020) (RD01MUS1). The low-level trans-
mit signal is then applied to Q1013 (Q3013) (RD09MUP2)
for final amplification up to 0.5 watts output power. The trans-
mit signal then passes through the antenna switch D1002
(D3002) (HVU131) and is low pass filtered to suppress away
harmonic spurious radiation before delivery to the antenna.
3-3. Automatic Transmit Power Control
The current detector Q1064-1 (Q3064-1) (BA2902) detects
the current of Q1013 (Q3013) and Q1020 (Q3020), and con-
verts the current difference to the voltage difference. The out-
put from the current detector Q1064-1 (Q3064-1) is compared
with the reference voltage and amplified by the power control
amplifier Q1064-2 (Q3064-2). The output from Q1064-2
(Q3064-2) controls the gate bias of the final amplifiers Q1013
(Q3013) and the final amplifier driver Q1020 (Q3020). The
reference voltage changes into four values (Transmit Power
High and Low) controlled by Q1017-CH7 (Q3017-CH7)
(M62364FP).
4. PLL Frequency Synthesizer
The frequency synthesizer consists of PLL IC, Q1059 (Q3059)
(SA7025DK), VCO, TCXO (X1002 (X3002)) and buffer am-
plifier.
The output frequency from TCXO is 16.8MHz and the toler-
ance is ±2.5 ppm (in the temperature range –25 to +55 degrees).
4-1. VCO
While the radio is receiving, the RX oscillator Q1046 (Q3046)
in VCO generates a programmed frequency between 395.15625
and 395.24375 MHz as 1st local signal. While the radio is trans-
mitting, the TX oscillator Q1049 (Q3049) in VCO generates a
VX-351PMR446 Service Manual
Circuit Description
frequency between 446.00625 and 446.09375 MHz. The out-
put from oscillator is amplified by buffer amplifier Q1042
(Q3042) and becomes output of VCO. The output from VCO
is divided, one is amplified by Q1052 (Q3052) and feed back
to the PLL IC 5pin. The other is amplified in Q1031 (Q3031)
and in case of the reception, it is put into the mixer as the 1st
local signal through D1019 (D3019), in transmission, it is buff-
ered Q1026 (Q3026), and more amplified in Q1020 (Q3020)
through D1019 (D3019) and it is put into the final amplifier
Q1013 (Q3013).
4-2. PLL
The PLL IC consists of reference divider, main divider, phase
detector, charge pumps and fractional accumulator. The refer-
ence frequency from TCXO is inputted to 8pin of PLL IC and
is divided by reference divider. This IC is decimal point divid-
ing PLL IC and the dividing ratio becomes 1/8 of usual PLL
frequency step. Therefore, the output of reference divider is 8
times of frequencies of the channel step. For example, when
the channel stepping is 6.25 kHz, the output of reference divid-
er becomes 50 kHz. The other hand, inputted feed back signal
to 5 pin of PLL IC from VCO is divided with the dividing ratio
which becomes same frequency as the output of reference di-
vider. These two signals are compared by phase detector, the
phase difference pulse is generated. The phase difference pulse
and the pulse from fractional accumulator pass through the
charge pumps and LPF. It becomes the DC voltage to control
the VCO. The oscillation frequency of VCO is locked by the
control of this DC voltage. The PLL serial data from CPU is
sent with three lines of SDO (64 pin), SCK (1 pin) and PSTB
(32 pin). The lock condition of PLL is output from the UL (18
pin) terminal and UL becomes "H" at the time of the lock con-
dition and becomes "L" at the time of the unlocked condition.
The CPU always watches over the UL condition, and when it
becomes "L" unlocked condition, the CPU prohibits transmit-
ting and receiving.
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