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-V126R
CIRCUIT DESCRIPTION
Block diagram
TIOO
PTOO/P20 ©
THO
PTO1/P210
SI/PO3 O
$O/P02 O
SCK/PO10
INTO/P10 0
INT1/P110
INT2/P12 0
INT3/P13 ©
INT4/P00.0
PTHOO—PTHOS =
14
(__) BIT SEQ.
BUFFER(16)
(Trent ro
(|
ports
| (4 | P10—P13
BASIC
INTERVAL
TIMER
PROGRAM
INTBT
COUNTER
(13)
TIMER/EVENT
COUNTER
#0
BANK
co)
(Nor (rn
TIMER/EVENT
(cua
PORT 3
("4 ) P30-P3s
COUNTER
U
GENERAL REG.
#1
ROM
(ror KZ) ror
(_)
PORT 5
(4) p50-Ps3
oy
PORT 8
(4 )Pao-Pes
INTERRUPT
fx/2N
INTT1
PROGRAM
DECODE
AND
CONTROL.
MEMORY
SERIAL
INTERFACE
8064X8 BITS
DATA MEMORY
§12x4 BITS
CLOCK
CPU CLOCK
area
OUTEMT
BIviDER
GENERATGA
CONTROL
i
SEES
Va)
FONTROE
oa
PORT 13 (4 )P130-P123
THRESHOLD
we
t |
Vek, obs.
PCL/P22
X2
Xt
Vpp
Vss
RESET
'Se
PORT 14
(4) P140-P143
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