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Read. In down.
Whenever the byte
register contains an even number of
"I" data bits, a parity generator
automatically turns on DIP.
Odd
parity is, therefore, checked.
Par-
ity is not checked at" the drive to
ensure that there is not a Data
Parity Error.
e. The 8 Bits Processed FF sets •. This
sets the Read SRI FF.
f. Serial Read In is raised to the con-
troller to indicate that data (10
byte) on the bidirectional data lines
is valid.
11. When the controller accepts the infor·
mation, it raises Serial Write Out.
12. The drive drops Serial Read In until
the next 8 Bits Processed.
13. The Serial Read In/Serial Write Out
dialog continues without interruption
until the controller drops DeS.
Note that the first byte, the sync byte, is
recognized by SEROES but does not generate
SRI.
Only the ID byte and all subsequent
data bytes are transferred.
If the controller is late in raising Serial
Write Out another data byte could
be
loaded
into the byte register before the resident
byte is accepted.
If this happens, Transfer
Timing Error (bit 21 of OSl) is generated to
raise FLT.
This FLT does not, in itself,
terminate the read operation.
Serdes During A Read Header (ROH)
A Read Header (ROH) command is identical to
Read, except that data cannot be returned
to the controller until an address mark is
detected prior to the sync byte.
Except as specified herein, SEROES works in
the identical manner for both Read and Read
Header.
Assume that the read head is reading the in-.
ter-record gap of zeros.
The controller
raises Read Header and Device Command Strobe.
Sequencing is as follows:
1. Because Read Header does not generate
the Resync Pulse used to initiate Fast
Start (Figure 3-51) that signal is not
available.
(It timed out following
the last Read Enable).
2. The Data Good Enable FF remains reset
since there is no Not Fast Start edge
to toggle the FF.
Data Good cannot set
if the controller inadvertently raised
RDH preceding a record field without
an address mark.
8331S200
A
3. With both the Data Good FF and Data Good
Enable FF cleared.
Search Address Mark
is- raised to the level Time Constant
Co~trol
circuit (Figure 3-49).
4. Nothing of further consequence happens
until the address mark gap (transition-
less area) is sensed.
Delay
YS08
(Fig-
ure 3-51) can then time out.
s.
When the first MFM Clock of the sync
field is sensed, the resulting X pulse
retriggers
Y808
which,
in
turn, triggers
Fast Start single shot
Y806.
Fast Start
is up for 5 microseconds.
6. With Fast Start up, Search Address Mark
is disabled.
7. After about 4 bytes of the 12 byte sync
field (all zeros), Fast Start drops.
S. The Data Good Enable FF sets to permit
the Data Good FF to set when the hex 19
of the sync byte is loaded into SEROES.
The remaining operation of Read Header is
identical to the Read operation already
explained.
SENSE OPERATIONS
GENERAL-
Sense operations permit the controller to
determine drive status.
SUMMING STATUS REQUEST (SSRJ
The SSR command causes the transfer of one
byte of data from the drive to the controller.
This command does not require a previous
Seize command.
It is decoded directly off
of the command lines without passing through
the normal command decode logic.
The only
requirement is that the drive be online. The
meanings of each bit in the SSR dialog are
explained in Table 3-4 (Commands).
Two separate Summary Status Registers are
provided within the drive: one for each con-
troller.
Current status is loaded from the
logic into the applicable register when the
SSR command is decoded.
The register is
gated to the DLI transmitters followed by a
Serial Read In to indicate that the data is
valid.
SSR status may also be determined during
maintenance by setting the DISPLAY SELECT
switch on the maintenance panel to SSR. This
gates the status information (while bypass-
ing the Summary Status Register) to the dis-
play indicators.
Bit 28 (not used), bit 27
(Device Reserved), and bit 26 (Device Seized)
indicators are a.lways off.
Data placed on
the bidirectional data lines is applied to
3-103
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