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line.
The Data Strobe pulses are used to
toggle the Data Sense
FP.
The nominal strobe
is
a
delayed data pulse.
The strobels re-
lative position with respect to the data
window is adjusted for
maximwD
data recovery.
A -1-
is reoc;tcJDizecl-if strbbe occurs while
the
Data Window
FP
is set.
Early or late
strobes may
be
varied from the naminal. strobe
time by a collllllADd from
the
controller
(Ad-
vance
or Retard
Read Check)
or
the
setting
of a switch on the loqic chassis maintenance
panel.
This feature allows recovery of data
which may
be
out of position on
the
disk
relative to the average
data
position.
The shift pulses are narrow pulses which
occur once each cell time.
'rhese pulses
initialize the Data Sense
FF
and shift the
contents of the Data Sense
FF
into the Data
Register
PF.
The Shift pulses also initial-
ize the Clock register
FP.
The Reset pulses also
occur
once
per
cell
period.
'rhey initialize the Data Regiscer
FP
and toggle the Clock Register
PT.
As
shown
in
Fiqure 3-52), the Sh1ft
and
Reset
pulses control the timing of the output wave-
forms of the data sepaJ:'ator circuit.
Note
that the window is delayed beyond the Shift
pulse so that the Data Sense FF is always
ready to accept a Data Strobe pulse.
The Data Sense FF is toggled whenever a Data
Strobe occurs durinq the data window time
(Data Window FF set) of a cell period.
The
next Shift pulse would then transfer the
data
"1-
from the Data Sense FF to the Data
reqister FF.
Note in Fiqure 3-52 that the
data "1" is actually transmitted to SERDES
almost one cell time after it is detected.
SERDES Oeserializer
SERDES (figure 3-53) is used during Read
operations to convert serial information
read from the disk into parallel (byte)
information for transmission to the con-
troller.
Serdes During Read (RDX)
In order to understand the operation of this
circuit, assume that Read Enable is up (On
Cylinder and Not Write) and that the drivel
controller interface is not yet communicat-
ing.
The earlier stages of the read circuit
are operational: data pulses are available
from the data latch circuit and the PLQ is
providing read clock.
SERDES itself is in-
hibited because Read Gate is down.
The bit
counter contains a count of zero.
The heads are senSing the bytes of zeros in
the inter-record gap and the controller
raises Read and Device Command Strobe Se-
quencing is then as follows:
3-100
1. Read Gate is qenerated.
2. The rise of Device Command Strobe drops
the bit counter reset.
The bit counter
counts to one.
Then, because of Count
Inhibit, it is f:ozen.
3. Data
from
the data separator circuit
triggers single shot A625.
Data is
loaded into SERDES at the trailing edge
of each read clock from the
data
separa-
tor
circuit.
The remaining steps cannot occur
for at least
5
microseconds follow-
ing the rise of Read.
This is the
Fast Start timeout
to
allow full
frequency/phase synchronization.
4. After 5 microseconds, Fast Start drops
aDd the Data
Good
Enable
FP
sets.
Note
that S.-arch Address
Mark
is
NO'r
enabled.
5. The zeros pattern continues to be loaded
into
SERDES.
6. Eventually, the sync byte of hexadecimal
19 (0001 1001) beqins to enter SERDES.
See Fiqure 3-54 for timing.
7. When the sync byte is fully loaded, the
Hex 19 Detect FF sets.
8. The Data
Good
FF sets.
Count Inhibit
drops.
9. The bit counter starts counting
~rom
one
as the sync byte is shifted out of
SEaCES.
This byte cannot enter the byte reqister.
The ID byte (also hex 19) begins to
enter
~ERDES.
10. When
the
counter reaches a count of
eight, and at the trailing edge of read
clock:
a. The 10 byte is transferred from SERCES
to the byte register.
b. The first bit of the first data byte
is loaded into SERDES.
(This does
not affect the byte transferred to
the byte register because SEReES
contains edge-triggered devices. The
10 byte is transferred out before
the next incoming data biS can be
reflected in the SEROES 2
output.)
c. The bit counter is reset to one.
d. The output of the byte register is
applied to the bidirectional data
lines via the multiplexer as long as
Read Gate is up.
The data on these
lines has no validity with Serial
83318200
A
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