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s.
The track servo circuit is generating
the 806 kHz machine clock.
This clock
is generated by dibits read from the
servo track
7
therefore, variations
in
spindle motor speeds do not affect re-
cording density.
This basic clock is
used to form the
6.44
MHz write clock.
6.
The write clock controls a counter
wtW:h,.
in turn,
controls the shift register
function of SERDES.
Data is shifted
out of SERDES (deserialized) with each
wri te clock so that the information on
Bidirectional Data
Line
27 is written
first and 20 written last. .
7. Data· shifted from SERDES" which is
NRZ
(Non-Return to Zero), is converted. to
MFM.
Actual phasing to compensate for
peak shifting during subsequent read
operations is controlled by a write
compensation circuit.
8. If the controller has raised the Data
Modifier Line, SERDES is ic;noredand
all writing is inhibited.
9.
The
MFM
pulses are sent to the write .
driver circuits which supply the ne-
cessary current
~o
the write coil.
10. When a byte has been written,
8
Bits
Processed comes up to load the next
byte from
the
bidirectional data lines
and to drop Serial Read
In.
The Serial Write Out/Serial Read
In
sequenc-
ing continues for each byte written.
Device
Command Strobe and 1me command must remain
up until the write operation is to be term-
inated.
S.,des Serialize,
In order to understand the operation of tnis
circuit, assume that the drive is in the
process of writing byte "N".
Serial Read In
is up, Serial Write Out is down, and data
for byte "N+l" is on the bidirectional data
lines.
See Fiqure 3-41.
Sequencing is then
as follows:
•
Data is shifted from SERDES to the write
compensation circuit with the leading
edge of each write clock.
Refer to
Write Compensation for information on
the NRZ/MFM conversion process.
•
As data is shifted, the bit counter is
also incrementing with write clock.
It
normally begins counting from a count
of one: however, it starts from zp.ro
when Write is first enabled (writing
the zeros gap).
3-82
e
'!'he bit counter contains a value of
8
as
the last bit from byte "N" (originatinq
from 017 of the bidirectional data
lines)
is being shifted out.
e
If SRI
had
already dropped, or if Serial
Write OUt was still up, Transfer Timinq
Error (bit 21 of DS1) raises FLT to the
controller.
•
At the trailing edqe of the next write
clock:
a. Data for byte "N+l" is loaded into
SERDES from the bidirectional data
lines.
b.
The Write SRI-B
FF
toggles to the
cleared state.
Two flip-flops, Write
SlU-A and Write SRI-B, are connected
to an exclusive-oR qate.
They raise
Serial Read
In
whenever they are in
opposite states.
As each byte is
processed, toggling SlU";A raise
Serial
Read
In
while toggling SlU-B drops
Serial
Read
In.
In this case, with
Write SRI-A and W1:ite SRI-B
both
down, Serial Read
In
is 4ropped to
the controller.
This sic;nifies to
the controller that it may remove
data from the bidirectional
data~.
c. The bit counter is reset to one.
•
The data in SERDES is· shifted" out, one
at a time, with each clock.
•
While byte "N+l" is being written, the
controller places data for byte "N+2"
on the bidirectional data lines.
It
then raises Serial Write Out.
•
With Serial
W~ite
Out up, Write SRI-A
FF
toggles to the set state.
The re-
quirements of the exclusive-OR gate are
again met to raise Serial Read In.
If
Serial Write Out is late
(8
Bits Pro-
cessed generated before the controller
gets around to raising Serial Write Out.
Transfer Timing Error is generated.
•
The controller drops Serial Write Out
in response to the rise of Serial Read
In.
Parity of the data on the bidirec-
tional data lines is checked at this
tLme.
If parity is not odd, Data Parity
Error (bit
20
of OSl) is generated to
raise FLT to the controller.
This error
does not directly stop the writing pro-
cess.
The drive loqic will continue to
write garbage until the controller drops
Device Command Strobe.
Parity bits,
although checked by the I/O, are not
written on the pack.
83318200
A
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