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Q7 Pin
LVDS_A0_P
LVDS_A0_N
LVDS_A1_P
LVDS_A1_N
LVDS_A2_P
LVDS_A2_N
LVDS_A3_P
LVDS_A3_N
LVDS_A_CLK_P
LVDS_A_CLK_N
LVDS_B0_P
LVDS_B0_N
LVDS_B1_P
LVDS_B1_N
LVDS_B2_P
LVDS_B2_N
LVDS_B3_P
LVDS_B3_N
LVDS_B_CLK_P
LVDS_B_CLK_N
The LVDS A pins are muxed between MIPI_TX0 and eDP on the Module. The active function is selected with a
GPIO pin.
In addition to the Qseven edge connector there is an additional MIPI-CSI port accessiable via the MIPI-CSI
feature interface.
Signal
CAM_PWR
CAM0_CSI_D[0:3]+ CAM0_CSI_D[0:3]-
CAM0_CSI_CLK+ CAM0_CSI_CLK-
CAM0_I2C_CLK
CAM0_I2C_DAT
CAM0_RST#
CAM0_ENA#
MCLK
CAM[0:1]_GPIO
v1.6
Page 34
Function
MIPI_TX0_D0P
MIPI_TX0_D0N
MIPI_TX0_D1P
MIPI_TX0_D1N
MIPI_TX0_D2P
MIPI_TX0_D2N
MIPI_TX0_D3P
MIPI_TX0_D3N
MIPI_TX0_CLKP
MIPI_TX0_CLKN
MIPI_TX1/RX1_D0P
MIPI_TX1/RX1_D0N
MIPI_TX1/RX1_D1P
MIPI_TX1/RX1_D1N
MIPI_TX1/RX1_D2P
MIPI_TX1/RX1_D2N
MIPI_TX1/RX1_D3P
MIPI_TX1/RX1_D3N
MIPI_TX1/RX1_CLKP
MIPI_TX1/RX1_CLKN
Function
CPU Pin
LVDS A Mux
GPIO2_A2
LVDS A Mux
Function
0
MIPI
1
eDP
Type
Signal Level
P
3.3V
I
D-PHY
I
D-PHY
I/O
1.8V
I/O
1.8V
I/O
1.8V
I/O
1.8V
O
1.8V
I/O
1.8V
Alternate Function
EDP_TX0_P
EDP_TX0_N
EDP_TX1_P
EDP_TX1_N
EDP_TX2_P
EDP_TX2_N
EDP_TX3_P
EDP_TX3_N
EDP_AUX_P
EDP_AUX_N
Linux GPIO #
34
Description
3.3V supply to power the camera
CSI2 Camera 0 Data Lane differential pairs
CSI2 Camera 0 Clock Lane differential pairs
CSI2 Camera 0 Control Interface Clock
CSI2 Camera 0 Control Interface Data
CSI2 Camera 0 Reset (low active)
CSI2 Camera 0 Enable (low active)
CSI2 Camera 0 Master Clock
GPIO for Camera
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