Cherry PUMA SOM-RK3399-Q7 User Manual page 37

5.4.4 I2C
Signal Type
Q7_I2C_CLK O
Q7_I2C_DAT I/O
LVDS_DID_CLK O
/GP2_I2C_CLK
LVDS_DID_DAT I/O
/GP2_I2C_DAT
SMB_CLK O
GP1_I2C_CLK
SMB_DAT I/O
GP1_I2C_DAT
LVDS_BLC_DAT O
LVDS_BLC_CLK I/O
5.4.5 I2S
Signal Type
I2S_RST# O
I2S_WS O
I2S_CLK O
I2S_SDO O
I2S_SDI I
5.4.6 HDMI
Signal Type
TMDS_CLK+ O
TMDS_CLK-
TMDS_LANE[0:2]+ O
TMDS_LANE[0:2]-
HDMI_CTRL_CLK O
HDMI_CTRL_DAT I/O
HDMI_HPD# I
5.4.7 Video
The RK3399-Q7 does not feature LVDS as the CPU lacks this interface. Instead the Qseven LVDS pins are used
for MIDI-DSI. These signals are electrical compatible but are not defined in the Qseven standard.
RK3399-Q7 User Manual
© Cherry Embedded Solutions GmbH
Signal Description
Level
3.3V I2C bus clock line connected to RK3399
3.3V I2C bus data line connected to RK3399
3.3V I2C bus clock line connected to RK3399
3.3V I2C bus data line connected to RK3399
3.3V Clock line of System Management Bus. Alternate function I2C
Bus clock line
3.3V Data line of System Management Bus. Alternate function I2C
Bus data line
3.3V I2C bus clock line connected to RK3399, Kerkey and baseboard
EEPROM
3.3V I2C bus data line connected to RK3399, Kerkey and baseboard
EEPROM
Signal Description
Level
3.3V I2S Codec Reset
3.3V I2S Word Select
3.3V I2S Serial Data Clock
3.3V I2S Serial Data Output
3.3V I2S Serial Data Input
Signal Description
Level
TMDS TMDS differential pair clock lines
TMDS TMDS differential pair lanes 0, 1, 2
3.3V DDC based control signal (clock) for HDMI device
3.3V DDC based control signal (data) for HDMI device
3.3V Hot plug detection signal
v1.6
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