Texas Instruments ADS5400EVM-CVAL User Manual page 10

Circuit Description
2.2.3.1 Analog Input Option 1
Option 1 supplies the transformer coupled input from J1 to ADC. This configuration is the default on the
EVM. The test result using this option is shown in
The transformer footprint used on the ADS5400EVM-CVAL is flexible to accommodate either transformers
or baluns from several suppliers. If baluns are installed, then the signal must be AC coupled to the
ADS5400HFS/EM so that the common-mode biasing circuits in the input may bias the signal to the
desired common-mode level. AC coupling capacitors C128 and C129 on the EVM serve this purpose. By
default, a dual balun (Minicircuits ETC1-1-13) is installed on the ADS5400EVM-CVAL. Depending on the
input frequency to be evaluated, it may be desirable to select a different transformer or balun component
more suited to a particular frequency range.
2.2.3.2 Analog Input Option 2
Option 2 allows the use of a differential input applied to two SMA connectors, and the differential input
signal then bypasses the transformer coupling. By default, the SMA connector for the negative side of the
differential input is not assembled on the EVM and must be added before this option is used. By default,
component L25 is assembled with a 0-ohm jumper resistor to steer the positive side of the differential
input to the transformer input. This 0-Ω resistor must be moved from component location L25 to
component location R55 to steer the signal around the transformer coupling. Then the 0-Ω resistors R25
and R26 must be removed and installed instead in locations R39 and R40. This completes the differential
path from J1 and J2 to the analog inputs of the ADS5400HFS/EM.
2.2.4 Digital Outputs
The LVDS digital outputs can be accessed through the J4 output connector. A parallel 100-Ω termination
resistor must be placed at the receiver to properly terminate each LVDS data pair. These resistors are
required if the user wants to analyze the signals on an oscilloscope or a logic analyzer. The ADC
performance also can be quickly evaluated using the TSW1200 boards as explained in next section.
2.2.5 Sync Input
The ADS5400HFS/EM analog-to-digital converter device features a Reset input pin that may also be
referred to as a Sync input pin, depending on the mode of operation of the device. When the LVDS output
clock for the ADS5400HFS/EM is operating in DDR mode, it may be desirable to reset the output clocking
circuitry to put the phase of the DDR clock in a known position, particularly if multiple ADS5400HFS/EM
devices are to be synchronized. Also, a pulse on the Reset/Sync input pin results in a SYNCOUT output
pulse if SYNC mode is enabled.
Because the ADS5400EVM-CVAL has a single ADS5400HFS/EM device installed on it, it is unnecessary
to use the Reset/Sync input for normal evaluation, and the TSW1200 does not require the Reset/Sync pin
to be used. Nevertheless, the ADS5400EVM provides mechanisms for using the Reset/Sync input.
The default configuration of the ADS5400EVM-CVAL provides for switch SW1 to assert a reset pulse to
the Reset/Sync input pin. An LVDS buffer device converts the pulse from the switch to a differential input
to the ADS5400HFS/EM. Because the switch SW1 is not synchronized to the sample clock at all, setup
and hold timings between the resulting reset input and the sample clock cannot be ensured. Switch SW1
is simply a way to assert the signal to see what effect the Reset/Sync input may have on the device.
Pressing switch SW1 may have about a 50% probability of inverting the phase of the LVDS DDR output
clock
The Reset/Sync input may be used as a periodic SYNC input that causes a SYNCOUT output signal
useful for synchronizing the sample data across multiple data converters or to some external event. The
SYNC input in this case must meet setup and hold timing relationships relative to the input sample clock.
To facilitate this mode, the ADS5400EVM-CVAL has an SMA input J13 (normally not installed) that is
converted to differential by transformer coupling to the Reset/Sync input pins in a path that is matched
both in schematic and layout with the sample clock input path. Thus, if clock and sync signals are
generated and synchronized externally, then the ADS5400EVM preserves their timing relationship up to
the input pins of the ADS5400HFS/EM. To enable the transformer-coupled SYNC input from J13, resistors
R30 and R33 are to be removed and AC coupling capacitors C66 and C71 are to be installed.
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ADS5400EVM-CVAL
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Figure 4.
Copyright © 2012, Texas Instruments Incorporated
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SLAU471 – December 2012
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