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MCIO17 Pin Definition (CPU1 P0 [7:0])
Pin
Defeinition
A1
GND
A2
RX_DP7
A3
RX_DN7
A4
GND
A5
RX_DP6
A6
RX_DN6
A7
GND
A8
BP_TYPE
A9
WAKE#
A10
GND
A11
DP1
A12
DN1
A13
GND
A14
RX_DP5
A15
RX_DN5
A16
GND
A17
RX_DP4
A18
RX_DN4
A19
GND
A20
RX_DP3
A21
RX_DN3
A22
GND
A23
RX_DP2
A24
RX_DN2
A25
GND
A26
BP_TYPE
A27
WAKE#
A28
GND
A29
DP2
A30
DN2
A31
GND
A32
RX_DP1
A33
RX_DN1
A34
GND
A35
RX_DP0
A36
RX_DN0
A37
GND
75
NP_NC_1
77
PGND_1
79
PGND_2
Pin Defeinition
B1
GND
B2
TX_DP7
B3
TX_DN7
B4
GND
B5
TX_DP6
B6
TX_DN6
B7
GND
B8
SCL1
B9
SDA1
B10
GND
B11
PERST_BUF1_N
B12
PRSNT_N
B13
GND
B14
TX_DP5
B15
TX_DN5
B16
GND
B17
TX_DP4
B18
TX_DN4
B19
GND
B20
TX_DP3
B21
TX_DN3
B22
GND
B23
TX_DP2
B24
TX_DN2
B25
GND
B26
SCL2
B27
SDA2
B28
GND
B29
PERST_BUF2_N
B30
PRSNT_N
B31
GND
B32
TX_DP1
B33
TX_DN1
B34
GND
B35
TX_DP0
B36
TX_DN0
B37
GND
76
NP_NC_2
78
PGND_3
80
PGND_4
GENOA2D24G-2L+
47
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