Quick Start Procedure - Linear Technology DC2222A Demo Manual

DEMO MANUAL DC2222A

Quick start proceDure

Table 1. DC2222A Assembly and Clock Options
ASSEMBLY U1 PART
VERSION NUMBER
DC2222A-B LTC2508IDKD-32
.
DC2222A-C LTC2512IDKD-24
Check to make sure that all jumpers are set as described
in the DC2222A Jumpers section. In particular, make sure
that VCCIO (JP3) is set to the 2.5V position. Controlling
the DC2222A with the DC890 while JP3 of the DC2222A
is in the 3.3V position will cause noticeable performance
degradation in SNR and THD. The default jumper con-
nections configure the ADC to use the onboard reference
and regulators. The analog input is DC coupled by default.
Connect the DC2222A to a DC890 USB High Speed Data
Collection Board using connector P1. (Do not connect a
PScope controller and QuikEval controller at the same
time.) Next, connect the DC890 to a host PC with a stan-
dard USB A/B cable. Apply ±9V to the indicated terminals.
Next apply a low jitter differential sine source to J2 and J4.
Connect a low jitter 2.5V
P-P
connector J1, using Table 1 as a guide for the appropriate
clock frequency. Note that J1 has a 49.9Ω termination
resistor to ground.
Run the PScope software (PScope.exe version K86 or
later) supplied with the DC890 or download it from www.
linear.com/software.
Complete software documentation is available from the
Help menu. Updates can be downloaded from the Tools
menu. Check for updates periodically as new features
may be added.
2
MAX OUTPUT
DATA RATE DF
3.472ksps 256
2.900ksps 256
3.906ksps 256
3.906ksps 256
900ksps 1
350.877ksps 4
303.03ksps 4
400ksps 4
400ksps 4
1.5Msps 1
sine wave or square wave to
MAX CLK IN
BITS FREQ OUTPUT
32 80MHz A
32 75MHz A
32 43MHz A
32 45MHz A
14 90MHz B
24 80MHz A
24 80MHz A
24 62.4MHz A
24 70.4MHz A
14 85.5MHz B
The PScope software should recognize the DC2222A
and configure itself automatically. The default setup is to
read the filtered output with Verify and Distributed Read
not selected and the Down Sampling Factor (DF) set to
the smallest possible value. To change this, click on the
Set Demo Bd Options setting of the PScope Tool Bar as
shown in Figure 2. The Configuration Options box shown
in Figures 3a and 3b allows the ADC output, DF , Verify and
Distributed Read to be set. If Verify is not selected then
the minimum number of bits will be clocked out. If Verify
is selected the number of bits clocked out is increased
by eight which includes the number of samples taken
for the current output. Distributed Read allows a slower
clock to be used by spreading the data clocked out over
a number of samples. DF can be set over a wide range
which is determined by the device in use. Increasing DF
will improve the SNR. Theoretically, SNR will improve by
6dB if the down sampling factor is increased by a factor
of four. In practice, reference noise will eventually limit the
SNR improvement. Increasing the REF bypass capacitor
(C20) or using a lower noise external reference will extend
this limit.
Click the Collect button (See Figure 4) to begin acquiring
data. The Collect button then changes to Pause, which
can be clicked to stop data acquisition.
MODE DIVIDER
No Verify 90
Verify 101
Distributed Read 43
Verify + Distributed Read 45
100
No Verify 57
Verify 66
Distributed Read 39
Verify + Distributed Read 44
57
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