Circuit Explanations; Address Selection - Casio I/O-PB-11 Service Manual

3. CIRCUIT EXPLANATIONS

3-1. Address selection

+12V
+
C7
-12V
1
GND
GND
2
GND
2
3
IRQ
4
GND
R2
5
WR
6
GND
R1
7
RD
GND 8
D7
A7 9
10
GND
11
D6
GND 12
D5 13
14
GND
D4 15
GND 16
D3 17
-12V
18
D2 19
-12V 20
D1
21
12V
22
D0 23
12V
24
C1 C6
+
R9
1
A3
2
GND
R8
3
A2
4
GND
R7
5
A1
6
GND
R6
7
A0
8
GND
9
VCC
10
VCC
R5
11
IOCS
12
VCC
R4
13
RESET
14
VCC
R3
15
E
16
VCC
VCC
According to the address of main CPU, the decorder selects the following optional devises.
IC No. Pin No.
IC17 4
10
IC14 11
IC15 6
V+
V-
IC14
1
3 3
2
IC1
IC4
2
3
IC4
IC14
4 4
5
6
5
IC14
9
8
10
D7
C30
D6
C29
D5 GND
D4
D3
D2
-12V
D1
D0
+12V
IC1
IC5
IC12
7 6 5
5 6
4
6
IC15
1
IC4
4 2
5
4
8
IC4
10 5
7 6 9
IC15
IC12
IC4
9 10
C8
C9
IC4
C10
12
11
C11
IC1
IC15
12
10
9
11
13
IC4
14 15
IC12
2
1
C23
3
GND
CPU address
1Y0 0034H & RD="L" RDTM gate enable of IC8 (For scale data read)
2Y2 0036H
CLK 0034H & WR="L" Clock signal of IC9 (For C-In line controller data)
CS 0030H
0031H
IC17
VCC
1 16
1G VCC
2 15
1A 2G
3 14
1B 2A
4 13
1Y0 2B
5 12
1Y1 2Y0
6
11
1Y2 2Y1
7
10
1Y3 2Y2
8
9
GND 2Y3
C31
GND
R27
C33
GND
D2
IC15
9
3
D3
8
10
GND
D4
C37
D5
D6
GND
D7
R10
R26
VCC
R25
Descriptions
Chip selection of C-In line controller
Chip selection of USART (Data)
Chip selection of USART (Control status)
— 8 —
CS for IC10
(C-In line controller)
IC12
11
13
IC14
12
12
11
13
CLK for IC9
RDTM
C32
IC16
VCC
1 16
Q12 VCC
2 15
Q6 Q11
3 14
Q5 Q10
4 13
Q7 Q8
5 12
Q4 Q9
6
11
Q3 RST
7
10
Q2 CLK
8
9
GND Q1
C36
GND
USART
IC7
1 28
D1
D2 D1
2 27
D0
D3 D0
3 26
VDD
RXD
4 25
GND RXCLK
5 24
D4 DTR
6 23
RTS
D5
7 22
D6 DSR
8 21
RESET
D7
9 20
CLK
TXCLK
10 19
WR TXD
11 18
TXEMP
CS
12 17
C/D CTS
13 16
RD SYNC
14 15
TXRDY
RXRDY
R11