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vol scription
Input for CLV error signal from DSP.
Output for RF
For setting RF gain and 3T compensation constant together with RFSM
SLICE LEVEL CONTROL; output for controlling the data slice level of DSP with
RF waveform.
Pin Name
w 'oO
Q
ii
Vv
RFSM
Q
+
ie)
w
SLC
SLI
D-GND
FSC
Input for controlling the data slice level of DSP
GND for digital system.
Output pin for focus search smoothing capacitor
wm
ima)
aa)
io)
(Tracking Balance Control) EF balance variable range setting pin
49
DEF
Output for disk defect detection.
50
|
cK
Standard clock input; DSP's 4.23MHz is inputted.
Clock input for microcontroller command.
Data input for microcontroller command.
Ee
aa
ee
Chip-enable input for microcontroller command.
|
54
|
RFs
(O
Detect RF; output for RF level detection.
55
FSS
(Focus Search Mode) = search/+search against reference voltage switching pin.
(Not used)
| os7)
|
REFECS{'*d*Cd
For connecting pass capacitor to reference voltage.
R
Reference voltage output.
F2
oo
For setting disk defect-detection time constant.
Q
onnects to capacitor for RF signal peak hold.
onnects to capacitor for RF signal bottom hold.
Output for APC circuit.
S
vccl
Vv
L
LDD
LD
Input for APC circuit.
VCC pin for RF system.
[=
Ea
Pagid
—52-
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