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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -68
Q103 : F2628E-01 (XM Digital Transceiver)
BLOCK DIAGRAM
3.3V
GND
COMM_TX_P
COMM_TX_M
COMM_RX_P
COMM_RX_M
LINKACTIVE (M=o, S=o)
COMM_TX_EN (M=o, S=o)
OSC_IN
OSC_OUT
PIN CONFIGURATION
SC_TX_OUT
SC_RX_IN
RFU (I2C_SCL)
RFU (I2C_SDA)
ANT_REV
RESET#
SLAVE_SEL
OSC
RAM
LSDP
1
VSS
2
3
VDD
4
5
6
XM/DT IC
7
VDD
8
9
10
VSS
11
12
I2S_OCLK (M=o, S=n/u)
I2S_LRCLK (M=o; S=i)
Inter-IC
I2S_SCLK (M=o; S=i)
Sound
I2S_DATA (M=o; S=i)
(I2S)
I2S_RATE (M=o, S=n/u)
MUTE (M=o, S=n/u)
High Speed
HSDP_EN# (M=o; S=i)
Data Port
HSDP_CLK (M=o; S=i)
(HSDP)
HSDP_DATA (M=o; S=i)
Low Speed
Data Port
LSDP (M=o; S=i)
(LSDP)
SAII_REQ (M=i; S=o)
SAII
SAII_CLK (M=o; S=i)
SAII_DATA (M=o; S=i)
Sys Ctrlr
SC_RX_IN (M=i, S=i)
(CBM)
SC_TX_OUT (M=o, S=o)
Bus I/F
SC_RATE (M=i, S=o)
RESET# (M=i, S=i)
ANT_REV (M=o,S=n/u)
DT4_MODE (M=i, S=i)
Misc Status
SLAVE_SEL (M=i, S=i)
& Control
TEST (M=i, S=i)
(RFU –I2C_SCL)
(RFU –I2C_SDA)
36
HSDP_EN#
35
DT4_MODE
34
HSDP_CLK
33
VDD
32
HSDP_DATA
31
VSS
30
TEST
29
SC_RATE
28
OSC_IN
27
VDD
26
OSC_OUT
25
VSS
TX-SR875
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