Introduction; Functionality; Figure 2-1. Tsw14J59Evm - Texas Instruments SW14J59EVM JESD204C User Manual

Introduction

1 Introduction
The TI TSW14J59 evaluation module (EVM) is a next-generation pattern generator and data capture card used
to evaluate performances of the new TI JESD204C_B device family of high-speed analog-to-digital converters
(ADC) and digital-to-analog converters (DAC). For an ADC, by capturing the sampled data over a JESD204C_B
interface when using a high-quality, low-jitter clock, and a high-quality input frequency, the TSW14J59 can be
used to demonstrate data sheet performance specifications. Using the TI
can be dynamically configurable to support lane speeds from 1Gbps to 32Gbps, from 1 to 16 lanes. Together
with the accompanying High-Speed Data Converter Pro Graphic User Interface
complete system that captures and evaluates data samples from ADC EVMs, generates and sends desired test
patterns to DAC EVMs, and perform both tasks at the same time with AFE EVMs (transceiver mode).

2 Functionality

The TSW14J59EVM has a single industry standard FMC+ connector that interfaces directly with TI JESD204B/C
ADC, DAC, and AFE EVMs. The FMC+ carrier connector is compatible with the FMC mezzanine connector.
When used with an ADC EVM, high-speed serial data is captured, deserialized and formatted by a Xilinx
Kintex ® UltraScale ® + FPGA. The data is then stored into an external DDR4 memory bank, enabling the
TSW14J59 to store up to 1.536G, 16-bit data samples. To acquire data on a host PC, the FPGA reads the
data from memory and transmits on a high-speed 32-bit parallel interface. An on-board high-speed USB 3.0 to
parallel converter bridges the FPGA interface to the host PC and GUI.
In pattern generator mode, the TSW14J59 generates the desired test patterns for DAC EVMs under test. These
patterns are sent from the host PC over the USB interface to the TSW14J59. The FPGA stores the data received
into the board DDR4 memory module. The data from memory is then read by the FPGA and transmitted to a
DAC EVM across the FMC+ interface connector. The board contains two 200-MHz oscillators used to generate
the DDR4 reference clock and a general purpose clock. Figure 2-1 shows the TI TSW14J59 evaluation module.
2 TSW14J59EVM JESD204C Data Capture and Pattern Generator Card

Figure 2-1. TSW14J59EVM

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JESD204C IP core, the TSW14J59
(GUI), the TSW14J59 is a
SLWU095 – APRIL 2023
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